commit 9cae6d97d933f648fc7545dec65c7a25dc1f1a03
author Cindy Chen <chencindy@opentitan.org> Thu Mar 02 14:43:17 2023 -0800
committer Cindy Chen <cindy.chen0316@gmail.com> Fri Mar 03 13:42:48 2023 -0800
tree 6dc2dde4a4786ad6553fa5c700e1f0299ea55786
parent 5aba85ae4b645f7cf3bb592dd522e88c5b659bfa

[dv/chip] Fix sw test naming convention

All sw tests under sw/device/test/sim_dv does not have prefix
`chip_sw_` except `chip_sw_lc_ctrl_scrap_test`. So I removed the prefix.
This prefix only applies to hw sv tests.

Signed-off-by: Cindy Chen <chencindy@opentitan.org>

hw/top_earlgrey/dv/chip_sim_cfg.hjson

diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
index 9f460b2..c4259d4 100644
--- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson
+++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
@@ -756,7 +756,7 @@
     {
       name: chip_sw_lc_ctrl_rma_to_scrap
       uvm_test_seq: chip_sw_lc_ctrl_scrap_vseq
-      sw_images: ["//sw/device/tests/sim_dv:chip_sw_lc_ctrl_scrap_test:1"]
+      sw_images: ["//sw/device/tests/sim_dv:lc_ctrl_scrap_test:1"]
       en_run_modes: ["sw_test_mode_test_rom"]
       run_opts: ["+bypass_alert_ready_to_end_check=1",
                  "+src_dec_state=DecLcStRma"]
@@ -765,7 +765,7 @@
     {
       name: chip_sw_lc_ctrl_raw_to_scrap
       uvm_test_seq: chip_sw_lc_ctrl_scrap_vseq
-      sw_images: ["//sw/device/tests/sim_dv:chip_sw_lc_ctrl_scrap_test:1"]
+      sw_images: ["//sw/device/tests/sim_dv:lc_ctrl_scrap_test:1"]
       en_run_modes: ["sw_test_mode_test_rom"]
       run_opts: ["+bypass_alert_ready_to_end_check=1",
                  "+src_dec_state=DecLcStRaw"]
@@ -774,7 +774,7 @@
     {
       name: chip_sw_lc_ctrl_test_locked0_to_scrap
       uvm_test_seq: chip_sw_lc_ctrl_scrap_vseq
-      sw_images: ["//sw/device/tests/sim_dv:chip_sw_lc_ctrl_scrap_test:1"]
+      sw_images: ["//sw/device/tests/sim_dv:lc_ctrl_scrap_test:1"]
       en_run_modes: ["sw_test_mode_test_rom"]
       run_opts: ["+bypass_alert_ready_to_end_check=1",
                  "+src_dec_state=DecLcStTestLocked0"]
@@ -783,7 +783,7 @@
     {
       name: chip_sw_lc_ctrl_rand_to_scrap
       uvm_test_seq: chip_sw_lc_ctrl_scrap_vseq
-      sw_images: ["//sw/device/tests/sim_dv:chip_sw_lc_ctrl_scrap_test:1"]
+      sw_images: ["//sw/device/tests/sim_dv:lc_ctrl_scrap_test:1"]
       en_run_modes: ["sw_test_mode_test_rom"]
       run_opts: ["+bypass_alert_ready_to_end_check=1"]
       reseed: 3

sw/device/tests/sim_dv/BUILD

diff --git a/sw/device/tests/sim_dv/BUILD b/sw/device/tests/sim_dv/BUILD
index 2d5ee1e..0be24d4 100644
--- a/sw/device/tests/sim_dv/BUILD
+++ b/sw/device/tests/sim_dv/BUILD
@@ -272,8 +272,8 @@
 )
 
 opentitan_functest(
-    name = "chip_sw_lc_ctrl_scrap_test",
-    srcs = ["chip_sw_lc_ctrl_scrap_test.c"],
+    name = "lc_ctrl_scrap_test",
+    srcs = ["lc_ctrl_scrap_test.c"],
     targets = ["dv"],
     deps = [
         "//hw/top_earlgrey/sw/autogen:top_earlgrey",

sw/device/tests/sim_dv/lc_ctrl_scrap_test.c

diff --git a/sw/device/tests/sim_dv/chip_sw_lc_ctrl_scrap_test.c b/sw/device/tests/sim_dv/lc_ctrl_scrap_test.c
similarity index 100%
rename from sw/device/tests/sim_dv/chip_sw_lc_ctrl_scrap_test.c
rename to sw/device/tests/sim_dv/lc_ctrl_scrap_test.c