[keymgr] keymgr integration into top
- integrate keymgr
- hook-up flash seed bus to keymgr
Signed-off-by: Timothy Chen <timothytim@google.com>
[keymgr] update package to pass verilator
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.hjson b/hw/ip/flash_ctrl/data/flash_ctrl.hjson
index df33591..08e6871 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.hjson
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.hjson
@@ -50,6 +50,13 @@
package: "pwrmgr_pkg"
},
+ { struct: "keymgr_flash",
+ type: "uni",
+ name: "keymgr",
+ act: "req",
+ package: "flash_ctrl_pkg"
+ }
+
],
param_list: [
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
index e77522a..dbd9a9b 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
@@ -20,13 +20,14 @@
input flash_rsp_t flash_i,
output flash_req_t flash_o,
- // otp/lc/pwrmgr Interface
+ // otp/lc/pwrmgr/keymgr Interface
input otp_flash_t otp_i,
input lc_flash_req_t lc_i,
output lc_flash_rsp_t lc_o,
input pwrmgr_pkg::pwr_flash_req_t pwrmgr_i,
output pwrmgr_pkg::pwr_flash_rsp_t pwrmgr_o,
input edn_entropy_t edn_i,
+ output keymgr_flash_t keymgr_o,
// Interrupts
output logic intr_prog_empty_o, // Program fifo is empty
@@ -300,7 +301,7 @@
.rand_i(rand_val),
// outgoing seeds
- .seeds_o(),
+ .seeds_o(keymgr_o.seeds),
.seed_err_o(), // TBD hook-up to Err code register
// phase indication
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv
index 0017ee6..a8278f7 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv
@@ -300,6 +300,11 @@
logic [BusWidth-1:0] rma_ack_token;
} lc_flash_rsp_t;
+ // flash_ctrl to keymgr
+ typedef struct packed {
+ logic [NumSeeds-1:0][SeedWidth-1:0] seeds;
+ } keymgr_flash_t;
+
// place holder for interface to EDN, replace with real one later
typedef struct packed {
logic valid;
diff --git a/hw/ip/keymgr/data/keymgr.hjson b/hw/ip/keymgr/data/keymgr.hjson
index 426a887..0eed12d 100644
--- a/hw/ip/keymgr/data/keymgr.hjson
+++ b/hw/ip/keymgr/data/keymgr.hjson
@@ -52,11 +52,11 @@
act: "rcv",
package: "keymgr_pkg",
},
- { struct: "flash_key",
+ { struct: "keymgr_flash",
type: "uni",
name: "flash",
act: "rcv",
- package: "keymgr_pkg",
+ package: "flash_ctrl_pkg",
},
],
diff --git a/hw/ip/keymgr/keymgr_pkg.core b/hw/ip/keymgr/keymgr_pkg.core
index 0f09ed5..bb1118f 100644
--- a/hw/ip/keymgr/keymgr_pkg.core
+++ b/hw/ip/keymgr/keymgr_pkg.core
@@ -9,6 +9,7 @@
files_rtl:
depend:
- lowrisc:constants:top_pkg
+ - lowrisc:ip:flash_ctrl_pkg
files:
- rtl/keymgr_pkg.sv
file_type: systemVerilogSource
diff --git a/hw/ip/keymgr/rtl/keymgr.sv b/hw/ip/keymgr/rtl/keymgr.sv
index 0c14374..0ab97ce 100644
--- a/hw/ip/keymgr/rtl/keymgr.sv
+++ b/hw/ip/keymgr/rtl/keymgr.sv
@@ -29,7 +29,7 @@
// the following signals should eventually be wrapped into structs from other modules
input lc_data_t lc_i,
input otp_data_t otp_i,
- input flash_key_t flash_i,
+ input flash_ctrl_pkg::keymgr_flash_t flash_i,
// interrupts and alerts
output logic intr_op_done_o,
@@ -184,14 +184,18 @@
end
// Advance to creator_root_key
+ logic [KeyWidth-1:0] creator_seed;
+ assign creator_seed = flash_i.seeds[flash_ctrl_pkg::CreatorSeedIdx];
assign adv_matrix[Creator] = AdvDataWidth'({reg2hw.rom_ext_desc,
RevisionSecret,
otp_i.devid,
lc_i.health_state,
- flash_i.div_key});
+ creator_seed});
// Advance to owner_intermediate_key
- assign adv_matrix[OwnerInt] = AdvDataWidth'({reg2hw.software_binding,flash_i.owner_secret});
+ logic [KeyWidth-1:0] owner_seed;
+ assign owner_seed = flash_i.seeds[flash_ctrl_pkg::OwnerSeedIdx];
+ assign adv_matrix[OwnerInt] = AdvDataWidth'({reg2hw.software_binding,owner_seed});
// Advance to owner_key
assign adv_matrix[Owner] = AdvDataWidth'(reg2hw.software_binding);
@@ -326,6 +330,8 @@
/////////////////////////////////////
prim_intr_hw #(.Width(1)) u_intr_op_done (
+ .clk_i,
+ .rst_ni,
.event_intr_i (op_done),
.reg2hw_intr_enable_q_i (reg2hw.intr_enable.op_done.q),
.reg2hw_intr_test_q_i (reg2hw.intr_test.op_done.q),
@@ -356,6 +362,8 @@
// interrupts are only generated on changes to avoid interrupt storms
prim_intr_hw #(.Width(1)) u_err_code (
+ .clk_i,
+ .rst_ni,
.event_intr_i (err_code != err_code_q),
.reg2hw_intr_enable_q_i (reg2hw.intr_enable.err.q),
.reg2hw_intr_test_q_i (reg2hw.intr_test.err.q),
diff --git a/hw/ip/keymgr/rtl/keymgr_pkg.sv b/hw/ip/keymgr/rtl/keymgr_pkg.sv
index 5aa974f..8d93b3e 100644
--- a/hw/ip/keymgr/rtl/keymgr_pkg.sv
+++ b/hw/ip/keymgr/rtl/keymgr_pkg.sv
@@ -122,7 +122,7 @@
logic [KeyWidth-1:0] digest_share1;
} kmac_data_rsp_t;
- parameter kmac_data_rsp_t KMAC_DATA_RSP_DEFAULT = ' {
+ parameter kmac_data_rsp_t KMAC_DATA_RSP_DEFAULT = '{
ready: 1'b1,
done: 1'b1,
digest_share0: KeyWidth'(32'hDEADBEEF),
@@ -136,7 +136,7 @@
logic keymgr_en;
} lc_data_t;
- parameter lc_data_t LC_DATA_DEFAULT = ' {
+ parameter lc_data_t LC_DATA_DEFAULT = '{
health_state: '0,
keymgr_en: 1'b1
};
@@ -146,7 +146,7 @@
logic [KeyWidth-1:0] root_key;
} otp_data_t;
- parameter otp_data_t OTP_DATA_DEFAULT = ' {
+ parameter otp_data_t OTP_DATA_DEFAULT = '{
devid: '0,
root_key: '0
};
@@ -156,7 +156,7 @@
logic [KeyWidth-1:0] owner_secret;
} flash_key_t;
- parameter flash_key_t FLASH_KEY_DEFAULT = ' {
+ parameter flash_key_t FLASH_KEY_DEFAULT = '{
div_key: '0,
owner_secret: '0
};
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index 282cd80..7c815da 100644
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -406,10 +406,11 @@
// e.g flash_ctrl0.flash: [flash_phy0.flash_ctrl]
inter_module: {
'connect': {
- 'flash_ctrl.flash': ['eflash.flash_ctrl'],
- 'pwrmgr.pwr_flash': ['flash_ctrl.pwrmgr'],
- 'pwrmgr.pwr_rst' : ['rstmgr.pwr'],
- 'pwrmgr.pwr_clk' : ['clkmgr.pwr'],
+ 'flash_ctrl.flash' : ['eflash.flash_ctrl'],
+ 'pwrmgr.pwr_flash' : ['flash_ctrl.pwrmgr'],
+ 'pwrmgr.pwr_rst' : ['rstmgr.pwr'],
+ 'pwrmgr.pwr_clk' : ['clkmgr.pwr'],
+ 'flash_ctrl.keymgr': ['keymgr.flash']
}
// top is to connect to top net/struct.
