| commit | 9a6fc4681cfc0ac1bbb2ef29e6b94c963b0dcc53 | [log] [tgz] |
|---|---|---|
| author | Greg Chadwick <gac@lowrisc.org> | Tue Aug 10 15:42:16 2021 +0100 |
| committer | Greg Chadwick <mail@gregchadwick.co.uk> | Thu Aug 12 13:47:17 2021 +0100 |
| tree | ebf8c4532e4eebe99881b7de1991b558f24e2e14 | |
| parent | 21721e32cc6cc388dbc2f3460835efd0c57bc826 [diff] |
[otbn] Fix bug with indirect register read timing For a load read the indirect register index for the destination the first cycle of the instruction. Otherwise if it is incremented in the first cycle the wrong register index is used. Fixes #7639 Signed-off-by: Greg Chadwick <gac@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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