[dv/otp_ctrl] Update csr test and exclusions
This PR updates csr exclusions, instead of test CSRs right after init,
this exclusion will test CSRs after OTP_INIT. Waiting until otp_init
done is because we want to reuse the same settings for csr memory
automation tests.
This PR also updates a few tasks based on updated otp_ctrl_base_vseq.sv
Signed-off-by: Cindy Chen <chencindy@google.com>
diff --git a/hw/ip/otp_ctrl/data/otp_ctrl.hjson b/hw/ip/otp_ctrl/data/otp_ctrl.hjson
index 1fde18b..b348802 100644
--- a/hw/ip/otp_ctrl/data/otp_ctrl.hjson
+++ b/hw/ip/otp_ctrl/data/otp_ctrl.hjson
@@ -216,6 +216,8 @@
swaccess: "ro",
hwaccess: "hwo",
hwext: "true",
+ tags: [ // OTP internal HW can modify status register
+ "excl:CsrAllTests:CsrExclCheck"],
fields: [
{ bits: "0"
name: "CREATOR_SW_CFG_ERROR"
@@ -414,8 +416,10 @@
swaccess: "ro",
hwaccess: "hwo",
hwext: "true",
- tags: [ // DAI interface will set it to 0 during initialization,
- // so even after reset, the value might not be the reset value
+ tags: [ // OTP internal HW will set this enable register to 0 when OTP is not under IDLE
+ // state, so could not auto-predict its value
+ // TODO: change the exclusion to CsrNonInitTests once top-level triggers otp_init
+ // after reset
"excl:CsrAllTests:CsrExclCheck"],
fields: [
{
@@ -436,9 +440,8 @@
hwqe: "true",
hwext: "true",
regwen: "DIRECT_ACCESS_REGWEN",
- tags: [ // The enable register "DIRECT_ACCESS_REGWEN" is HW controlled,
- // so not able to predict this register value automatically
- "excl:CsrNonInitTests:CsrExclCheck"],
+ tags: [ // Write to DIRECT_ACCESS_CMD randomly might cause OTP_ERRORs and illegal sequences
+ "excl:CsrNonInitTests:CsrExclWrite"],
fields: [
{ bits: "0",
name: "READ",
diff --git a/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv b/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv
index bee784a..8733962 100644
--- a/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv
+++ b/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_base_vseq.sv
@@ -34,7 +34,6 @@
virtual task otp_ctrl_init();
// reset memory to avoid readout X
cfg.mem_bkdr_vif.clear_mem();
- csr_wr(ral.intr_enable, en_intr);
endtask
// this task triggers an OTP write sequence via the DAI interface
diff --git a/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_common_vseq.sv b/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_common_vseq.sv
index 5c8b898..237ef17 100644
--- a/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_common_vseq.sv
+++ b/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_common_vseq.sv
@@ -10,6 +10,13 @@
}
`uvm_object_new
+ virtual task dut_init(string reset_kind = "HARD");
+ super.dut_init(reset_kind);
+ // drive pwr_otp_req pin
+ cfg.pwr_otp_vif.drive_pin(0, 1);
+ wait(cfg.pwr_otp_vif.pins[2] == 1);
+ endtask
+
virtual task body();
run_common_vseq_wrapper(num_trans);
endtask : body
diff --git a/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_sanity_vseq.sv b/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_sanity_vseq.sv
index 3392e9d..90484a9 100644
--- a/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_sanity_vseq.sv
+++ b/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_sanity_vseq.sv
@@ -42,6 +42,7 @@
cfg.pwr_otp_vif.drive_pin(0, 1);
wait(cfg.pwr_otp_vif.pins[2] == 1);
cfg.lc_provision_en_vif.drive(lc_ctrl_pkg::On);
+ csr_wr(ral.intr_enable, en_intr);
endtask
virtual task pre_start();
diff --git a/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_wake_up_vseq.sv b/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_wake_up_vseq.sv
index 19f2be7..f534b3c 100644
--- a/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_wake_up_vseq.sv
+++ b/hw/ip/otp_ctrl/dv/env/seq_lib/otp_ctrl_wake_up_vseq.sv
@@ -10,6 +10,7 @@
virtual task otp_ctrl_init();
super.otp_ctrl_init();
+ csr_wr(ral.intr_enable, en_intr);
// drive pwr_otp_req pin
cfg.pwr_otp_vif.drive_pin(0, 1);
endtask
