[sw/silicon_creator] Switch hmac to abs_mmio
Signed-off-by: Miguel Osorio <miguelosorio@google.com>
diff --git a/sw/device/silicon_creator/lib/drivers/hmac.c b/sw/device/silicon_creator/lib/drivers/hmac.c
index 106bb8c..2cc939c 100644
--- a/sw/device/silicon_creator/lib/drivers/hmac.c
+++ b/sw/device/silicon_creator/lib/drivers/hmac.c
@@ -6,22 +6,21 @@
#include "sw/device/lib/base/bitfield.h"
#include "sw/device/lib/base/memory.h"
-#include "sw/device/lib/base/mmio.h"
+#include "sw/device/silicon_creator/lib/base/abs_mmio.h"
#include "sw/device/silicon_creator/lib/error.h"
#include "hmac_regs.h" // Generated.
+#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
-rom_error_t hmac_sha256_init(const hmac_t *hmac) {
- if (hmac == NULL) {
- return kErrorHmacInvalidArgument;
- }
-
+void hmac_sha256_init(void) {
// Clear the config, stopping the SHA engine.
- mmio_region_write32(hmac->base_addr, HMAC_CFG_REG_OFFSET, 0u);
+ abs_mmio_write32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_CFG_REG_OFFSET, 0u);
// Disable and clear interrupts. INTR_STATE register is rw1c.
- mmio_region_write32(hmac->base_addr, HMAC_INTR_ENABLE_REG_OFFSET, 0u);
- mmio_region_write32(hmac->base_addr, HMAC_INTR_STATE_REG_OFFSET, UINT32_MAX);
+ abs_mmio_write32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_INTR_ENABLE_REG_OFFSET,
+ 0u);
+ abs_mmio_write32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_INTR_STATE_REG_OFFSET,
+ UINT32_MAX);
uint32_t reg = 0;
reg = bitfield_bit32_write(reg, HMAC_CFG_DIGEST_SWAP_BIT, false);
@@ -29,62 +28,63 @@
reg = bitfield_bit32_write(reg, HMAC_CFG_ENDIAN_SWAP_BIT, true);
reg = bitfield_bit32_write(reg, HMAC_CFG_SHA_EN_BIT, true);
reg = bitfield_bit32_write(reg, HMAC_CFG_HMAC_EN_BIT, false);
- mmio_region_write32(hmac->base_addr, HMAC_CFG_REG_OFFSET, reg);
+ abs_mmio_write32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_CFG_REG_OFFSET, reg);
reg = 0;
reg = bitfield_bit32_write(reg, HMAC_CMD_HASH_START_BIT, true);
- mmio_region_write32(hmac->base_addr, HMAC_CMD_REG_OFFSET, reg);
-
- return kErrorOk;
+ abs_mmio_write32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_CMD_REG_OFFSET, reg);
}
-rom_error_t hmac_sha256_update(const hmac_t *hmac, const void *data,
- size_t len) {
- if (hmac == NULL || data == NULL) {
+rom_error_t hmac_sha256_update(const void *data, size_t len) {
+ if (data == NULL) {
return kErrorHmacInvalidArgument;
}
const uint8_t *data_sent = (const uint8_t *)data;
// Individual byte writes are needed if the buffer isn't word aligned.
for (; len != 0 && (uintptr_t)data_sent & 3; --len) {
- mmio_region_write8(hmac->base_addr, HMAC_MSG_FIFO_REG_OFFSET, *data_sent++);
+ abs_mmio_write8(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_MSG_FIFO_REG_OFFSET,
+ *data_sent++);
}
for (; len >= sizeof(uint32_t); len -= sizeof(uint32_t)) {
// FIXME: read_32 does not work for unittests.
uint32_t data_aligned = *(const uint32_t *)data_sent;
- mmio_region_write32(hmac->base_addr, HMAC_MSG_FIFO_REG_OFFSET,
- data_aligned);
+ abs_mmio_write32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_MSG_FIFO_REG_OFFSET,
+ data_aligned);
data_sent += sizeof(uint32_t);
}
// Handle non-32bit aligned bytes at the end of the buffer.
for (; len != 0; --len) {
- mmio_region_write8(hmac->base_addr, HMAC_MSG_FIFO_REG_OFFSET, *data_sent++);
+ abs_mmio_write8(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_MSG_FIFO_REG_OFFSET,
+ *data_sent++);
}
return kErrorOk;
}
-rom_error_t hmac_sha256_final(const hmac_t *hmac, hmac_digest_t *digest) {
- if (hmac == NULL || digest == NULL) {
+rom_error_t hmac_sha256_final(hmac_digest_t *digest) {
+ if (digest == NULL) {
return kErrorHmacInvalidArgument;
}
uint32_t reg = 0;
reg = bitfield_bit32_write(reg, HMAC_CMD_HASH_PROCESS_BIT, true);
- mmio_region_write32(hmac->base_addr, HMAC_CMD_REG_OFFSET, reg);
+ abs_mmio_write32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_CMD_REG_OFFSET, reg);
do {
- reg = mmio_region_read32(hmac->base_addr, HMAC_INTR_STATE_REG_OFFSET);
+ reg = abs_mmio_read32(TOP_EARLGREY_HMAC_BASE_ADDR +
+ HMAC_INTR_STATE_REG_OFFSET);
} while (!bitfield_bit32_read(reg, HMAC_INTR_STATE_HMAC_DONE_BIT));
- mmio_region_write32(hmac->base_addr, HMAC_INTR_STATE_REG_OFFSET, reg);
+ abs_mmio_write32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_INTR_STATE_REG_OFFSET,
+ reg);
// Read the digest in reverse to preserve the numerical value.
// The least significant word is at HMAC_DIGEST_7_REG_OFFSET.
for (size_t i = 0; i < ARRAYSIZE(digest->digest); ++i) {
- digest->digest[i] = mmio_region_read32(
- hmac->base_addr, HMAC_DIGEST_7_REG_OFFSET - (i * sizeof(uint32_t)));
+ digest->digest[i] =
+ abs_mmio_read32(TOP_EARLGREY_HMAC_BASE_ADDR + HMAC_DIGEST_7_REG_OFFSET -
+ (i * sizeof(uint32_t)));
}
-
return kErrorOk;
}
diff --git a/sw/device/silicon_creator/lib/drivers/hmac.h b/sw/device/silicon_creator/lib/drivers/hmac.h
index 9eed615..34fa97c 100644
--- a/sw/device/silicon_creator/lib/drivers/hmac.h
+++ b/sw/device/silicon_creator/lib/drivers/hmac.h
@@ -7,22 +7,13 @@
#include <stddef.h>
#include <stdint.h>
-#include "sw/device/lib/base/mmio.h"
#include "sw/device/silicon_creator/lib/error.h"
#ifdef __cplusplus
extern "C" {
#endif
-/**
- * Initialization parameters for HMAC.
- */
-typedef struct hmac {
- /**
- * The base address for the HMAC hardware registers.
- */
- mmio_region_t base_addr;
-} hmac_t;
+#define HMAC_WARN_UNUSED_RESULT __attribute__((warn_unused_result))
/**
* A typed representation of the HMAC digest.
@@ -37,11 +28,8 @@
* This function resets the HMAC module to clear the digest register.
* It then configures the HMAC block in SHA256 mode with little endian
* data input and digest output.
- *
- * @param hmac A HMAC handle.
- * @return The result of the operation.
*/
-rom_error_t hmac_sha256_init(const hmac_t *hmac);
+void hmac_sha256_init(void);
/**
* Sends `len` bytes from `data` to the SHA2-256 function.
@@ -50,22 +38,21 @@
* FIFO. Since the this function is meant to run in blocking mode,
* polling for FIFO status is equivalent to stalling on FIFO write.
*
- * @param hmac A HMAC handle
* @param data Buffer to copy data from.
* @param len size of the `data` buffer.
* @return The result of the operation.
*/
-rom_error_t hmac_sha256_update(const hmac_t *hmac, const void *data,
- size_t len);
+HMAC_WARN_UNUSED_RESULT
+rom_error_t hmac_sha256_update(const void *data, size_t len);
/**
* Finalizes SHA256 operation and writes `digest` buffer.
*
- * @param hmac A HMAC handle.
* @param[out] digest Buffer to copy digest to.
* @return The result of the operation.
*/
-rom_error_t hmac_sha256_final(const hmac_t *hmac, hmac_digest_t *digest);
+HMAC_WARN_UNUSED_RESULT
+rom_error_t hmac_sha256_final(hmac_digest_t *digest);
#ifdef __cplusplus
}
diff --git a/sw/device/silicon_creator/lib/drivers/hmac_unittest.cc b/sw/device/silicon_creator/lib/drivers/hmac_unittest.cc
index 8e22f9e..cc083d3 100644
--- a/sw/device/silicon_creator/lib/drivers/hmac_unittest.cc
+++ b/sw/device/silicon_creator/lib/drivers/hmac_unittest.cc
@@ -9,51 +9,46 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
-#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/silicon_creator/lib/base/mock_abs_mmio.h"
#include "sw/device/silicon_creator/lib/error.h"
#include "hmac_regs.h" // Generated.
+#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
namespace hmac_unittest {
namespace {
-using ::mock_mmio::MmioTest;
using ::testing::ElementsAreArray;
using ::testing::Test;
-class HmacTest : public Test, public MmioTest {
+class HmacTest : public mask_rom_test::MaskRomTest {
protected:
- hmac_t hmac_ = {.base_addr = dev().region()};
+ uint32_t base_ = TOP_EARLGREY_HMAC_BASE_ADDR;
+ mask_rom_test::MockAbsMmio mmio_;
};
class Sha256InitTest : public HmacTest {};
-TEST_F(Sha256InitTest, NullArgs) {
- EXPECT_EQ(hmac_sha256_init(nullptr), kErrorHmacInvalidArgument);
-}
-
TEST_F(Sha256InitTest, Initialize) {
- EXPECT_WRITE32(HMAC_CFG_REG_OFFSET, 0u);
- EXPECT_WRITE32(HMAC_INTR_ENABLE_REG_OFFSET, 0u);
- EXPECT_WRITE32(HMAC_INTR_STATE_REG_OFFSET,
- std::numeric_limits<uint32_t>::max());
- EXPECT_WRITE32(HMAC_CFG_REG_OFFSET, {
- {HMAC_CFG_DIGEST_SWAP_BIT, false},
- {HMAC_CFG_ENDIAN_SWAP_BIT, true},
- {HMAC_CFG_SHA_EN_BIT, true},
- {HMAC_CFG_HMAC_EN_BIT, false},
- });
- EXPECT_WRITE32(HMAC_CMD_REG_OFFSET, {{HMAC_CMD_HASH_START_BIT, true}});
- EXPECT_EQ(hmac_sha256_init(&hmac_), kErrorOk);
+ EXPECT_ABS_WRITE32(mmio_, base_ + HMAC_CFG_REG_OFFSET, 0u);
+ EXPECT_ABS_WRITE32(mmio_, base_ + HMAC_INTR_ENABLE_REG_OFFSET, 0u);
+ EXPECT_ABS_WRITE32(mmio_, base_ + HMAC_INTR_STATE_REG_OFFSET,
+ std::numeric_limits<uint32_t>::max());
+ EXPECT_ABS_WRITE32(mmio_, base_ + HMAC_CFG_REG_OFFSET,
+ {
+ {HMAC_CFG_DIGEST_SWAP_BIT, false},
+ {HMAC_CFG_ENDIAN_SWAP_BIT, true},
+ {HMAC_CFG_SHA_EN_BIT, true},
+ {HMAC_CFG_HMAC_EN_BIT, false},
+ });
+ EXPECT_ABS_WRITE32(mmio_, base_ + HMAC_CMD_REG_OFFSET,
+ {{HMAC_CMD_HASH_START_BIT, true}});
+ hmac_sha256_init();
}
class Sha256UpdateTest : public HmacTest {};
TEST_F(Sha256UpdateTest, NullArgs) {
- EXPECT_EQ(hmac_sha256_update(&hmac_, nullptr, 0), kErrorHmacInvalidArgument);
-
- uint32_t data;
- EXPECT_EQ(hmac_sha256_update(nullptr, &data, sizeof(uint32_t)),
- kErrorHmacInvalidArgument);
+ EXPECT_EQ(hmac_sha256_update(nullptr, 0), kErrorHmacInvalidArgument);
}
TEST_F(Sha256UpdateTest, SendData) {
@@ -63,30 +58,27 @@
};
// Trigger 8bit aligned writes.
- EXPECT_WRITE8(HMAC_MSG_FIFO_REG_OFFSET, 0x01);
- EXPECT_WRITE8(HMAC_MSG_FIFO_REG_OFFSET, 0x02);
- EXPECT_EQ(hmac_sha256_update(&hmac_, &kData[1], 2), kErrorOk);
+ EXPECT_ABS_WRITE8(mmio_, base_ + HMAC_MSG_FIFO_REG_OFFSET, 0x01);
+ EXPECT_ABS_WRITE8(mmio_, base_ + HMAC_MSG_FIFO_REG_OFFSET, 0x02);
+ EXPECT_EQ(hmac_sha256_update(&kData[1], 2), kErrorOk);
// Trigger a single 32bit aligned write.
- EXPECT_WRITE32(HMAC_MSG_FIFO_REG_OFFSET, 0x03020100);
- EXPECT_EQ(hmac_sha256_update(&hmac_, &kData[0], 4), kErrorOk);
+ EXPECT_ABS_WRITE32(mmio_, base_ + HMAC_MSG_FIFO_REG_OFFSET, 0x03020100);
+ EXPECT_EQ(hmac_sha256_update(&kData[0], 4), kErrorOk);
// Trigger 8bit/32bit/8bit sequence.
- EXPECT_WRITE8(HMAC_MSG_FIFO_REG_OFFSET, 0x02);
- EXPECT_WRITE8(HMAC_MSG_FIFO_REG_OFFSET, 0x03);
- EXPECT_WRITE32(HMAC_MSG_FIFO_REG_OFFSET, 0x07060504);
- EXPECT_WRITE8(HMAC_MSG_FIFO_REG_OFFSET, 0x08);
- EXPECT_WRITE8(HMAC_MSG_FIFO_REG_OFFSET, 0x09);
- EXPECT_EQ(hmac_sha256_update(&hmac_, &kData[2], 8), kErrorOk);
+ EXPECT_ABS_WRITE8(mmio_, base_ + HMAC_MSG_FIFO_REG_OFFSET, 0x02);
+ EXPECT_ABS_WRITE8(mmio_, base_ + HMAC_MSG_FIFO_REG_OFFSET, 0x03);
+ EXPECT_ABS_WRITE32(mmio_, base_ + HMAC_MSG_FIFO_REG_OFFSET, 0x07060504);
+ EXPECT_ABS_WRITE8(mmio_, base_ + HMAC_MSG_FIFO_REG_OFFSET, 0x08);
+ EXPECT_ABS_WRITE8(mmio_, base_ + HMAC_MSG_FIFO_REG_OFFSET, 0x09);
+ EXPECT_EQ(hmac_sha256_update(&kData[2], 8), kErrorOk);
}
class Sha256FinalTest : public HmacTest {};
TEST_F(Sha256FinalTest, NullArgs) {
- EXPECT_EQ(hmac_sha256_final(&hmac_, nullptr), kErrorHmacInvalidArgument);
-
- hmac_digest_t digest;
- EXPECT_EQ(hmac_sha256_final(nullptr, &digest), kErrorHmacInvalidArgument);
+ EXPECT_EQ(hmac_sha256_final(nullptr), kErrorHmacInvalidArgument);
}
TEST_F(Sha256FinalTest, GetDigest) {
@@ -96,35 +88,44 @@
};
// Request digest.
- EXPECT_WRITE32(HMAC_CMD_REG_OFFSET, {{HMAC_CMD_HASH_PROCESS_BIT, true}});
+ EXPECT_ABS_WRITE32(mmio_, base_ + HMAC_CMD_REG_OFFSET,
+ {{HMAC_CMD_HASH_PROCESS_BIT, true}});
// Poll a couple of times before returning the result
- EXPECT_READ32(HMAC_INTR_STATE_REG_OFFSET,
- {
- {HMAC_INTR_STATE_HMAC_DONE_BIT, false},
- });
- EXPECT_READ32(HMAC_INTR_STATE_REG_OFFSET,
- {
- {HMAC_INTR_STATE_HMAC_DONE_BIT, true},
- });
- EXPECT_WRITE32(HMAC_INTR_STATE_REG_OFFSET,
- {
- {HMAC_INTR_STATE_HMAC_DONE_BIT, true},
- });
+ EXPECT_ABS_READ32(mmio_, base_ + HMAC_INTR_STATE_REG_OFFSET,
+ {
+ {HMAC_INTR_STATE_HMAC_DONE_BIT, false},
+ });
+ EXPECT_ABS_READ32(mmio_, base_ + HMAC_INTR_STATE_REG_OFFSET,
+ {
+ {HMAC_INTR_STATE_HMAC_DONE_BIT, true},
+ });
+ EXPECT_ABS_WRITE32(mmio_, base_ + HMAC_INTR_STATE_REG_OFFSET,
+ {
+ {HMAC_INTR_STATE_HMAC_DONE_BIT, true},
+ });
// Set expectations explicitly to ensure that the registers
// are contiguous.
- EXPECT_READ32(HMAC_DIGEST_7_REG_OFFSET, kExpectedDigest[0]);
- EXPECT_READ32(HMAC_DIGEST_6_REG_OFFSET, kExpectedDigest[1]);
- EXPECT_READ32(HMAC_DIGEST_5_REG_OFFSET, kExpectedDigest[2]);
- EXPECT_READ32(HMAC_DIGEST_4_REG_OFFSET, kExpectedDigest[3]);
- EXPECT_READ32(HMAC_DIGEST_3_REG_OFFSET, kExpectedDigest[4]);
- EXPECT_READ32(HMAC_DIGEST_2_REG_OFFSET, kExpectedDigest[5]);
- EXPECT_READ32(HMAC_DIGEST_1_REG_OFFSET, kExpectedDigest[6]);
- EXPECT_READ32(HMAC_DIGEST_0_REG_OFFSET, kExpectedDigest[7]);
+ EXPECT_ABS_READ32(mmio_, base_ + HMAC_DIGEST_7_REG_OFFSET,
+ kExpectedDigest[0]);
+ EXPECT_ABS_READ32(mmio_, base_ + HMAC_DIGEST_6_REG_OFFSET,
+ kExpectedDigest[1]);
+ EXPECT_ABS_READ32(mmio_, base_ + HMAC_DIGEST_5_REG_OFFSET,
+ kExpectedDigest[2]);
+ EXPECT_ABS_READ32(mmio_, base_ + HMAC_DIGEST_4_REG_OFFSET,
+ kExpectedDigest[3]);
+ EXPECT_ABS_READ32(mmio_, base_ + HMAC_DIGEST_3_REG_OFFSET,
+ kExpectedDigest[4]);
+ EXPECT_ABS_READ32(mmio_, base_ + HMAC_DIGEST_2_REG_OFFSET,
+ kExpectedDigest[5]);
+ EXPECT_ABS_READ32(mmio_, base_ + HMAC_DIGEST_1_REG_OFFSET,
+ kExpectedDigest[6]);
+ EXPECT_ABS_READ32(mmio_, base_ + HMAC_DIGEST_0_REG_OFFSET,
+ kExpectedDigest[7]);
hmac_digest_t got_digest;
- EXPECT_EQ(hmac_sha256_final(&hmac_, &got_digest), kErrorOk);
+ EXPECT_EQ(hmac_sha256_final(&got_digest), kErrorOk);
EXPECT_THAT(got_digest.digest, ElementsAreArray(kExpectedDigest));
}
diff --git a/sw/device/silicon_creator/lib/drivers/meson.build b/sw/device/silicon_creator/lib/drivers/meson.build
index bf97129..1e0b4f5 100644
--- a/sw/device/silicon_creator/lib/drivers/meson.build
+++ b/sw/device/silicon_creator/lib/drivers/meson.build
@@ -11,7 +11,7 @@
'hmac.c',
],
dependencies: [
- sw_lib_mmio,
+ sw_silicon_creator_lib_base_abs_mmio,
],
),
)
@@ -25,11 +25,11 @@
],
dependencies: [
sw_vendor_gtest,
- sw_lib_base_testing_mock_mmio,
+ sw_silicon_creator_lib_base_mock_abs_mmio,
],
native: true,
- c_args: ['-DMOCK_MMIO'],
- cpp_args: ['-DMOCK_MMIO'],
+ c_args: ['-DMOCK_ABS_MMIO'],
+ cpp_args: ['-DMOCK_ABS_MMIO'],
),
suite: 'mask_rom',
)
diff --git a/sw/device/silicon_creator/lib/drivers/mock_hmac.h b/sw/device/silicon_creator/lib/drivers/mock_hmac.h
index 7d8cfd5..a80ad0d 100644
--- a/sw/device/silicon_creator/lib/drivers/mock_hmac.h
+++ b/sw/device/silicon_creator/lib/drivers/mock_hmac.h
@@ -16,10 +16,9 @@
*/
class MockHmac {
public:
- MOCK_METHOD(rom_error_t, sha256_init, (const hmac_t *));
- MOCK_METHOD(rom_error_t, sha256_update,
- (const hmac_t *, const void *, size_t));
- MOCK_METHOD(rom_error_t, sha256_final, (const hmac_t *, hmac_digest_t *));
+ MOCK_METHOD(void, sha256_init, ());
+ MOCK_METHOD(rom_error_t, sha256_update, (const void *, size_t));
+ MOCK_METHOD(rom_error_t, sha256_final, (hmac_digest_t *));
virtual ~MockHmac() {}
};
@@ -29,17 +28,14 @@
extern "C" {
-rom_error_t hmac_sha256_init(const hmac_t *hmac) {
- return MockHmac::Instance().sha256_init(hmac);
+void hmac_sha256_init(void) { MockHmac::Instance().sha256_init(); }
+
+rom_error_t hmac_sha256_update(const void *data, size_t len) {
+ return MockHmac::Instance().sha256_update(data, len);
}
-rom_error_t hmac_sha256_update(const hmac_t *hmac, const void *data,
- size_t len) {
- return MockHmac::Instance().sha256_update(hmac, data, len);
-}
-
-rom_error_t hmac_sha256_final(const hmac_t *hmac, hmac_digest_t *digest) {
- return MockHmac::Instance().sha256_final(hmac, digest);
+rom_error_t hmac_sha256_final(hmac_digest_t *digest) {
+ return MockHmac::Instance().sha256_final(digest);
}
} // extern "C"
diff --git a/sw/device/silicon_creator/mask_rom/mask_rom.c b/sw/device/silicon_creator/mask_rom/mask_rom.c
index 3929d5b..851c90c 100644
--- a/sw/device/silicon_creator/mask_rom/mask_rom.c
+++ b/sw/device/silicon_creator/mask_rom/mask_rom.c
@@ -35,7 +35,6 @@
void mask_rom_exception_handler(void) { wait_for_interrupt(); }
void mask_rom_nmi_handler(void) { wait_for_interrupt(); }
-hmac_t hmac;
uart_t uart;
// FIXME: Temporary workaround to run functional test of SHA256.
@@ -46,12 +45,11 @@
return kErrorUnknown;
}
- RETURN_IF_ERROR(hmac_sha256_init(&hmac));
- RETURN_IF_ERROR(
- hmac_sha256_update(&hmac, &rom_ext_identifier, sizeof(uint32_t)));
+ hmac_sha256_init();
+ RETURN_IF_ERROR(hmac_sha256_update(&rom_ext_identifier, sizeof(uint32_t)));
hmac_digest_t digest;
- RETURN_IF_ERROR(hmac_sha256_final(&hmac, &digest));
+ RETURN_IF_ERROR(hmac_sha256_final(&digest));
return memcmp(digest.digest, kROMExtIdentifierExpectedDigest,
sizeof(digest.digest)) == 0
@@ -74,10 +72,6 @@
.sink = uart_sink,
});
- // Map HMAC registers.
- // TODO(lowrisc/opentitan#6283): Move to constant driver handles.
- hmac.base_addr = mmio_region_from_addr(TOP_EARLGREY_HMAC_BASE_ADDR);
-
// FIXME: what (if anything) should we print at startup?
base_printf("MaskROM\r\n");
diff --git a/sw/device/silicon_creator/mask_rom/sig_verify.c b/sw/device/silicon_creator/mask_rom/sig_verify.c
index d4a872d..c96f9e5 100644
--- a/sw/device/silicon_creator/mask_rom/sig_verify.c
+++ b/sw/device/silicon_creator/mask_rom/sig_verify.c
@@ -92,15 +92,10 @@
rom_error_t sigverify_rom_ext_signature_verify(
const uint8_t *signed_region, size_t signed_region_len,
const sigverify_rsa_buffer_t *signature, uint32_t key_id) {
- // TODO(#39): Make this a global const.
- hmac_t hmac = {
- .base_addr = mmio_region_from_addr(TOP_EARLGREY_HMAC_BASE_ADDR),
- };
-
hmac_digest_t act_digest;
- RETURN_IF_ERROR(hmac_sha256_init(&hmac));
- RETURN_IF_ERROR(hmac_sha256_update(&hmac, signed_region, signed_region_len));
- RETURN_IF_ERROR(hmac_sha256_final(&hmac, &act_digest));
+ hmac_sha256_init();
+ RETURN_IF_ERROR(hmac_sha256_update(signed_region, signed_region_len));
+ RETURN_IF_ERROR(hmac_sha256_final(&act_digest));
// TODO(#21): Key validity check using OTP.
const sigverify_rsa_key_t *key;
diff --git a/sw/device/silicon_creator/mask_rom/sig_verify_unittest.cc b/sw/device/silicon_creator/mask_rom/sig_verify_unittest.cc
index ea9d13c..4cb3b96 100644
--- a/sw/device/silicon_creator/mask_rom/sig_verify_unittest.cc
+++ b/sw/device/silicon_creator/mask_rom/sig_verify_unittest.cc
@@ -14,13 +14,6 @@
#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
-// Provide `==` for `hmac_t` in the global namespace to be able to use it in
-// expectations. Since `hmac_t` does not have any padding, `std::memcmp` is good
-// enough.
-bool operator==(const hmac_t &lhs, const hmac_t &rhs) {
- return std::memcmp(&lhs, &rhs, sizeof(lhs)) == 0;
-}
-
namespace sig_verify_unittest {
namespace {
using ::testing::DoAll;
@@ -30,13 +23,6 @@
using ::testing::SetArgPointee;
/**
- * Expected HMAC handle.
- */
-const hmac_t kHmacHandle = {
- .base_addr = mmio_region_from_addr(TOP_EARLGREY_HMAC_BASE_ADDR),
-};
-
-/**
* SHA2-256 digest of "test".
*
* Can be obtained using:
@@ -111,13 +97,11 @@
// FIXME: Parameterize with key ids.
const auto key_id = sigverify_rsa_key_id_get(&kSigVerifyRsaKeys[0]);
- EXPECT_CALL(hmac_, sha256_init(Pointee(kHmacHandle)))
+ EXPECT_CALL(hmac_, sha256_init());
+ EXPECT_CALL(hmac_, sha256_update(kSignedRegion.data(), sizeof(kSignedRegion)))
.WillOnce(Return(kErrorOk));
- EXPECT_CALL(hmac_, sha256_update(Pointee(kHmacHandle), kSignedRegion.data(),
- sizeof(kSignedRegion)))
- .WillOnce(Return(kErrorOk));
- EXPECT_CALL(hmac_, sha256_final(Pointee(kHmacHandle), NotNull()))
- .WillOnce(DoAll(SetArgPointee<1>(kTestDigest), Return(kErrorOk)));
+ EXPECT_CALL(hmac_, sha256_final(NotNull()))
+ .WillOnce(DoAll(SetArgPointee<0>(kTestDigest), Return(kErrorOk)));
EXPECT_CALL(sig_verify_mod_exp_,
mod_exp_ibex(&kSigVerifyRsaKeys[0], &kSignature, NotNull()))
.WillOnce(DoAll(SetArgPointee<2>(kEncMsg), Return(kErrorOk)));
@@ -139,13 +123,12 @@
auto bad_enc_msg = kEncMsg;
bad_enc_msg.data[i] = ~bad_enc_msg.data[i];
- EXPECT_CALL(hmac_, sha256_init(Pointee(kHmacHandle)))
+ EXPECT_CALL(hmac_, sha256_init());
+ EXPECT_CALL(hmac_,
+ sha256_update(kSignedRegion.data(), sizeof(kSignedRegion)))
.WillOnce(Return(kErrorOk));
- EXPECT_CALL(hmac_, sha256_update(Pointee(kHmacHandle), kSignedRegion.data(),
- sizeof(kSignedRegion)))
- .WillOnce(Return(kErrorOk));
- EXPECT_CALL(hmac_, sha256_final(Pointee(kHmacHandle), NotNull()))
- .WillOnce(DoAll(SetArgPointee<1>(kTestDigest), Return(kErrorOk)));
+ EXPECT_CALL(hmac_, sha256_final(NotNull()))
+ .WillOnce(DoAll(SetArgPointee<0>(kTestDigest), Return(kErrorOk)));
EXPECT_CALL(sig_verify_mod_exp_,
mod_exp_ibex(&kSigVerifyRsaKeys[0], &kSignature, NotNull()))
.WillOnce(DoAll(SetArgPointee<2>(bad_enc_msg), Return(true)));
