[rv_dm, doc] Document lifecycle control of debug
Signed-off-by: Greg Chadwick <gac@lowrisc.org>
diff --git a/hw/ip/rv_dm/doc/_index.md b/hw/ip/rv_dm/doc/_index.md
index 8604290..3a094b6 100644
--- a/hw/ip/rv_dm/doc/_index.md
+++ b/hw/ip/rv_dm/doc/_index.md
@@ -34,6 +34,14 @@
All hardware interfaces of the debug system are documented in the [PULP RISC-V Debug System Documentation](https://github.com/lowRISC/opentitan/blob/master/hw/vendor/pulp_riscv_dbg/doc/debug-system.md), with the exception of the bus interfaces, which are converted to TL-UL by this wrapper.
+### Life Cycle Control
+
+Debug system functionality is controlled by the [HW_DEBUG_EN]({{< relref "hw/ip/lc_ctrl/doc/#hw_debug_en" >}}) function of the life cycle controller.
+
+```verilog
+input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i, // Debug module lifecycle enable/disable
+```
+
### JTAG
The debug system provides a standard JTAG (IEEE Std 1149.1-2013) port for external debug access.
diff --git a/hw/ip/rv_dm/rtl/rv_dm.sv b/hw/ip/rv_dm/rtl/rv_dm.sv
index d5d9df1..c13510d 100644
--- a/hw/ip/rv_dm/rtl/rv_dm.sv
+++ b/hw/ip/rv_dm/rtl/rv_dm.sv
@@ -21,7 +21,7 @@
input logic clk_i, // clock
input logic rst_ni, // asynchronous reset active low, connect PoR
// here, not the system reset
- input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i,
+ input lc_ctrl_pkg::lc_tx_t lc_hw_debug_en_i, // Debug module lifecycle enable/disable
input prim_mubi_pkg::mubi4_t scanmode_i,
input scan_rst_ni,
output logic ndmreset_req_o, // non-debug module reset
