| commit | 987f307e801b34e3331fb54ce8264421819d70e2 | [log] [tgz] |
|---|---|---|
| author | Guillermo Maturana <maturana@google.com> | Thu Jun 10 22:14:37 2021 -0700 |
| committer | cindychip <cindy.chen0316@gmail.com> | Tue Jun 15 11:06:41 2021 -0700 |
| tree | 6592cea0b3e76aa96938d7afdd1facf975ee8c9b | |
| parent | 6fa343eabaf41afe7c2139ec91698620038bd958 [diff] |
[dv/clkmgr] Update docs and minor refactor Add coverpoints in the testplan. Remove extclk_sel_regwen from clkmgr_if. Fix the type of extclk_sel in clkmgr_if. Replace clkmgr_vif.wait_clks by clk_rst_vif.wait_clks. Simplify the constraint for lc_tx_t variable. Start monitor_ip_clk_en task in clkmgr_scoreboard. Signed-off-by: Guillermo Maturana <maturana@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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