[rom_ctrl] Add initial RTL
This doesn't really do anything very interesting: it just replaces the
ROM instantiation that was in top_earlgrey.sv and generates a verbose
wrapper around it.
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index 5f29a7e..bb776f2 100755
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -574,37 +574,18 @@
reset_connections: {rst_ni: "sys", rst_edn_ni: "sys"},
base_addr: "0x411D0000",
},
+ { name: "rom_ctrl",
+ type: "rom_ctrl",
+ clock_srcs: {clk_i: "main"},
+ clock_group: "infra",
+ reset_connections: {rst_ni: "sys"},
+ base_addrs: {rom: "0x00008000", regs: "0x411e0000"}
+ }
]
// Memories (ROM, RAM, eFlash) are defined at the top.
// It utilizes the primitive cells but configurable
memory: [
- { name: "rom",
- clock_srcs: {clk_i: "main"},
- clock_group: "infra",
- reset_connections: {rst_ni: "sys"},
- type: "rom",
- base_addr: "0x00008000",
- swaccess: "ro",
- size: "0x4000",
- // data integrity width
- integ_width: 8,
- inter_signal_list: [
- { struct: "tl"
- package: "tlul_pkg"
- type: "req_rsp"
- act: "rsp"
- name: "tl"
- },
- // Interface to memory configuration
- { struct: "rom_cfg",
- package: "prim_rom_pkg",
- type: "uni",
- name: "cfg",
- act: "rcv"
- }
- ]
- },
{ name: "ram_main",
clock_srcs: {clk_i: "main"},
clock_group: "infra",
@@ -838,7 +819,7 @@
'connect': {
'ast.ram_1p_cfg' : ['otbn.ram_cfg', 'ram_main.cfg', 'ram_ret_aon.cfg', 'rv_core_ibex.ram_cfg'],
'ast.ram_2p_cfg' : ['spi_device.ram_cfg', 'usbdev.ram_cfg'],
- 'ast.rom_cfg' : ['rom.cfg'],
+ 'ast.rom_cfg' : ['rom_ctrl.rom_cfg'],
'alert_handler.crashdump' : ['rstmgr_aon.alert_dump'],
'alert_handler.esc_rx' : ['rv_core_ibex.esc_nmi_rx',
'lc_ctrl.esc_wipe_secrets_rx',
