| commit | 96712d785a3273373960675c27df44ffd9008261 | [log] [tgz] |
|---|---|---|
| author | Cindy Chen <chencindy@opentitan.org> | Wed Apr 20 18:11:05 2022 -0700 |
| committer | Cindy Chen <cindy.chen0316@gmail.com> | Thu Apr 21 15:24:18 2022 -0700 |
| tree | 8c6c14c3dfcf925a055e1ee6e15a8ee6d998e117 | |
| parent | 877ec9265f073d886d27e3875cd4b691336fcce9 [diff] |
[dv/chip_lc_trans] Fix timeout issue This PR fixes chip_sw_lc_ctrl_transition_vseq timeout issue from nightly regression. 1). The reason for this timeout is: JTAG DV agent does not know when the chip is reset, so it does not reset its internal values properly. Solution: Override the apply_reset task with jtag cfg signal `in_reset` to let the jtag agent know when DUT resets. Also add a max attempt timeout so the sequence won't run for too long. 2). Second reason for timeout is the `num_trans`. If the num_trans = 3, it might run over the sw_timeout limit, and make it hard to dump waves and debug. So I reduced the `num_trans` to only 1-2 iterations. Signed-off-by: Cindy Chen <chencindy@opentitan.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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