[sw/boot_rom] Rename "boot_rom" to "test_rom".
The ROM code in `sw/device/boot_rom/` is used purely for testing purposes,
and is not designed to be used as the production mask ROM. The mask ROM
code lives in `sw/device/silicon_creator/mask_rom`. To make this more clear,
the `sw/device/boot_rom` ia renamed and relocated to
`sw/device/lib/testing/test_rom`.
This fixes #9154.
Signed-off-by: Timothy Trippel <ttrippel@google.com>
diff --git a/azure-pipelines.yml b/azure-pipelines.yml
index 7b3f3fe..6f46a88 100644
--- a/azure-pipelines.yml
+++ b/azure-pipelines.yml
@@ -213,10 +213,10 @@
# Patch software.
./hw/top_englishbreakfast/util/prepare_sw.py
# Build FPGA boot ROM and aes_serial binary for FPGA SCA.
- ninja -C "$OBJ_DIR" sw/device/boot_rom/boot_rom_export_fpga_nexysvideo
+ ninja -C "$OBJ_DIR" sw/device/lib/testing/test_rom/test_rom_export_fpga_nexysvideo
ninja -C "$OBJ_DIR" sw/device/sca/aes_serial_export_fpga_nexysvideo
# Build binaries for Verilator simulation.
- ninja -C "$OBJ_DIR" sw/device/boot_rom/boot_rom_export_sim_verilator
+ ninja -C "$OBJ_DIR" sw/device/lib/testing/test_rom/test_rom_export_sim_verilator
ninja -C "$OBJ_DIR" sw/device/tests/aes_smoketest_export_sim_verilator
ninja -C "$OBJ_DIR" sw/device/examples/hello_world/hello_world_export_sim_verilator
displayName: Build embedded targets
@@ -416,7 +416,7 @@
mkdir -p "$OBJ_DIR/hw"
mkdir -p "$BIN_DIR/hw/top_earlgrey"
- BOOTROM_VMEM="$BIN_DIR/sw/device/boot_rom/boot_rom_fpga_cw310.scr.39.vmem"
+ BOOTROM_VMEM="$BIN_DIR/sw/device/lib/testing/test_rom/test_rom_fpga_cw310.scr.39.vmem"
test -f "$BOOTROM_VMEM"
OTP_VMEM="$BIN_DIR/sw/device/otp_img/otp_img_fpga_cw310.vmem"
test -f "$OTP_VMEM"
@@ -510,7 +510,7 @@
./hw/top_earlgrey/util/top_earlgrey_reduce.py
- BOOTROM_VMEM="$BIN_DIR/sw/device/boot_rom/boot_rom_fpga_nexysvideo.scr.39.vmem"
+ BOOTROM_VMEM="$BIN_DIR/sw/device/lib/testing/test_rom/test_rom_fpga_nexysvideo.scr.39.vmem"
test -f "$BOOTROM_VMEM"
OTP_VMEM="$BIN_DIR/sw/device/otp_img/otp_img_fpga_nexysvideo.vmem"
test -f "$OTP_VMEM"
@@ -566,7 +566,7 @@
mkdir -p "$OBJ_DIR/hw"
mkdir -p "$BIN_DIR/hw/top_englishbreakfast"
- BOOTROM_VMEM="$BIN_DIR/sw/device/boot_rom/boot_rom_fpga_nexysvideo.32.vmem"
+ BOOTROM_VMEM="$BIN_DIR/sw/device/lib/testing/test_rom/test_rom_fpga_nexysvideo.32.vmem"
test -f "$BOOTROM_VMEM"
util/topgen-fusesoc.py --files-root=. --topname=top_englishbreakfast
diff --git a/doc/rm/ref_manual_fpga.md b/doc/rm/ref_manual_fpga.md
index 181f2b6..1dc0802 100644
--- a/doc/rm/ref_manual_fpga.md
+++ b/doc/rm/ref_manual_fpga.md
@@ -21,7 +21,7 @@
### Boot ROM development
-The FPGA bitstream is built after compiling whatever code is sitting in `sw/device/boot_rom`.
+The FPGA bitstream is built after compiling whatever code is sitting in `sw/device/lib/testing/test_rom`.
This binary is used to initialize internal FPGA memory and is part of the bitstream directly.
To update this content without rebuilding the FPGA, a flow is required to splice a new boot ROM binary into the bitstream.
@@ -44,7 +44,7 @@
The script assumes that there is an existing bitfile `build/lowrisc_systems_chip_earlgrey_cw310_0.1/synth-vivado/lowrisc_systems_chip_earlgrey_cw310_0.1.bit` (this is created after following the steps in [getting_started_fpga]({{< relref "doc/ug/getting_started_fpga" >}})).
-The script assumes that there is an existing boot ROM image under `build-bin/sw/device/boot_rom` and then creates a new bitfile of the same name at the same location.
+The script assumes that there is an existing boot ROM image under `build-bin/sw/device/lib/testing/test_rom` and then creates a new bitfile of the same name at the same location.
The original input bitfile is moved to `build/lowrisc_systems_chip_earlgrey_cw310_0.1/synth-vivado/lowrisc_systems_chip_earlgrey_cw310_0.1.bit.orig`.
The `cw310_loader.py` can then be used to directly flash the updated bitstream to the FPGA.
@@ -81,4 +81,4 @@
Loading done.
```
-For more details on the exact operation of the loading flow and how the boot ROM processes incoming data, please refer to the [boot ROM readme]({{< relref "sw/device/boot_rom/README.md" >}}).
+For more details on the exact operation of the loading flow and how the boot ROM processes incoming data, please refer to the [boot ROM readme]({{< relref "sw/device/lib/testing/test_rom/README.md" >}}).
diff --git a/doc/ug/directory_structure.md b/doc/ug/directory_structure.md
index 772d734..cf59203 100644
--- a/doc/ug/directory_structure.md
+++ b/doc/ug/directory_structure.md
@@ -112,14 +112,9 @@
├──device => Sources compiled for the OpenTitan chip,
│ │ including tests run on FPGA and simulations
│ │
-│ ├──boot_rom => Sources for generating the primary boot image
-│ │ loaded into ROM
-│ │
│ ├──benchmarks => Standard benchmarks and instructions for running
│ │ └──coremark them
│ │
-│ ├──doc => Documentation sources
-│ │
│ ├──examples => Example programs to demonstrate basic
│ │ ├──hello_world functionality
│ │ ├──...
@@ -129,8 +124,10 @@
│ │ └──common => Common sources for all SW tests including the CRT
│ │ source and the linker script
│ │
-│ ├──lib => SW library of device interface functions (DIFs)
-│ │ that provide APIs for controlling the hardware
+│ ├──lib => SW libraries, including device interface functions
+│ │ (DIFs), testutils, test boot ROM (test_rom), the
+│ │ OTTF, and other base APIs for controlling the
+│ │ hardware
│ │
│ └──tests => SW tests implemented on FPGA/Verilator/DV targets
│ ├──flash_ctrl
diff --git a/doc/ug/getting_started_build_sw.md b/doc/ug/getting_started_build_sw.md
index ad72425..e01566c 100644
--- a/doc/ug/getting_started_build_sw.md
+++ b/doc/ug/getting_started_build_sw.md
@@ -11,7 +11,7 @@
OpenTitan software is built using [Meson](https://mesonbuild.com).
However, Meson is not an exact fit for a lot of things OpenTitan does (such as distinguishing between FPGA, ASIC, and simulations), so the setup is a little bit different.
-For example, the following commands build the `boot_rom` and `hello_world` binaries for FPGA:
+For example, the following commands build the `test_rom` and `hello_world` binaries for FPGA:
```console
# Configure the Meson environment.
@@ -19,7 +19,7 @@
$ ./meson_init.sh
# Build the two targets we care about, specifically.
-$ ninja -C build-out sw/device/boot_rom/boot_rom_export_fpga_cw310
+$ ninja -C build-out sw/device/lib/testing/test_rom/test_rom_export_fpga_cw310
$ ninja -C build-out sw/device/examples/hello_world/hello_world_export_fpga_cw310
# Build *everything*, including targets for other devices.
diff --git a/doc/ug/getting_started_fpga.md b/doc/ug/getting_started_fpga.md
index b883ec6..7b91184 100644
--- a/doc/ug/getting_started_fpga.md
+++ b/doc/ug/getting_started_fpga.md
@@ -27,7 +27,7 @@
The FPGA build will pull in a program to act as the boot ROM.
This must be built before running the FPGA build.
-This is pulled in from the `sw/device/boot_rom` directory (see the `parameters:` section of the `hw/top_earlgrey/chip_earlgrey_cw310.core` file).
+This is pulled in from the `sw/device/lib/testing/test_rom/test_rom` directory (see the `parameters:` section of the `hw/top_earlgrey/chip_earlgrey_cw310.core` file).
To build it:
```console
@@ -337,7 +337,7 @@
```console
$ cd $REPO_TOP
-$ /tools/riscv/bin/riscv32-unknown-elf-gdb -ex "target extended-remote :3333" -ex "info reg" sw/device/boot_rom/rom.elf
+$ /tools/riscv/bin/riscv32-unknown-elf-gdb -ex "target extended-remote :3333" -ex "info reg" build-bin/sw/device/lib/testing/test_rom/test_rom_fpga_cw310.elf
```
#### Common operations with GDB
diff --git a/doc/ug/getting_started_verilator.md b/doc/ug/getting_started_verilator.md
index afa8da1..ae7dabe 100644
--- a/doc/ug/getting_started_verilator.md
+++ b/doc/ug/getting_started_verilator.md
@@ -47,7 +47,7 @@
```console
$ cd $REPO_TOP
$ build/lowrisc_dv_chip_verilator_sim_0.1/sim-verilator/Vchip_sim_tb \
- --meminit=rom,build-bin/sw/device/boot_rom/boot_rom_sim_verilator.scr.39.vmem \
+ --meminit=rom,build-bin/sw/device/lib/testing/test_rom/test_rom_sim_verilator.scr.39.vmem \
--meminit=flash,build-bin/sw/device/examples/hello_world/hello_world_sim_verilator.64.scr.vmem \
--meminit=otp,build-bin/sw/device/otp_img/otp_img_sim_verilator.vmem
```
@@ -83,10 +83,10 @@
```console
$ cat /dev/pts/11
-I00000 boot_rom.c:35] Version: opentitan-snapshot-20191101-1-1182-g2aedf641
+I00000 test_rom.c:35] Version: opentitan-snapshot-20191101-1-1182-g2aedf641
Build Date: 2020-05-13, 15:04:09
-I00001 boot_rom.c:44] Boot ROM initialisation has completed, jump into flash!
+I00001 test_rom.c:44] Boot ROM initialisation has completed, jump into flash!
I00000 hello_world.c:30] Hello World!
I00001 hello_world.c:31] Built at: May 13 2020, 15:27:31
I00002 demos.c:17] Watch the LEDs!
@@ -104,7 +104,7 @@
```console
$ cd $REPO_TOP
$ build/lowrisc_dv_chip_verilator_sim_0.1/sim-verilator/Vchip_sim_tb \
- --meminit=rom,build-bin/sw/device/boot_rom/boot_rom_sim_verilator.scr.39.vmem \
+ --meminit=rom,build-bin/sw/device/lib/testing/test_rom/test_rom_sim_verilator.scr.39.vmem \
--meminit=flash,build-bin/sw/device/examples/hello_world/hello_world_sim_verilator.64.scr.vmem \
--meminit=otp,build-bin/sw/device/otp_img/otp_img_sim_verilator.vmem
+UARTDPI_LOG_uart0=-
@@ -196,7 +196,7 @@
```console
$ cd $REPO_TOP
$ build/lowrisc_dv_chip_verilator_sim_0.1/sim-verilator/Vchip_sim_tb \
- --meminit=rom,build-bin/sw/device/boot_rom/boot_rom_sim_verilator.scr.39.vmem \
+ --meminit=rom,build-bin/sw/device/lib/testing/test_rom/test_rom_sim_verilator.scr.39.vmem \
--meminit=flash,build-bin/sw/device/examples/hello_world/hello_world_sim_verilator.64.scr.vmem \
--meminit=otp,build-bin/sw/device/otp_img/otp_img_sim_verilator.vmem
--trace
diff --git a/hw/ip/otbn/README.md b/hw/ip/otbn/README.md
index c8564e8..6d156ee 100644
--- a/hw/ip/otbn/README.md
+++ b/hw/ip/otbn/README.md
@@ -117,7 +117,7 @@
```sh
build/lowrisc_systems_chip_earlgrey_verilator_0.1/sim-verilator/Vchip_earlgrey_verilator \
- --meminit=rom,build-bin/sw/device/boot_rom/boot_rom_sim_verilator.scr.39.vmem \
+ --meminit=rom,build-bin/sw/device/lib/testing/test_rom/test_rom_sim_verilator.scr.39.vmem \
--meminit=flash,build-bin/sw/device/tests/otbn_smoketest_sim_verilator.elf \
--meminit=otp,build-bin/sw/device/otp_img/otp_img_sim_verilator.vmem \
+UARTDPI_LOG_uart0=- \
diff --git a/hw/ip/rom_ctrl/util/gen_vivado_mem_image.py b/hw/ip/rom_ctrl/util/gen_vivado_mem_image.py
index 5e2e612..8bb93a7 100755
--- a/hw/ip/rom_ctrl/util/gen_vivado_mem_image.py
+++ b/hw/ip/rom_ctrl/util/gen_vivado_mem_image.py
@@ -12,7 +12,7 @@
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug898-vivado-embedded-design.pdf#page=165
Typical usage:
->>> ./gen_vivado_mem_image.py boot_rom.scr.32.vmem boot_rom.updatemem.mem
+>>> ./gen_vivado_mem_image.py test_rom.scr.32.vmem test_rom.updatemem.mem
'''
import argparse
diff --git a/hw/top_earlgrey/chip_earlgrey_cw310.core b/hw/top_earlgrey/chip_earlgrey_cw310.core
index 0a0cfe5..d125cc6 100644
--- a/hw/top_earlgrey/chip_earlgrey_cw310.core
+++ b/hw/top_earlgrey/chip_earlgrey_cw310.core
@@ -35,14 +35,14 @@
parameters:
# XXX: This parameter needs to be absolute, or relative to the *.runs/synth_1
# directory. It's best to pass it as absolute path when invoking fusesoc, e.g.
- # --BootRomInitFile=$PWD/build-bin/sw/device/boot_rom/boot_rom_fpga_cw310.scr.39.vmem
+ # --BootRomInitFile=$PWD/build-bin/sw/device/lib/testing/test_rom/test_rom_fpga_cw310.scr.39.vmem
# XXX: The VMEM file should be added to the sources of the Vivado project to
# make the Vivado dependency tracking work. However this requires changes to
# fusesoc first.
BootRomInitFile:
datatype: str
description: Scrambled boot ROM initialization file in 40 bit vmem hex format
- default: "../../../../../build-bin/sw/device/boot_rom/boot_rom_fpga_cw310.scr.39.vmem"
+ default: "../../../../../build-bin/sw/device/lib/testing/test_rom/test_rom_fpga_cw310.scr.39.vmem"
paramtype: vlogparam
OtpCtrlMemInitFile:
datatype: str
diff --git a/hw/top_earlgrey/chip_earlgrey_nexysvideo.core b/hw/top_earlgrey/chip_earlgrey_nexysvideo.core
index 6ee70fb..5eba26e 100644
--- a/hw/top_earlgrey/chip_earlgrey_nexysvideo.core
+++ b/hw/top_earlgrey/chip_earlgrey_nexysvideo.core
@@ -35,14 +35,14 @@
parameters:
# XXX: This parameter needs to be absolute, or relative to the *.runs/synth_1
# directory. It's best to pass it as absolute path when invoking fusesoc, e.g.
- # --BootRomInitFile=$PWD/build-bin/sw/device/boot_rom/boot_rom_fpga_nexysvideo.scr.39.vmem
+ # --BootRomInitFile=$PWD/build-bin/sw/device/lib/testing/test_rom/test_rom_fpga_nexysvideo.scr.39.vmem
# XXX: The VMEM file should be added to the sources of the Vivado project to
# make the Vivado dependency tracking work. However this requires changes to
# fusesoc first.
BootRomInitFile:
datatype: str
description: Scrambled boot ROM initialization file in 40 bit vmem hex format
- default: "../../../../../build-bin/sw/device/boot_rom/boot_rom_fpga_nexysvideo.scr.39.vmem"
+ default: "../../../../../build-bin/sw/device/lib/testing/test_rom/test_rom_fpga_nexysvideo.scr.39.vmem"
paramtype: vlogparam
OtpCtrlMemInitFile:
datatype: str
diff --git a/hw/top_earlgrey/doc/dv/index.md b/hw/top_earlgrey/doc/dv/index.md
index 309d795..965b123 100644
--- a/hw/top_earlgrey/doc/dv/index.md
+++ b/hw/top_earlgrey/doc/dv/index.md
@@ -40,7 +40,7 @@
* [JTAG interface]()
* SPI interface
* UART interface
-* SW logger inteface (for boot_rom as well as the test SW)
+* SW logger inteface (for test boot ROM as well as the test SW)
* SW test status monitor
* Backdoor memory interfaces (for ROM, SRAM and the flask banks)
* Individual control pins:
diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
index 01e130a..b5f5379 100644
--- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson
+++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
@@ -135,7 +135,7 @@
}
{
name: sw_test_mode
- sw_images: ["sw/device/boot_rom/boot_rom:0"]
+ sw_images: ["sw/device/lib/testing/test_rom/test_rom:0"]
run_opts: ["+sw_build_bin_dir={sw_build_dir}/build-bin",
"+sw_build_device={sw_build_device}",
// Separate individual SW images supplied to +sw_images plusarg by comma.
@@ -178,7 +178,7 @@
//
// Each entry in `sw_images` is followed by an index separated with ':' which
// is used by the testbench to know what type of image is it:
- // - 0 for boot_rom,
+ // - 0 for Boot ROM,
// - 1 for SW test,
// - 2 for OTBN test,
// This allows an arbitrary number of SW images to be supplied to the TB.
diff --git a/hw/top_earlgrey/dv/env/chip_env_cfg.sv b/hw/top_earlgrey/dv/env/chip_env_cfg.sv
index 9424f0f..1c108ec 100644
--- a/hw/top_earlgrey/dv/env/chip_env_cfg.sv
+++ b/hw/top_earlgrey/dv/env/chip_env_cfg.sv
@@ -43,7 +43,7 @@
// suffixed to the basename to pick the correct image. The following files (extensions) with this
// basename are expected to exist there:
// - .elf: embedded executable
- // - .32.vmem: mem image with 32-bit word size (for boot_rom)
+ // - .32.vmem: mem image with 32-bit word size (for boot ROM)
// - .64.vmem: mem image with 64-bit word size (for sw_test / flash load)
// - .frames.vmem: mem image converted with spiflash frames (for tests with boostrap enabled)
// - .rodata.txt: dump of RO sections of the SW
diff --git a/hw/top_earlgrey/dv/verilator/verilator_sim_cfg.hjson b/hw/top_earlgrey/dv/verilator/verilator_sim_cfg.hjson
index 72c94cd..839f1d5 100644
--- a/hw/top_earlgrey/dv/verilator/verilator_sim_cfg.hjson
+++ b/hw/top_earlgrey/dv/verilator/verilator_sim_cfg.hjson
@@ -56,7 +56,7 @@
run_modes: [
{
name: sw_test_mode
- sw_images: ["sw/device/boot_rom/boot_rom:0",
+ sw_images: ["sw/device/lib/testing/test_rom/test_rom:0",
"sw/device/otp_img/otp_img:3"]
run_opts: [
// The following shell snippet converts the SW images specification to what's
@@ -91,7 +91,7 @@
//
// Each entry in `sw_images` is followed by an index separated with ':' which
// is used by the testbench to know what type of image is it:
- // - 0 for boot_rom,
+ // - 0 for boot ROM,
// - 1 for SW test,
// - 2 for OTBN test,
// - 3 for OTP and so on
diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv
index faded64..b5612c4 100644
--- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv
+++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_cw310.sv
@@ -12,7 +12,7 @@
module chip_earlgrey_cw310 #(
// Path to a VMEM file containing the contents of the boot ROM, which will be
// baked into the FPGA bitstream.
- parameter BootRomInitFile = "boot_rom_fpga_cw310.32.vmem",
+ parameter BootRomInitFile = "test_rom_fpga_cw310.32.vmem",
// Path to a VMEM file containing the contents of the emulated OTP, which will be
// baked into the FPGA bitstream.
parameter OtpCtrlMemInitFile = "otp_img_fpga_cw310.vmem"
diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv
index cbcb86b..c3fd887 100644
--- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv
+++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv
@@ -12,7 +12,7 @@
module chip_earlgrey_nexysvideo #(
// Path to a VMEM file containing the contents of the boot ROM, which will be
// baked into the FPGA bitstream.
- parameter BootRomInitFile = "boot_rom_fpga_nexysvideo.32.vmem",
+ parameter BootRomInitFile = "test_rom_fpga_nexysvideo.32.vmem",
// Path to a VMEM file containing the contents of the emulated OTP, which will be
// baked into the FPGA bitstream.
parameter OtpCtrlMemInitFile = "otp_img_fpga_nexysvideo.vmem"
diff --git a/hw/top_earlgrey/util/opentitan_earlgrey_usbdev_pin_config_sim.sh b/hw/top_earlgrey/util/opentitan_earlgrey_usbdev_pin_config_sim.sh
index e1898d7..3eae468 100755
--- a/hw/top_earlgrey/util/opentitan_earlgrey_usbdev_pin_config_sim.sh
+++ b/hw/top_earlgrey/util/opentitan_earlgrey_usbdev_pin_config_sim.sh
@@ -7,7 +7,7 @@
VERILATOR=build/lowrisc_systems_chip_earlgrey_verilator_0.1/sim-verilator/Vchip_earlgrey_verilator
# Code to load
-ROMCODE=build-bin/sw/device/boot_rom/boot_rom_sim_verilator.scr.39.vmem
+ROMCODE=build-bin/sw/device/lib/testing/test_rom/test_rom_sim_verilator.scr.39.vmem
FLASH=build-bin/sw/device/examples/hello_usbdev/hello_usbdev_sim_verilator.elf
OTP=build-bin/sw/device/otp_img/otp_img_sim_verilator.vmem
diff --git a/hw/top_earlgrey/util/top_earlgrey_reduce.py b/hw/top_earlgrey/util/top_earlgrey_reduce.py
index 96f7a09..c142d08 100755
--- a/hw/top_earlgrey/util/top_earlgrey_reduce.py
+++ b/hw/top_earlgrey/util/top_earlgrey_reduce.py
@@ -133,7 +133,7 @@
if (args.build):
log.info("Regenerating boot ROM...")
cmd = ["ninja", "-C", top_path + "/build-out",
- "sw/device/boot_rom/boot_rom_export_fpga_nexysvideo"]
+ "sw/device/lib/testing/test_rom/test_rom_export_fpga_nexysvideo"]
try:
subprocess.run(cmd,
check=True,
diff --git a/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core b/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core
index e1a03c7..1586894 100644
--- a/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core
+++ b/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core
@@ -32,14 +32,14 @@
parameters:
# XXX: This parameter needs to be absolute, or relative to the *.runs/synth_1
# directory. It's best to pass it as absolute path when invoking fusesoc, e.g.
- # --BootRomInitFile=$PWD/build-bin/sw/device/boot_rom/boot_rom_fpga_nexysvideo.32.vmem
+ # --BootRomInitFile=$PWD/build-bin/sw/device/lib/testing/test_rom/test_rom_fpga_nexysvideo.32.vmem
# XXX: The VMEM file should be added to the sources of the Vivado project to
# make the Vivado dependency tracking work. However this requires changes to
# fusesoc first.
BootRomInitFile:
datatype: str
description: Boot ROM initialization file in 32 bit vmem hex format
- default: "../../../../../build-bin/sw/device/boot_rom/boot_rom_fpga_nexysvideo.32.vmem"
+ default: "../../../../../build-bin/sw/device/lib/testing/test_rom/test_rom_fpga_nexysvideo.32.vmem"
paramtype: vlogparam
# For value definition, please see ip/prim/rtl/prim_pkg.sv
PRIM_DEFAULT_IMPL:
diff --git a/hw/top_englishbreakfast/util/prepare_sw.py b/hw/top_englishbreakfast/util/prepare_sw.py
index 6ed6273..73ad7db 100755
--- a/hw/top_englishbreakfast/util/prepare_sw.py
+++ b/hw/top_englishbreakfast/util/prepare_sw.py
@@ -140,11 +140,11 @@
sys.exit(1)
if (args.build):
- # Build the software including boot_rom to enable the FPGA build.
+ # Build the software including test_rom to enable the FPGA build.
binaries = [
- 'sw/device/boot_rom/boot_rom_export_fpga_nexysvideo',
+ 'sw/device/lib/testing/test_rom/test_rom_export_fpga_nexysvideo',
'sw/device/sca/aes_serial_export_fpga_nexysvideo',
- 'sw/device/boot_rom/boot_rom_export_sim_verilator',
+ 'sw/device/lib/testing/test_rom/test_rom_export_sim_verilator',
'sw/device/tests/aes_smoketest_export_sim_verilator',
'sw/device/examples/hello_world/hello_world_export_sim_verilator',
]
diff --git a/hw/top_englishbreakfast/util/sw_sources.patch b/hw/top_englishbreakfast/util/sw_sources.patch
index bec9a48..d4a18b2 100644
--- a/hw/top_englishbreakfast/util/sw_sources.patch
+++ b/hw/top_englishbreakfast/util/sw_sources.patch
@@ -1,27 +1,3 @@
-diff --git a/sw/device/boot_rom/rom_crt.S b/sw/device/boot_rom/rom_crt.S
-index e4b14eb84..d595aa757 100644
---- a/sw/device/boot_rom/rom_crt.S
-+++ b/sw/device/boot_rom/rom_crt.S
-@@ -81,19 +81,6 @@ _reset_start:
- _start:
- .globl _start
-
-- // Enable entropy complex - this is not the full enable
-- li a0, TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR
-- li t0, 0x55505a
-- sw t0, ENTROPY_SRC_CONF_REG_OFFSET(a0)
--
-- li a0, TOP_EARLGREY_CSRNG_BASE_ADDR
-- li t0, 0xaaa
-- sw t0, CSRNG_CTRL_REG_OFFSET(a0)
--
-- li a0, TOP_EARLGREY_EDN0_BASE_ADDR
-- li t0, 0x55aa
-- sw t0, EDN_CTRL_REG_OFFSET(a0)
--
- // Zero out the `.bss` segment.
- la a0, _bss_start
- la a1, _bss_end
diff --git a/sw/device/lib/pinmux.c b/sw/device/lib/pinmux.c
index 8861f54ba..8442bb896 100644
--- a/sw/device/lib/pinmux.c
@@ -51,6 +27,30 @@
- mask = PINMUX_MIO_OUTSEL_0_OUT_0_MASK;
- mmio_region_write32(reg32, reg_offset, reg_value & mask);
}
+diff --git a/sw/device/lib/testing/test_rom/test_rom_start.S b/sw/device/lib/testing/test_rom/test_rom_start.S
+index e4b14eb84..d595aa757 100644
+--- a/sw/device/lib/testing/test_rom/test_rom_start.S
++++ b/sw/device/lib/testing/test_rom/test_rom_start.S
+@@ -81,19 +81,6 @@ _reset_start:
+ _start:
+ .globl _start
+
+- // Enable entropy complex - this is not the full enable
+- li a0, TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR
+- li t0, 0x55505a
+- sw t0, ENTROPY_SRC_CONF_REG_OFFSET(a0)
+-
+- li a0, TOP_EARLGREY_CSRNG_BASE_ADDR
+- li t0, 0xaaa
+- sw t0, CSRNG_CTRL_REG_OFFSET(a0)
+-
+- li a0, TOP_EARLGREY_EDN0_BASE_ADDR
+- li t0, 0x55aa
+- sw t0, EDN_CTRL_REG_OFFSET(a0)
+-
+ // Zero out the `.bss` segment.
+ la a0, _bss_start
+ la a1, _bss_end
diff --git a/sw/device/sca/aes_serial.c b/sw/device/sca/aes_serial.c
index 5dc1286af..1e2dced96 100644
--- a/sw/device/sca/aes_serial.c
@@ -227,10 +227,10 @@
CHECK_DIF_OK(
dif_aes_init(mmio_region_from_addr(TOP_EARLGREY_AES_BASE_ADDR), &aes));
diff --git a/sw/device/tests/meson.build b/sw/device/tests/meson.build
-index 2df371008..d9ab1416f 100644
+index 4ad73f695..f87b0779c 100644
--- a/sw/device/tests/meson.build
+++ b/sw/device/tests/meson.build
-@@ -259,7 +259,6 @@ aes_smoketest_lib = declare_dependency(
+@@ -245,7 +245,6 @@ aes_smoketest_lib = declare_dependency(
sw_lib_dif_aes,
sw_lib_mmio,
sw_lib_runtime_log,
diff --git a/rules/opentitan.bzl b/rules/opentitan.bzl
index 782ba34..0d934a9 100644
--- a/rules/opentitan.bzl
+++ b/rules/opentitan.bzl
@@ -224,7 +224,7 @@
)
def verilator_params(
- rom = "//sw/device/boot_rom:boot_rom_verilator_scr",
+ rom = "//sw/device/lib/testing/test_rom:test_rom_verilator_scr",
otp = "//hw/ip/otp_ctrl/data:rma_image_verilator",
tags = ["verilator"],
timeout = "moderate",
diff --git a/sw/_index.md b/sw/_index.md
index 4123f28..68bc772 100644
--- a/sw/_index.md
+++ b/sw/_index.md
@@ -47,7 +47,7 @@
## Testing-only Utilities
There are some host-side utilities, which are only used for testing.
-* `sw/host/spiflash` is a tool that can flash a testing image over SPI onto a chip that uses `sw/device/boot_rom` for its reset boot stage.
+* `sw/host/spiflash` is a tool that can flash a testing image over SPI onto a chip that uses `sw/device/lib/testing/test_rom/test_rom` as its first boot stage.
# Other Documentation
diff --git a/sw/device/_index.md b/sw/device/_index.md
index cc8773f..8376865 100644
--- a/sw/device/_index.md
+++ b/sw/device/_index.md
@@ -26,7 +26,7 @@
There are also prototype versions of some of the boot stages, now only used for testing:
-- [`sw/device/boot_rom`]({{< relref "sw/device/boot_rom/README.md" >}}) is a previous, testing-only version of the Mask ROM.
+- [`sw/device/lib/testing/test_rom`]({{< relref "sw/device/lib/testing/test_rom/README.md" >}}) is a previous, testing-only version of the Mask ROM.
- `sw/device/exts` contains software for our prototype second boot stage images.
## Documentation Index
diff --git a/sw/device/lib/testing/meson.build b/sw/device/lib/testing/meson.build
index a815b30..93d6c59 100644
--- a/sw/device/lib/testing/meson.build
+++ b/sw/device/lib/testing/meson.build
@@ -153,3 +153,4 @@
)
subdir('test_framework')
+subdir('test_rom')
diff --git a/sw/device/lib/testing/test_framework/test_status.h b/sw/device/lib/testing/test_framework/test_status.h
index 099c8e4..04ea452 100644
--- a/sw/device/lib/testing/test_framework/test_status.h
+++ b/sw/device/lib/testing/test_framework/test_status.h
@@ -18,7 +18,7 @@
*/
typedef enum test_status {
/**
- * Indicates that the CPU has started executing the boot_rom code.
+ * Indicates that the CPU has started executing the test_rom code.
*
* Writing this value to #kDeviceTestStatusAddress must not stop simulation of
* the current device.
diff --git a/sw/device/boot_rom/BUILD b/sw/device/lib/testing/test_rom/BUILD
similarity index 88%
rename from sw/device/boot_rom/BUILD
rename to sw/device/lib/testing/test_rom/BUILD
index 9dd0056..24b7c5a 100644
--- a/sw/device/boot_rom/BUILD
+++ b/sw/device/lib/testing/test_rom/BUILD
@@ -12,26 +12,26 @@
)
opentitan_binary(
- name = "boot_rom",
+ name = "test_rom",
srcs = [
- "irq_vector.S",
+ "test_rom_irq_vector.S",
],
linkopts = [
- "-T $(location rom_link.ld)",
+ "-T $(location test_rom.ld)",
],
output_scrambled = True,
deps = [
- "rom_link.ld",
- ":boot_rom_lib",
+ "test_rom.ld",
+ ":test_rom_lib",
"//sw/device/lib/base:mmio",
],
)
cc_library(
- name = "boot_rom_lib",
+ name = "test_rom_lib",
srcs = [
- "boot_rom.c",
- "rom_crt.S",
+ "test_rom.c",
+ "test_rom_start.S",
],
target_compatible_with = [OPENTITAN_CPU],
deps = [
@@ -83,9 +83,9 @@
)
opentitan_functest(
- name = "boot_rom_test",
+ name = "test_rom_test",
srcs = [
- "boot_rom_test.c",
+ "test_rom_test.c",
],
deps = [
],
diff --git a/sw/device/boot_rom/README.md b/sw/device/lib/testing/test_rom/README.md
similarity index 100%
rename from sw/device/boot_rom/README.md
rename to sw/device/lib/testing/test_rom/README.md
diff --git a/sw/device/boot_rom/bootstrap.c b/sw/device/lib/testing/test_rom/bootstrap.c
similarity index 98%
rename from sw/device/boot_rom/bootstrap.c
rename to sw/device/lib/testing/test_rom/bootstrap.c
index faf3c63..588a921 100644
--- a/sw/device/boot_rom/bootstrap.c
+++ b/sw/device/lib/testing/test_rom/bootstrap.c
@@ -2,11 +2,10 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-#include "sw/device/boot_rom/bootstrap.h"
+#include "sw/device/lib/testing/test_rom/bootstrap.h"
#include <stddef.h>
-#include "sw/device/boot_rom/spiflash_frame.h"
#include "sw/device/lib/arch/device.h"
#include "sw/device/lib/base/memory.h"
#include "sw/device/lib/base/mmio.h"
@@ -17,6 +16,7 @@
#include "sw/device/lib/runtime/hart.h"
#include "sw/device/lib/runtime/log.h"
#include "sw/device/lib/testing/check.h"
+#include "sw/device/lib/testing/test_rom/spiflash_frame.h"
#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
diff --git a/sw/device/boot_rom/bootstrap.h b/sw/device/lib/testing/test_rom/bootstrap.h
similarity index 81%
rename from sw/device/boot_rom/bootstrap.h
rename to sw/device/lib/testing/test_rom/bootstrap.h
index 9b22991..aef7daf 100644
--- a/sw/device/boot_rom/bootstrap.h
+++ b/sw/device/lib/testing/test_rom/bootstrap.h
@@ -2,8 +2,8 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-#ifndef OPENTITAN_SW_DEVICE_BOOT_ROM_BOOTSTRAP_H_
-#define OPENTITAN_SW_DEVICE_BOOT_ROM_BOOTSTRAP_H_
+#ifndef OPENTITAN_SW_DEVICE_LIB_TESTING_TEST_ROM_BOOTSTRAP_H_
+#define OPENTITAN_SW_DEVICE_LIB_TESTING_TEST_ROM_BOOTSTRAP_H_
/**
* A bootstrap error representing a flash erase failure.
@@ -32,4 +32,4 @@
*/
int bootstrap(void);
-#endif // OPENTITAN_SW_DEVICE_BOOT_ROM_BOOTSTRAP_H_
+#endif // OPENTITAN_SW_DEVICE_LIB_TESTING_TEST_ROM_BOOTSTRAP_H_
diff --git a/sw/device/boot_rom/meson.build b/sw/device/lib/testing/test_rom/meson.build
similarity index 68%
rename from sw/device/boot_rom/meson.build
rename to sw/device/lib/testing/test_rom/meson.build
index ccf1c3f..6c28d56 100644
--- a/sw/device/boot_rom/meson.build
+++ b/sw/device/lib/testing/test_rom/meson.build
@@ -19,34 +19,34 @@
)],
)
-# ROM linker parameters.
+# Test ROM linker parameters.
#
# See sw/device/exts/common/flash_link.ld for additional info about these
# parameters.
-rom_linkfile = files(['rom_link.ld'])
-rom_link_args = [
+test_rom_linker_script = files(['test_rom.ld'])
+test_rom_link_args = [
'-Wl,-L,@0@'.format(meson.source_root()),
- '-Wl,-T,@0@/@1@'.format(meson.source_root(), rom_linkfile[0]),
+ '-Wl,-T,@0@/@1@'.format(meson.source_root(), test_rom_linker_script[0]),
'-Wl,--build-id=none',
]
-rom_link_deps = [rom_linkfile]
+test_rom_link_deps = [test_rom_linker_script]
foreach device_name, device_lib : sw_lib_arch_core_devices
- boot_rom_elf = executable(
- 'boot_rom_' + device_name,
+ test_rom_elf = executable(
+ 'test_rom_' + device_name,
sources: [
hw_ip_sram_ctrl_reg_h,
hw_ip_entropy_src_reg_h,
hw_ip_csrng_reg_h,
hw_ip_edn_reg_h,
- 'boot_rom.c',
+ 'test_rom.c',
'bootstrap.c',
- 'irq_vector.S',
- 'rom_crt.S',
+ 'test_rom_irq_vector.S',
+ 'test_rom_start.S',
],
name_suffix: 'elf',
- link_args: rom_link_args,
- link_depends: rom_link_deps,
+ link_args: test_rom_link_args,
+ link_depends: test_rom_link_deps,
dependencies: [
chip_info_h,
sw_lib_crt,
@@ -67,52 +67,52 @@
],
)
- target_name = 'boot_rom_@0@_' + device_name
+ target_name = 'test_rom_@0@_' + device_name
- boot_rom_dis = custom_target(
+ test_rom_dis = custom_target(
target_name.format('dis'),
- input: boot_rom_elf,
+ input: test_rom_elf,
kwargs: elf_to_dis_custom_target_args,
)
- boot_rom_bin = custom_target(
+ test_rom_bin = custom_target(
target_name.format('bin'),
- input: boot_rom_elf,
+ input: test_rom_elf,
kwargs: elf_to_bin_custom_target_args,
)
- boot_rom_vmem32 = custom_target(
+ test_rom_vmem32 = custom_target(
target_name.format('vmem32'),
- input: boot_rom_bin,
+ input: test_rom_bin,
kwargs: bin_to_vmem32_custom_target_args,
)
- boot_rom_vmem64 = custom_target(
+ test_rom_vmem64 = custom_target(
target_name.format('vmem64'),
- input: boot_rom_bin,
+ input: test_rom_bin,
kwargs: bin_to_vmem64_custom_target_args,
)
- boot_rom_scrambled = custom_target(
+ test_rom_scrambled = custom_target(
target_name.format('scrambled'),
command: scramble_image_command,
depend_files: scramble_image_depend_files,
- input: boot_rom_elf,
+ input: test_rom_elf,
output: scramble_image_outputs,
build_by_default: true,
)
- boot_rom_sim_dv_logs = []
+ test_rom_sim_dv_logs = []
if device_name == 'sim_dv'
- boot_rom_sim_dv_logs = custom_target(
- 'boot_rom_dv_logs',
- # Boot_rom has additional RO data sections of interest to DV logging.
+ test_rom_sim_dv_logs = custom_target(
+ 'test_rom_dv_logs',
+ # test_rom has additional RO data sections of interest to DV logging.
command: [
extract_sw_logs_sim_dv_command,
'--rodata-sections', '.chip_info',
],
depend_files: [extract_sw_logs_sim_dv_depend_files,],
- input: boot_rom_elf,
+ input: test_rom_elf,
output: extract_sw_logs_sim_dv_outputs,
)
endif
@@ -122,13 +122,13 @@
command: export_target_command,
depend_files: [export_target_depend_files,],
input: [
- boot_rom_elf,
- boot_rom_dis,
- boot_rom_bin,
- boot_rom_vmem32,
- boot_rom_vmem64,
- boot_rom_scrambled,
- boot_rom_sim_dv_logs,
+ test_rom_elf,
+ test_rom_dis,
+ test_rom_bin,
+ test_rom_vmem32,
+ test_rom_vmem64,
+ test_rom_scrambled,
+ test_rom_sim_dv_logs,
],
output: target_name.format('export'),
build_always_stale: true,
diff --git a/sw/device/boot_rom/spiflash_frame.h b/sw/device/lib/testing/test_rom/spiflash_frame.h
similarity index 89%
rename from sw/device/boot_rom/spiflash_frame.h
rename to sw/device/lib/testing/test_rom/spiflash_frame.h
index de8867a..52aa3a2 100644
--- a/sw/device/boot_rom/spiflash_frame.h
+++ b/sw/device/lib/testing/test_rom/spiflash_frame.h
@@ -2,8 +2,8 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-#ifndef OPENTITAN_SW_DEVICE_BOOT_ROM_SPIFLASH_FRAME_H_
-#define OPENTITAN_SW_DEVICE_BOOT_ROM_SPIFLASH_FRAME_H_
+#ifndef OPENTITAN_SW_DEVICE_LIB_TESTING_TEST_ROM_SPIFLASH_FRAME_H_
+#define OPENTITAN_SW_DEVICE_LIB_TESTING_TEST_ROM_SPIFLASH_FRAME_H_
#include <stdint.h>
@@ -74,4 +74,4 @@
_Static_assert(sizeof(spiflash_frame_t) == SPIFLASH_RAW_BUFFER_SIZE,
"spiflash_frame_t is the wrong size!");
-#endif // OPENTITAN_SW_DEVICE_BOOT_ROM_SPIFLASH_FRAME_H_
+#endif // OPENTITAN_SW_DEVICE_LIB_TESTING_TEST_ROM_SPIFLASH_FRAME_H_
diff --git a/sw/device/boot_rom/boot_rom.c b/sw/device/lib/testing/test_rom/test_rom.c
similarity index 92%
rename from sw/device/boot_rom/boot_rom.c
rename to sw/device/lib/testing/test_rom/test_rom.c
index aa26b52..f18c494 100644
--- a/sw/device/boot_rom/boot_rom.c
+++ b/sw/device/lib/testing/test_rom/test_rom.c
@@ -2,8 +2,6 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-#include "sw/device/boot_rom/bootstrap.h"
-#include "sw/device/boot_rom/chip_info.h" // Generated.
#include "sw/device/lib/arch/device.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/dif/dif_gpio.h"
@@ -16,11 +14,13 @@
#include "sw/device/lib/runtime/print.h"
#include "sw/device/lib/testing/check.h"
#include "sw/device/lib/testing/test_framework/test_status.h"
+#include "sw/device/lib/testing/test_rom/bootstrap.h"
+#include "sw/device/lib/testing/test_rom/chip_info.h" // Generated.
#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" // Generated.
/**
- * This symbol is defined in sw/device/boot_rom/rom_link.ld,
+ * This symbol is defined in sw/device/lib/testing/test_rom/test_rom.ld,
* and describes the location of the flash header.
*
* The actual contents are not defined by the ROM, but rather
diff --git a/sw/device/boot_rom/rom_link.ld b/sw/device/lib/testing/test_rom/test_rom.ld
similarity index 97%
rename from sw/device/boot_rom/rom_link.ld
rename to sw/device/lib/testing/test_rom/test_rom.ld
index aa41408..aa59b92 100644
--- a/sw/device/boot_rom/rom_link.ld
+++ b/sw/device/lib/testing/test_rom/test_rom.ld
@@ -61,7 +61,7 @@
*/
SECTIONS {
/**
- * Ibex interrupt vector. See irq_vector.S for more information.
+ * Ibex interrupt vector. See test_rom_irq_vector.S for more information.
*
* This has to be set up at the boot address, so that execution jumps to the
* reset handler correctly.
diff --git a/sw/device/boot_rom/irq_vector.S b/sw/device/lib/testing/test_rom/test_rom_irq_vector.S
similarity index 100%
rename from sw/device/boot_rom/irq_vector.S
rename to sw/device/lib/testing/test_rom/test_rom_irq_vector.S
diff --git a/sw/device/boot_rom/rom_crt.S b/sw/device/lib/testing/test_rom/test_rom_start.S
similarity index 100%
rename from sw/device/boot_rom/rom_crt.S
rename to sw/device/lib/testing/test_rom/test_rom_start.S
diff --git a/sw/device/boot_rom/boot_rom_test.c b/sw/device/lib/testing/test_rom/test_rom_test.c
similarity index 100%
rename from sw/device/boot_rom/boot_rom_test.c
rename to sw/device/lib/testing/test_rom/test_rom_test.c
diff --git a/sw/device/meson.build b/sw/device/meson.build
index 200661a..1427b68 100644
--- a/sw/device/meson.build
+++ b/sw/device/meson.build
@@ -2,9 +2,6 @@
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
-subdir('lib')
-subdir('exts')
-
# Dictionaries that can be used as `custom_target` arguments for common
# operations on `.elf` and `.bin` files. To create a custom target using
# `my_custom_target_args`:
@@ -164,7 +161,8 @@
},
}
-subdir('boot_rom')
+subdir('lib')
+subdir('exts')
subdir('otp_img')
subdir('silicon_creator')
subdir('silicon_owner')
diff --git a/sw/device/silicon_creator/mask_rom/BUILD b/sw/device/silicon_creator/mask_rom/BUILD
index d8609ca..7655d7c 100644
--- a/sw/device/silicon_creator/mask_rom/BUILD
+++ b/sw/device/silicon_creator/mask_rom/BUILD
@@ -164,7 +164,7 @@
hdrs = ["primitive_bootstrap.h"],
deps = [
"//hw/top_earlgrey/sw/autogen:top_earlgrey",
- "//sw/device/boot_rom:bootstrap",
+ "//sw/device/lib/testing/test_rom:bootstrap",
"//sw/device/lib:flash_ctrl",
"//sw/device/lib/arch:device",
"//sw/device/lib/base",
diff --git a/sw/device/silicon_creator/mask_rom/primitive_bootstrap.c b/sw/device/silicon_creator/mask_rom/primitive_bootstrap.c
index e538095..ef499b4 100644
--- a/sw/device/silicon_creator/mask_rom/primitive_bootstrap.c
+++ b/sw/device/silicon_creator/mask_rom/primitive_bootstrap.c
@@ -6,13 +6,13 @@
#include <stddef.h>
-#include "sw/device/boot_rom/spiflash_frame.h"
#include "sw/device/lib/arch/device.h"
#include "sw/device/lib/base/memory.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/dif/dif_gpio.h"
#include "sw/device/lib/dif/dif_spi_device.h"
#include "sw/device/lib/flash_ctrl.h"
+#include "sw/device/lib/testing/test_rom/spiflash_frame.h"
#include "sw/device/silicon_creator/lib/drivers/hmac.h"
#include "sw/device/silicon_creator/lib/error.h"
#include "sw/device/silicon_creator/lib/log.h"
diff --git a/sw/device/tests/meson.build b/sw/device/tests/meson.build
index 27dada5..4ad73f6 100644
--- a/sw/device/tests/meson.build
+++ b/sw/device/tests/meson.build
@@ -755,7 +755,7 @@
###############################################################################
# Build Targets
###############################################################################
-# (unsigned) test binaries loaded with ROM from sw/device/boot_rom/
+# (unsigned) test binaries loaded with ROM from sw/device/lib/testing/test_rom/
foreach sw_test_name, sw_test_info : sw_tests
foreach device_name, device_lib : sw_lib_arch_core_devices
sw_test_elf = executable(
diff --git a/sw/host/spiflash/README.md b/sw/host/spiflash/README.md
index 287d028..821256b 100644
--- a/sw/host/spiflash/README.md
+++ b/sw/host/spiflash/README.md
@@ -40,9 +40,9 @@
Where ${DEVICE} is one of 'sim_verilator' or 'fpga_nexysvideo'
-## Run the tool in Verilator
+## Run the tool with the Verilator Simulation
-Run Verilator with boot_rom enabled as described in the [verilator]({{< relref "doc/ug/getting_started_verilator" >}}) getting started guide.
+Run Verilator with test_rom as described in the [verilator]({{< relref "doc/ug/getting_started_verilator" >}}) getting started guide.
Run spiflash.
In this example we use SPI device `/dev/pts/3` as an example.
diff --git a/sw/host/spiflash/ftdi_spi_interface.cc b/sw/host/spiflash/ftdi_spi_interface.cc
index 3b14d25..fdfa21d 100644
--- a/sw/host/spiflash/ftdi_spi_interface.cc
+++ b/sw/host/spiflash/ftdi_spi_interface.cc
@@ -38,7 +38,7 @@
};
/**
- * Resets the target to go back to boot_rom. Assumes boot_rom will enter
+ * Resets the target to go back to boot ROM. Assumes boot ROM will enter
* bootstrap mode.
*/
void ResetTarget(struct mpsse_context *ctx) {
diff --git a/sw/vendor/patches/riscv_compliance/0002-Add-OpenTitan-target.patch b/sw/vendor/patches/riscv_compliance/0002-Add-OpenTitan-target.patch
index 5a2e2ed..8fdb0e5 100644
--- a/sw/vendor/patches/riscv_compliance/0002-Add-OpenTitan-target.patch
+++ b/sw/vendor/patches/riscv_compliance/0002-Add-OpenTitan-target.patch
@@ -70,7 +70,7 @@
+To quickly get started with a verilator binary or FPGA bitfile, please see the
+[OpenTitan quick start guide](https://docs.opentitan.org/doc/ug/quickstart/).
+
-+Finally the support software must be built, including the boot_rom when using
++Finally the support software must be built, including the test_rom when using
+the verilator target.
+
+```console
@@ -285,7 +285,7 @@
+ CARG = -DSIMULATION=1
+ RUN_TARGET = \
+ $(TARGET_SIM) \
-+ --meminit="rom,$(OT_BIN)/sw/device/boot_rom/boot_rom_sim_verilator.elf" \
++ --meminit="rom,$(OT_BIN)/sw/device/lib/testing/test_rom/test_rom_sim_verilator.elf" \
+ --meminit="flash,$(<)" \
+ +UARTDPI_LOG_uart0="$(*).uart.log" > $@ 2>&1 \
+ && sed -e 's/^/[UART $(shell basename $(*))] /' "$(*).uart.log" $(REDIR) \
diff --git a/sw/vendor/patches/riscv_compliance/0004-otp-img-Add-OTP-image-preload-switch-to-RUN_TARGET.patch b/sw/vendor/patches/riscv_compliance/0004-otp-img-Add-OTP-image-preload-switch-to-RUN_TARGET.patch
index 969b225..f9f31db 100644
--- a/sw/vendor/patches/riscv_compliance/0004-otp-img-Add-OTP-image-preload-switch-to-RUN_TARGET.patch
+++ b/sw/vendor/patches/riscv_compliance/0004-otp-img-Add-OTP-image-preload-switch-to-RUN_TARGET.patch
@@ -14,6 +14,6 @@
RUN_TARGET = \
$(TARGET_SIM) \
+ --meminit="otp,$(OT_BIN)/sw/device/otp_img/otp_img_sim_verilator.vmem" \
- --meminit="rom,$(OT_BIN)/sw/device/boot_rom/boot_rom_sim_verilator.elf" \
+ --meminit="rom,$(OT_BIN)/sw/device/lib/testing/test_rom/test_rom_sim_verilator.elf" \
--meminit="flash,$(<)" \
+UARTDPI_LOG_uart0="$(*).uart.log" > $@ 2>&1 \
diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/README.md b/sw/vendor/riscv_compliance/riscv-target/opentitan/README.md
index a942788..6286b29 100644
--- a/sw/vendor/riscv_compliance/riscv-target/opentitan/README.md
+++ b/sw/vendor/riscv_compliance/riscv-target/opentitan/README.md
@@ -37,7 +37,7 @@
To quickly get started with a verilator binary or FPGA bitfile, please see the
[OpenTitan quick start guide](https://docs.opentitan.org/doc/ug/quickstart/).
-Finally the support software must be built, including the boot_rom when using
+Finally the support software must be built, including the test_rom when using
the verilator target.
```console
diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include b/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include
index 570e0be..6e4643e 100644
--- a/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include
+++ b/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include
@@ -26,7 +26,7 @@
RUN_TARGET = \
$(TARGET_SIM) \
--meminit="otp,$(OT_BIN)/sw/device/otp_img/otp_img_sim_verilator.vmem" \
- --meminit="rom,$(OT_BIN)/sw/device/boot_rom/boot_rom_sim_verilator.elf" \
+ --meminit="rom,$(OT_BIN)/sw/device/lib/testing/test_rom/test_rom_sim_verilator.elf" \
--meminit="flash,$(<)" \
+UARTDPI_LOG_uart0="$(*).uart.log" > $@ 2>&1 \
&& sed -e 's/^/[UART $(shell basename $(*))] /' "$(*).uart.log" $(REDIR) \
diff --git a/test/systemtest/earlgrey/test_sim_verilator.py b/test/systemtest/earlgrey/test_sim_verilator.py
index 4cb38e5..d95f976 100644
--- a/test/systemtest/earlgrey/test_sim_verilator.py
+++ b/test/systemtest/earlgrey/test_sim_verilator.py
@@ -130,7 +130,8 @@
"""
sim_path = bin_dir / "hw/top_earlgrey/Vchip_earlgrey_verilator"
- rom_vmem_path = bin_dir / "sw/device/boot_rom/boot_rom_sim_verilator.scr.39.vmem"
+ rom_vmem_path = (bin_dir /
+ "sw/device/lib/testing/test_rom/test_rom_sim_verilator.scr.39.vmem")
otp_img_path = bin_dir / "sw/device/otp_img/otp_img_sim_verilator.vmem"
sim = ot.VerilatorSimOpenTitan(sim_path, rom_vmem_path, otp_img_path, tmp_path)
@@ -180,7 +181,8 @@
""" Load a single application to the Verilator simulation using spiflash """
sim_path = bin_dir / "hw/top_earlgrey/Vchip_earlgrey_verilator"
- rom_vmem_path = bin_dir / "sw/device/boot_rom/boot_rom_sim_verilator.scr.39.vmem"
+ rom_vmem_path = (bin_dir /
+ "sw/device/lib/testing/test_rom/test_rom_sim_verilator.scr.39.vmem")
otp_img_path = bin_dir / "sw/device/otp_img/otp_img_sim_verilator.vmem"
sim = ot.VerilatorSimOpenTitan(sim_path, rom_vmem_path, otp_img_path, tmp_path)
@@ -210,7 +212,8 @@
"""
# Run a simulation (bootrom only, no app beyond that)
sim_path = bin_dir / "hw/top_earlgrey/Vchip_earlgrey_verilator"
- rom_vmem_path = bin_dir / "sw/device/boot_rom/boot_rom_sim_verilator.scr.39.vmem"
+ rom_vmem_path = (bin_dir /
+ "sw/device/lib/testing/test_rom/test_rom_sim_verilator.scr.39.vmem")
otp_img_path = bin_dir / "sw/device/otp_img/otp_img_sim_verilator.vmem"
sim = ot.VerilatorSimOpenTitan(sim_path, rom_vmem_path, otp_img_path, tmp_path)
diff --git a/test/systemtest/englishbreakfast/test_sim_verilator.py b/test/systemtest/englishbreakfast/test_sim_verilator.py
index 5aceec1..2d6279c 100644
--- a/test/systemtest/englishbreakfast/test_sim_verilator.py
+++ b/test/systemtest/englishbreakfast/test_sim_verilator.py
@@ -56,7 +56,8 @@
"""
sim_path = bin_dir / "hw/top_englishbreakfast/Vchip_englishbreakfast_verilator"
- rom_vmem_path = bin_dir / "sw/device/boot_rom/boot_rom_sim_verilator.32.vmem"
+ rom_vmem_path = (bin_dir /
+ "sw/device/lib/testing/test_rom/test_rom_sim_verilator.32.vmem")
sim = ot.VerilatorSimOpenTitan(sim_path, rom_vmem_path, None, tmp_path)
diff --git a/util/fpga/splice_rom.sh b/util/fpga/splice_rom.sh
index 89c2f86..a62caee 100755
--- a/util/fpga/splice_rom.sh
+++ b/util/fpga/splice_rom.sh
@@ -31,7 +31,7 @@
- b: Mask ROM binary, set to either DV or PROD.
Mask ROM binary targets (-b):
- - DV: sw/device/boot_rom
+ - DV: sw/device/lib/testing/test_rom
- PROD: sw/device/silicon_creator/mask_rom
USAGE
@@ -83,7 +83,7 @@
TARGET_PREFIX=""
if [[ ${FLAGS_BIN} == "DV" ]]; then
- TARGET_PREFIX="sw/device/boot_rom/boot_rom"
+ TARGET_PREFIX="sw/device/lib/testing/test_rom/test_rom"
elif [[ ${FLAGS_BIN} == "PROD" ]]; then
TARGET_PREFIX="sw/device/silicon_creator/mask_rom/mask_rom"
else
diff --git a/util/topgen/templates/chiplevel.sv.tpl b/util/topgen/templates/chiplevel.sv.tpl
index cafe44e..b1af1a6 100644
--- a/util/topgen/templates/chiplevel.sv.tpl
+++ b/util/topgen/templates/chiplevel.sv.tpl
@@ -71,7 +71,7 @@
module chip_${top["name"]}_${target["name"]} #(
// Path to a VMEM file containing the contents of the boot ROM, which will be
// baked into the FPGA bitstream.
- parameter BootRomInitFile = "boot_rom_fpga_${target["name"]}.32.vmem",
+ parameter BootRomInitFile = "test_rom_fpga_${target["name"]}.32.vmem",
// Path to a VMEM file containing the contents of the emulated OTP, which will be
// baked into the FPGA bitstream.
parameter OtpCtrlMemInitFile = "otp_img_fpga_${target["name"]}.vmem"
