commit 961a33b6872b349929ba51b5cdf5fa6f7841af25
author Weicai Yang <weicai@google.com> Tue May 12 15:28:14 2020 -0700
committer sriyerg <46467186+sriyerg@users.noreply.github.com> Tue May 12 19:15:21 2020 -0700
tree 4e8acd86eaf29a255ab3e2d85d57872eb2953690
parent e288e3b6b279d8a8521f0e2e44254f7878933152

[dv/top] Fix chip_flash_ctrl_test timeout

Increase timeout timer

Signed-off-by: Weicai Yang <weicai@google.com>

hw/top_earlgrey/dv/chip_sim_cfg.hjson

diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
index 1d7152b..3313ea1 100644
--- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson
+++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
@@ -128,7 +128,7 @@
       uvm_test_seq: chip_sw_test_base_vseq
       sw_test: sw/device/benchmarks/coremark/coremark_top_earlgrey
       run_opts: ["+en_uart_logger=1",
-                 "+sw_test_timeout_ns=20000000"]
+                 "+sw_test_timeout_ns=22000000"] // 22ms
     }
 
     // The test below is added in the included tl_access_tests.hjson.

hw/top_earlgrey/dv/env/chip_env_cfg.sv

diff --git a/hw/top_earlgrey/dv/env/chip_env_cfg.sv b/hw/top_earlgrey/dv/env/chip_env_cfg.sv
index 8cf5f75..3d79a33 100644
--- a/hw/top_earlgrey/dv/env/chip_env_cfg.sv
+++ b/hw/top_earlgrey/dv/env/chip_env_cfg.sv
@@ -22,7 +22,7 @@
   sw_logger_vif             sw_logger_vif[string];
   string                    sw_images[string];
   virtual sw_test_status_if sw_test_status_vif;
-  uint                      sw_test_timeout_ns = 2_000_000; // 2ms
+  uint                      sw_test_timeout_ns = 5_000_000; // 5ms
 
   // ext component cfgs
   rand uart_agent_cfg m_uart_agent_cfg;