[prim] Remove temporary workaround in parameter list related to primgen
This workaround is related to lowRISC/OpenTitan#2679 which got resolved
a while back. It is no longer needed.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
diff --git a/hw/ip/prim_generic/rtl/prim_generic_flop.sv b/hw/ip/prim_generic/rtl/prim_generic_flop.sv
index 0e620e9..ef436ed 100644
--- a/hw/ip/prim_generic/rtl/prim_generic_flop.sv
+++ b/hw/ip/prim_generic/rtl/prim_generic_flop.sv
@@ -4,10 +4,9 @@
`include "prim_assert.sv"
-module prim_generic_flop # (
- parameter int Width = 1,
- localparam int WidthSubOne = Width-1,
- parameter logic [WidthSubOne:0] ResetValue = 0
+module prim_generic_flop #(
+ parameter int Width = 1,
+ parameter logic [Width-1:0] ResetValue = 0
) (
input clk_i,
input rst_ni,
@@ -23,4 +22,4 @@
end
end
-endmodule // prim_generic_flop
+endmodule
diff --git a/hw/ip/prim_generic/rtl/prim_generic_flop_2sync.sv b/hw/ip/prim_generic/rtl/prim_generic_flop_2sync.sv
index 76a072c..45f802b 100644
--- a/hw/ip/prim_generic/rtl/prim_generic_flop_2sync.sv
+++ b/hw/ip/prim_generic/rtl/prim_generic_flop_2sync.sv
@@ -7,11 +7,10 @@
// for synchronization
module prim_generic_flop_2sync #(
- parameter int Width = 16,
- localparam int WidthSubOne = Width-1, // temp work around #2679
- parameter logic [WidthSubOne:0] ResetValue = '0
+ parameter int Width = 16,
+ parameter logic [Width-1:0] ResetValue = '0
) (
- input clk_i, // receive clock
+ input clk_i,
input rst_ni,
input [Width-1:0] d_i,
output logic [Width-1:0] q_o
@@ -39,5 +38,4 @@
.q_o
);
-
endmodule
diff --git a/hw/ip/prim_xilinx/rtl/prim_xilinx_flop.sv b/hw/ip/prim_xilinx/rtl/prim_xilinx_flop.sv
index f98314a..fe63fd4 100644
--- a/hw/ip/prim_xilinx/rtl/prim_xilinx_flop.sv
+++ b/hw/ip/prim_xilinx/rtl/prim_xilinx_flop.sv
@@ -4,10 +4,9 @@
`include "prim_assert.sv"
-module prim_xilinx_flop # (
- parameter int Width = 1,
- localparam int WidthSubOne = Width-1,
- parameter logic [WidthSubOne:0] ResetValue = 0
+module prim_xilinx_flop #(
+ parameter int Width = 1,
+ parameter logic [Width-1:0] ResetValue = 0
) (
input clk_i,
input rst_ni,
@@ -24,4 +23,4 @@
end
end
-endmodule // prim_xilinx_flop
+endmodule
