[uart] d/q naming cleanup
diff --git a/hw/ip/uart/rtl/uart_core.sv b/hw/ip/uart/rtl/uart_core.sv
index b8e792a..62e14b9 100644
--- a/hw/ip/uart/rtl/uart_core.sv
+++ b/hw/ip/uart/rtl/uart_core.sv
@@ -28,13 +28,13 @@
import uart_reg_pkg::*;
- logic [15:0] rx_val;
+ logic [15:0] rx_val_q;
logic [7:0] uart_rdata;
logic tick_baud_x16, rx_tick_baud;
logic tx_fifo_rst_n, rx_fifo_rst_n;
logic [5:0] tx_fifo_depth, rx_fifo_depth;
- logic [5:0] rx_fifo_depth_prev;
- logic [23:0] rx_timeout_count, rx_timeout_count_next, uart_rxto_val;
+ logic [5:0] rx_fifo_depth_prev_q;
+ logic [23:0] rx_timeout_count_d, rx_timeout_count_q, uart_rxto_val;
logic rx_fifo_depth_changed, uart_rxto_en;
logic tx_enable, rx_enable;
logic sys_loopback, line_loopback, rxnf_enable;
@@ -53,8 +53,7 @@
logic rx_sync;
logic rx_in;
logic break_err;
- logic [4:0] allzero_cnt;
- logic [4:0] allzero_cnt_next;
+ logic [4:0] allzero_cnt_d, allzero_cnt_q;
logic allzero_err, not_allzero_char;
logic event_tx_watermark, event_rx_watermark, event_tx_overflow, event_rx_overflow;
logic event_rx_frame_err, event_rx_break_err, event_rx_timeout, event_rx_parity_err;
@@ -78,21 +77,21 @@
BRK_WAIT
} break_st_e ;
- break_st_e break_st;
+ break_st_e break_st_q;
assign not_allzero_char = rx_valid & (~event_rx_frame_err | (rx_fifo_data != 8'h0));
assign allzero_err = event_rx_frame_err & (rx_fifo_data == 8'h0);
- assign allzero_cnt_next = (break_st == BRK_WAIT || not_allzero_char) ? 5'h0 :
- //allzero_cnt[4] never be 1b without break_st as BRK_WAIT
- //allzero_cnt[4] ? allzero_cnt :
- allzero_err ? allzero_cnt + 5'd1 :
- allzero_cnt;
+ assign allzero_cnt_d = (break_st_q == BRK_WAIT || not_allzero_char) ? 5'h0 :
+ //allzero_cnt_q[4] never be 1b without break_st_q as BRK_WAIT
+ //allzero_cnt_q[4] ? allzero_cnt_q :
+ allzero_err ? allzero_cnt_q + 5'd1 :
+ allzero_cnt_q;
always_ff @(posedge clk_i or negedge rst_ni) begin
- if (!rst_ni) allzero_cnt <= '0;
- else if (rx_enable) allzero_cnt <= allzero_cnt_next;
+ if (!rst_ni) allzero_cnt_q <= '0;
+ else if (rx_enable) allzero_cnt_q <= allzero_cnt_d;
end
// break_err edges in same cycle as event_rx_frame_err edges ; that way the
@@ -100,33 +99,33 @@
always_comb begin
unique case (reg2hw.ctrl.rxblvl.q)
- 2'h0: break_err = allzero_cnt_next >= 5'd2;
- 2'h1: break_err = allzero_cnt_next >= 5'd4;
- 2'h2: break_err = allzero_cnt_next >= 5'd8;
- default: break_err = allzero_cnt_next >= 5'd16;
+ 2'h0: break_err = allzero_cnt_d >= 5'd2;
+ 2'h1: break_err = allzero_cnt_d >= 5'd4;
+ 2'h2: break_err = allzero_cnt_d >= 5'd8;
+ default: break_err = allzero_cnt_d >= 5'd16;
endcase
end
always_ff @(posedge clk_i or negedge rst_ni) begin
- if (!rst_ni) break_st <= BRK_CHK;
+ if (!rst_ni) break_st_q <= BRK_CHK;
else begin
- unique case (break_st)
+ unique case (break_st_q)
BRK_CHK: begin
- if (event_rx_break_err) break_st <= BRK_WAIT;
+ if (event_rx_break_err) break_st_q <= BRK_WAIT;
end
BRK_WAIT: begin
- if (rx_in) break_st <= BRK_CHK;
+ if (rx_in) break_st_q <= BRK_CHK;
end
default: begin
- break_st <= BRK_CHK;
+ break_st_q <= BRK_CHK;
end
endcase
end
end
- assign hw2reg.val.d = rx_val;
+ assign hw2reg.val.d = rx_val_q;
assign hw2reg.rdata.d = uart_rdata;
@@ -151,17 +150,17 @@
// Fin * (NCO/2**16)
// So, with a 16 bit accumulator, the output clock is
// Fin * (NCO/65536)
- logic [16:0] nco_sum; // extra bit to get the carry
+ logic [16:0] nco_sum_q; // extra bit to get the carry
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
- nco_sum <= 17'h0;
+ nco_sum_q <= 17'h0;
end else if (tx_enable || rx_enable) begin
- nco_sum <= {1'b0,nco_sum[15:0]} + {1'b0,reg2hw.ctrl.nco.q};
+ nco_sum_q <= {1'b0,nco_sum_q[15:0]} + {1'b0,reg2hw.ctrl.nco.q};
end
end
- assign tick_baud_x16 = nco_sum[16];
+ assign tick_baud_x16 = nco_sum_q[16];
// ######################################################################
// TX Logic
@@ -226,7 +225,7 @@
);
// Based on: en.wikipedia.org/wiki/Repetition_code mentions the use of a majority filter
- // in uarts to ignore brief noise spikes
+ // in UART to ignore brief noise spikes
logic rx_sync_q1, rx_sync_q2, rx_in_mx, rx_in_maj;
always_ff @(posedge clk_i or negedge rst_ni) begin
@@ -284,8 +283,8 @@
);
always_ff @(posedge clk_i or negedge rst_ni) begin
- if (!rst_ni) rx_val <= 16'h0;
- else if (tick_baud_x16) rx_val <= {rx_val[14:0], rx_in};
+ if (!rst_ni) rx_val_q <= 16'h0;
+ else if (tick_baud_x16) rx_val_q <= {rx_val_q[14:0], rx_in};
end
// ######################################################################
@@ -317,9 +316,9 @@
assign uart_rxto_en = reg2hw.timeout_ctrl.en.q;
assign uart_rxto_val = reg2hw.timeout_ctrl.val.q;
- assign rx_fifo_depth_changed = (rx_fifo_depth != rx_fifo_depth_prev);
+ assign rx_fifo_depth_changed = (rx_fifo_depth != rx_fifo_depth_prev_q);
- assign rx_timeout_count_next =
+ assign rx_timeout_count_d =
// don't count if timeout feature not enabled ;
// will never reach timeout val + lower power
(uart_rxto_en == 1'b0) ? 24'd0 :
@@ -332,26 +331,26 @@
// stop the count at timeout value (this will set the interrupt)
// Removed below line as when the timeout reaches the value,
// event occured, and timeout value reset to 0h.
- //(rx_timeout_count == uart_rxto_val) ? rx_timeout_count :
+ //(rx_timeout_count_q == uart_rxto_val) ? rx_timeout_count_q :
// increment if at rx baud tick
- rx_tick_baud ? (rx_timeout_count + 24'd1) :
- rx_timeout_count;
+ rx_tick_baud ? (rx_timeout_count_q + 24'd1) :
+ rx_timeout_count_q;
- assign event_rx_timeout = (rx_timeout_count == uart_rxto_val) & uart_rxto_en;
+ assign event_rx_timeout = (rx_timeout_count_q == uart_rxto_val) & uart_rxto_en;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
- rx_timeout_count <= 24'd0;
- rx_fifo_depth_prev <= 6'd0;
+ rx_timeout_count_q <= 24'd0;
+ rx_fifo_depth_prev_q <= 6'd0;
end else begin
- rx_timeout_count <= rx_timeout_count_next;
- rx_fifo_depth_prev <= rx_fifo_depth;
+ rx_timeout_count_q <= rx_timeout_count_d;
+ rx_fifo_depth_prev_q <= rx_fifo_depth;
end
end
assign event_rx_overflow = rx_fifo_wvalid & ~rx_fifo_wready;
assign event_tx_overflow = reg2hw.wdata.qe & ~tx_fifo_wready;
- assign event_rx_break_err = break_err && (break_st == BRK_CHK);
+ assign event_rx_break_err = break_err & (break_st_q == BRK_CHK);
// instantiate interrupt hardware primitives
diff --git a/hw/ip/uart/rtl/uart_rx.sv b/hw/ip/uart/rtl/uart_rx.sv
index 9b5cfe7..829895a 100644
--- a/hw/ip/uart/rtl/uart_rx.sv
+++ b/hw/ip/uart/rtl/uart_rx.sv
@@ -24,76 +24,82 @@
input rx
);
+ logic rx_valid_q;
+ logic [10:0] sreg_q, sreg_d;
+ logic [3:0] bit_cnt_q, bit_cnt_d;
+ logic [3:0] baud_div_q, baud_div_d;
+ logic tick_baud_d, tick_baud_q;
+ logic idle_d, idle_q;
- logic [10:0] sreg, sreg_next;
- logic [3:0] bit_cnt, bit_cnt_next;
- logic [3:0] baud_div, baud_div_next;
- logic tick_baud_next, idle_next;
+ assign tick_baud = tick_baud_q;
+ assign idle = idle_q;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
- sreg <= 11'h0;
- bit_cnt <= 4'h0;
- baud_div <= 4'h0;
- tick_baud <= 1'b0;
- idle <= 1'b1;
+ sreg_q <= 11'h0;
+ bit_cnt_q <= 4'h0;
+ baud_div_q <= 4'h0;
+ tick_baud_q <= 1'b0;
+ idle_q <= 1'b1;
end else begin
- sreg <= sreg_next;
- bit_cnt <= bit_cnt_next;
- baud_div <= baud_div_next;
- tick_baud <= tick_baud_next;
- idle <= idle_next;
+ sreg_q <= sreg_d;
+ bit_cnt_q <= bit_cnt_d;
+ baud_div_q <= baud_div_d;
+ tick_baud_q <= tick_baud_d;
+ idle_q <= idle_d;
end
end
always_comb begin
if (!rx_enable) begin
- sreg_next = 11'h0;
- bit_cnt_next = 4'h0;
- baud_div_next = 4'h0;
- tick_baud_next = 1'b0;
- idle_next = 1'b1;
+ sreg_d = 11'h0;
+ bit_cnt_d = 4'h0;
+ baud_div_d = 4'h0;
+ tick_baud_d = 1'b0;
+ idle_d = 1'b1;
end else begin
- tick_baud_next = 1'b0;
- sreg_next = sreg;
- bit_cnt_next = bit_cnt;
- baud_div_next = baud_div;
- idle_next = idle;
+ tick_baud_d = 1'b0;
+ sreg_d = sreg_q;
+ bit_cnt_d = bit_cnt_q;
+ baud_div_d = baud_div_q;
+ idle_d = idle_q;
if (tick_baud_x16) begin
- {tick_baud_next, baud_div_next} = {1'b0,baud_div} + 5'h1;
+ {tick_baud_d, baud_div_d} = {1'b0,baud_div_q} + 5'h1;
end
- if (idle && !rx) begin
+ if (idle_q && !rx) begin
// start of char, sample in the middle of the bit time
- baud_div_next = 4'd8;
- tick_baud_next = 1'b0;
- bit_cnt_next = (parity_enable ? 4'd11 : 4'd10);
- sreg_next = 11'h0;
- idle_next = 1'b0;
- end else if (!idle && tick_baud) begin
- if ((bit_cnt == (parity_enable ? 4'd11 : 4'd10)) && rx) begin
+ baud_div_d = 4'd8;
+ tick_baud_d = 1'b0;
+ bit_cnt_d = (parity_enable ? 4'd11 : 4'd10);
+ sreg_d = 11'h0;
+ idle_d = 1'b0;
+ end else if (!idle_q && tick_baud_q) begin
+ if ((bit_cnt_q == (parity_enable ? 4'd11 : 4'd10)) && rx) begin
// must have been a glitch on the input, start bit is not set
// in the middle of the bit time, abort
- idle_next = 1'b1;
- bit_cnt_next = 4'h0;
+ idle_d = 1'b1;
+ bit_cnt_d = 4'h0;
end else begin
- sreg_next = {rx, sreg[10:1]};
- bit_cnt_next = bit_cnt - 4'h1;
- idle_next = (bit_cnt == 4'h1);
+ sreg_d = {rx, sreg_q[10:1]};
+ bit_cnt_d = bit_cnt_q - 4'h1;
+ idle_d = (bit_cnt_q == 4'h1);
end
end
end
end
always_ff @(posedge clk_i or negedge rst_ni) begin
- if (!rst_ni) rx_valid <= 1'b0;
- else rx_valid <= tick_baud & (bit_cnt == 4'h1);
+ if (!rst_ni) rx_valid_q <= 1'b0;
+ else rx_valid_q <= tick_baud_q & (bit_cnt_q == 4'h1);
+
end
- assign rx_data = parity_enable ? sreg[8:1] : sreg[9:2];
- // (rx_parity = sreg[9])
- assign frame_err = rx_valid & ~sreg[10];
- assign rx_parity_err = parity_enable & rx_valid &
- (^{sreg[9:1],parity_odd});
+ assign rx_valid = rx_valid_q;
+ assign rx_data = parity_enable ? sreg_q[8:1] : sreg_q[9:2];
+ // (rx_parity = sreg_q[9])
+ assign frame_err = rx_valid_q & ~sreg_q[10];
+ assign rx_parity_err = parity_enable & rx_valid_q &
+ (^{sreg_q[9:1],parity_odd});
endmodule
diff --git a/hw/ip/uart/rtl/uart_tx.sv b/hw/ip/uart/rtl/uart_tx.sv
index ba6d305..d10d16a 100644
--- a/hw/ip/uart/rtl/uart_tx.sv
+++ b/hw/ip/uart/rtl/uart_tx.sv
@@ -22,56 +22,58 @@
);
- logic [3:0] baud_div;
- logic tick_baud;
+ logic [3:0] baud_div_q;
+ logic tick_baud_q;
- logic [3:0] bit_cnt, bit_cnt_next;
- logic [10:0] sreg, sreg_next;
- logic tx_next;
+ logic [3:0] bit_cnt_q, bit_cnt_d;
+ logic [10:0] sreg_q, sreg_d;
+ logic tx_q, tx_d;
+
+ assign tx = tx_q;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
- baud_div <= 4'h0;
- tick_baud <= 1'b0;
+ baud_div_q <= 4'h0;
+ tick_baud_q <= 1'b0;
end else if (tick_baud_x16) begin
- {tick_baud, baud_div} <= {1'b0,baud_div} + 5'h1;
+ {tick_baud_q, baud_div_q} <= {1'b0,baud_div_q} + 5'h1;
end else begin
- tick_baud <= 1'b0;
+ tick_baud_q <= 1'b0;
end
end
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
- bit_cnt <= 4'h0;
- sreg <= 11'h7ff;
- tx <= 1'b1;
+ bit_cnt_q <= 4'h0;
+ sreg_q <= 11'h7ff;
+ tx_q <= 1'b1;
end else begin
- bit_cnt <= bit_cnt_next;
- sreg <= sreg_next;
- tx <= tx_next;
+ bit_cnt_q <= bit_cnt_d;
+ sreg_q <= sreg_d;
+ tx_q <= tx_d;
end
end
always_comb begin
if (!tx_enable) begin
- bit_cnt_next = 4'h0;
- sreg_next = 11'h7ff;
- tx_next = 1'b1;
+ bit_cnt_d = 4'h0;
+ sreg_d = 11'h7ff;
+ tx_d = 1'b1;
end else begin
- bit_cnt_next = bit_cnt;
- sreg_next = sreg;
- tx_next = tx;
+ bit_cnt_d = bit_cnt_q;
+ sreg_d = sreg_q;
+ tx_d = tx_q;
if (wr) begin
- sreg_next = {1'b1, (parity_enable ? wr_parity : 1'b1), wr_data, 1'b0};
- bit_cnt_next = (parity_enable ? 4'd11 : 4'd10);
- end else if (tick_baud && (bit_cnt != 4'h0)) begin
- sreg_next = {1'b1, sreg[10:1]};
- tx_next = sreg[0];
- bit_cnt_next = bit_cnt - 4'h1;
+ sreg_d = {1'b1, (parity_enable ? wr_parity : 1'b1), wr_data, 1'b0};
+ bit_cnt_d = (parity_enable ? 4'd11 : 4'd10);
+ end else if (tick_baud_q && (bit_cnt_q != 4'h0)) begin
+ sreg_d = {1'b1, sreg_q[10:1]};
+ tx_d = sreg_q[0];
+ bit_cnt_d = bit_cnt_q - 4'h1;
end
end
end
- assign idle = (tx_enable) ? (bit_cnt == 4'h0) : 1'b1;
+ assign idle = (tx_enable) ? (bit_cnt_q == 4'h0) : 1'b1;
endmodule
