[sram] Add memory initialization
- Software can request memory initialization
- Memory contents will be written with "random" values
- During the duration of initialization, memory reads are blocked
- Software should poll on initialization completion before continuing
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/sram_ctrl/data/sram_ctrl.hjson b/hw/ip/sram_ctrl/data/sram_ctrl.hjson
index 8650d8b..834e19b 100644
--- a/hw/ip/sram_ctrl/data/sram_ctrl.hjson
+++ b/hw/ip/sram_ctrl/data/sram_ctrl.hjson
@@ -41,9 +41,15 @@
{ name: "RndCnstSramNonce",
desc: "Compile-time random reset value for SRAM scrambling nonce.",
type: "otp_ctrl_pkg::sram_nonce_t"
- randcount: "64",
+ randcount: "128",
randtype: "data", // randomize randcount databits
},
+ { name: "RndCnstSramLfsrPerm",
+ desc: "Compile-time random permutation for LFSR output",
+ type: "sram_ctrl_pkg::lfsr_perm_t"
+ randcount: "32",
+ randtype: "perm",
+ },
{ name: "InstrExec",
desc: "Support execution from SRAM",
type: "bit",
@@ -74,6 +80,14 @@
default: "'0"
package: "sram_ctrl_pkg"
},
+ // Interface with SRAM scrambling wrapper init interface
+ { struct: "sram_scr_init"
+ type: "req_rsp"
+ name: "sram_scr_init"
+ act: "req"
+ default: "'0"
+ package: "sram_ctrl_pkg"
+ },
// Broadcast from LC
{ struct: "lc_tx"
type: "uni"
@@ -204,8 +218,8 @@
}
{ name: "CTRL",
desc: "SRAM ctrl register.",
- swaccess: "wo",
- hwaccess: "hro",
+ swaccess: "rw",
+ hwaccess: "hrw",
hwqe: "true",
hwext: "true",
regwen: "CTRL_REGWEN"
@@ -223,6 +237,14 @@
a key request is pending has no effect.
'''
},
+ { bits: "1",
+ name: "INIT",
+ desc: '''
+ Write 1 to request memory init.
+ The init process is seeded using the a nonce that is supplied during the init process.
+ The resulting memory is programmed with random data instead of deterministic values.
+ '''
+ },
]
},
