commit 94febdbe378603da3cbe5fd12d9fdd77b2f819c6
author Weicai Yang <weicai@google.com> Wed Aug 31 16:58:58 2022 -0700
committer weicaiyang <49293026+weicaiyang@users.noreply.github.com> Thu Sep 01 10:14:52 2022 -0700
tree 1a60228fa992521931a0da4e3c396ac5b5c4e530
parent 6d7e5dd10741acda2fe7b8ab16cb48a4d4fe97fa

[dv] Fix CSR sequence with shadow regs

Disabled TL abort for shadow reg.

if there is any shadow reg, we shouldn't abort TL access, otherwise, it may do only one
write to the shadow reg, which may cause an unexpected recoverable error.

Signed-off-by: Weicai Yang <weicai@google.com>

hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv

diff --git a/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv b/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv
index 1da4ab3..6b98dbc 100644
--- a/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv
+++ b/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv
@@ -634,8 +634,19 @@
                             bit    do_rand_wr_and_reset = 1,
                             dv_base_reg_block models[$] = {},
                             string ral_name = "");
+    bit has_shadow_reg;
+    dv_base_reg regs[$];
 
-    if (csr_access_abort_pct.rand_mode()) begin
+    // if there is any shadow reg, we shouldn't abort TL access, otherwise, it may do only one
+    // write to the shadow reg, which may cause an unexpected recoverable error.
+    foreach (cfg.ral_models[i]) cfg.ral_models[i].get_dv_base_regs(regs);
+    foreach (regs[i]) begin
+      if (regs[i].get_is_shadowed()) begin
+        has_shadow_reg = 1;
+        break;
+      end
+    end
+    if (!has_shadow_reg && csr_access_abort_pct.rand_mode()) begin
       `DV_CHECK_MEMBER_RANDOMIZE_FATAL(csr_access_abort_pct)
     end else begin
       csr_access_abort_pct = 0;