[top] Auto generate files
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index df11ded..7aab762 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -813,6 +813,19 @@
index: -1
}
{
+ struct: keymgr_flash
+ type: uni
+ name: keymgr
+ act: req
+ package: flash_ctrl_pkg
+ inst_name: flash_ctrl
+ width: 1
+ default: ""
+ top_type: broadcast
+ top_signame: flash_ctrl_keymgr
+ index: -1
+ }
+ {
struct: tl
package: tlul_pkg
type: req_rsp
@@ -2287,6 +2300,151 @@
]
}
{
+ name: keymgr
+ type: keymgr
+ clock_srcs:
+ {
+ clk_i: main
+ }
+ clock_group: secure
+ reset_connections:
+ {
+ rst_ni: sys
+ }
+ base_addr: 0x401a0000
+ clock_reset_export: []
+ clock_connections:
+ {
+ clk_i: clkmgr_clocks.clk_main_secure
+ }
+ size: 0x1000
+ bus_device: tlul
+ bus_host: none
+ available_input_list: []
+ available_output_list: []
+ available_inout_list: []
+ interrupt_list:
+ [
+ {
+ name: op_done
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: interrupt
+ }
+ {
+ name: err
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: interrupt
+ }
+ ]
+ alert_list:
+ [
+ {
+ name: err
+ width: 1
+ type: alert
+ async: 0
+ }
+ ]
+ wakeup_list: []
+ scan: "false"
+ scan_reset: "false"
+ inter_signal_list:
+ [
+ {
+ struct: hw_key
+ type: uni
+ name: aes_key
+ act: req
+ package: keymgr_pkg
+ inst_name: keymgr
+ index: -1
+ }
+ {
+ struct: hw_key
+ type: uni
+ name: hmac_key
+ act: req
+ package: keymgr_pkg
+ inst_name: keymgr
+ index: -1
+ }
+ {
+ struct: hw_key
+ type: uni
+ name: kmac_key
+ act: req
+ package: keymgr_pkg
+ inst_name: keymgr
+ index: -1
+ }
+ {
+ struct: kmac_data
+ type: req_rsp
+ name: kmac_data
+ act: req
+ package: keymgr_pkg
+ inst_name: keymgr
+ index: -1
+ }
+ {
+ struct: lc_data
+ type: uni
+ name: lc
+ act: rcv
+ package: keymgr_pkg
+ inst_name: keymgr
+ index: -1
+ }
+ {
+ struct: otp_data
+ type: uni
+ name: otp
+ act: rcv
+ package: keymgr_pkg
+ inst_name: keymgr
+ index: -1
+ }
+ {
+ struct: keymgr_flash
+ type: uni
+ name: flash
+ act: rcv
+ package: flash_ctrl_pkg
+ inst_name: keymgr
+ width: 1
+ default: ""
+ top_signame: flash_ctrl_keymgr
+ index: -1
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: keymgr
+ width: 1
+ default: ""
+ top_signame: keymgr_tl
+ index: -1
+ }
+ ]
+ }
+ {
name: otbn
type: otbn
clock_srcs:
@@ -2564,6 +2722,10 @@
[
clkmgr.pwr
]
+ flash_ctrl.keymgr:
+ [
+ keymgr.flash
+ ]
pwrmgr.wakeups:
[
pinmux.aon_wkup_req
@@ -2620,6 +2782,10 @@
[
main.tl_otbn
]
+ keymgr.tl:
+ [
+ main.tl_keymgr
+ ]
uart.tl:
[
peri.tl_uart
@@ -2738,6 +2904,7 @@
alert_handler
nmi_gen
otbn
+ keymgr
]
dm_sba:
[
@@ -3060,6 +3227,24 @@
stub: false
pipeline: "true"
}
+ {
+ name: keymgr
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ pipeline_byp: "false"
+ inst_type: keymgr
+ addr_range:
+ [
+ {
+ base_addr: 0x401a0000
+ size_byte: 0x1000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: "true"
+ }
]
clock: clk_main_i
type: xbar
@@ -3269,6 +3454,18 @@
top_signame: otbn_tl
index: -1
}
+ {
+ struct: tl
+ type: req_rsp
+ name: tl_keymgr
+ act: req
+ package: tlul_pkg
+ inst_name: main
+ width: 1
+ default: ""
+ top_signame: keymgr_tl
+ index: -1
+ }
]
}
{
@@ -3680,6 +3877,7 @@
usbdev
pwrmgr
otbn
+ keymgr
]
interrupt:
[
@@ -4333,6 +4531,32 @@
type: interrupt
module_name: otbn
}
+ {
+ name: keymgr_op_done
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: interrupt
+ module_name: keymgr
+ }
+ {
+ name: keymgr_err
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: interrupt
+ module_name: keymgr
+ }
]
alert_module:
[
@@ -4340,6 +4564,7 @@
hmac
otbn
sensor_ctrl
+ keymgr
]
alert:
[
@@ -4392,6 +4617,13 @@
async: 1
module_name: sensor_ctrl
}
+ {
+ name: keymgr_err
+ width: 1
+ type: alert
+ async: 0
+ module_name: keymgr
+ }
]
pinmux:
{
@@ -4825,6 +5057,19 @@
index: -1
}
{
+ struct: keymgr_flash
+ type: uni
+ name: keymgr
+ act: req
+ package: flash_ctrl_pkg
+ inst_name: flash_ctrl
+ width: 1
+ default: ""
+ top_type: broadcast
+ top_signame: flash_ctrl_keymgr
+ index: -1
+ }
+ {
struct: tl
package: tlul_pkg
type: req_rsp
@@ -5392,6 +5637,84 @@
index: -1
}
{
+ struct: hw_key
+ type: uni
+ name: aes_key
+ act: req
+ package: keymgr_pkg
+ inst_name: keymgr
+ index: -1
+ }
+ {
+ struct: hw_key
+ type: uni
+ name: hmac_key
+ act: req
+ package: keymgr_pkg
+ inst_name: keymgr
+ index: -1
+ }
+ {
+ struct: hw_key
+ type: uni
+ name: kmac_key
+ act: req
+ package: keymgr_pkg
+ inst_name: keymgr
+ index: -1
+ }
+ {
+ struct: kmac_data
+ type: req_rsp
+ name: kmac_data
+ act: req
+ package: keymgr_pkg
+ inst_name: keymgr
+ index: -1
+ }
+ {
+ struct: lc_data
+ type: uni
+ name: lc
+ act: rcv
+ package: keymgr_pkg
+ inst_name: keymgr
+ index: -1
+ }
+ {
+ struct: otp_data
+ type: uni
+ name: otp
+ act: rcv
+ package: keymgr_pkg
+ inst_name: keymgr
+ index: -1
+ }
+ {
+ struct: keymgr_flash
+ type: uni
+ name: flash
+ act: rcv
+ package: flash_ctrl_pkg
+ inst_name: keymgr
+ width: 1
+ default: ""
+ top_signame: flash_ctrl_keymgr
+ index: -1
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: keymgr
+ width: 1
+ default: ""
+ top_signame: keymgr_tl
+ index: -1
+ }
+ {
name: idle
type: uni
struct: logic
@@ -5679,6 +6002,18 @@
{
struct: tl
type: req_rsp
+ name: tl_keymgr
+ act: req
+ package: tlul_pkg
+ inst_name: main
+ width: 1
+ default: ""
+ top_signame: keymgr_tl
+ index: -1
+ }
+ {
+ struct: tl
+ type: req_rsp
name: tl_main
act: rsp
package: tlul_pkg
@@ -6036,6 +6371,14 @@
default: ""
}
{
+ package: flash_ctrl_pkg
+ struct: keymgr_flash
+ signame: flash_ctrl_keymgr
+ width: 1
+ type: uni
+ default: ""
+ }
+ {
package: ""
struct: logic
signame: pwrmgr_wakeups
@@ -6254,6 +6597,22 @@
{
package: tlul_pkg
struct: tl_h2d
+ signame: keymgr_tl_req
+ width: 1
+ type: req_rsp
+ default: ""
+ }
+ {
+ package: tlul_pkg
+ struct: tl_d2h
+ signame: keymgr_tl_rsp
+ width: 1
+ type: req_rsp
+ default: ""
+ }
+ {
+ package: tlul_pkg
+ struct: tl_h2d
signame: uart_tl_req
width: 1
type: req_rsp
diff --git a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
index 1fa8670..0127aef 100644
--- a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
+++ b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
@@ -44,6 +44,7 @@
tl_if alert_handler_tl_if(clk_main, rst_n);
tl_if nmi_gen_tl_if(clk_main, rst_n);
tl_if otbn_tl_if(clk_main, rst_n);
+tl_if keymgr_tl_if(clk_main, rst_n);
tl_if uart_tl_if(clk_io_div4, rst_n);
tl_if gpio_tl_if(clk_io_div4, rst_n);
tl_if spi_device_tl_if(clk_io_div4, rst_n);
@@ -98,6 +99,7 @@
`DRIVE_TL_DEVICE_IF(alert_handler, alert_handler, tl)
`DRIVE_TL_DEVICE_IF(nmi_gen, nmi_gen, tl)
`DRIVE_TL_DEVICE_IF(otbn, otbn, tl)
+ `DRIVE_TL_DEVICE_IF(keymgr, keymgr, tl)
`DRIVE_TL_DEVICE_IF(uart, uart, tl)
`DRIVE_TL_DEVICE_IF(gpio, gpio, tl)
`DRIVE_TL_DEVICE_IF(spi_device, spi_device, tl)
diff --git a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
index c18cacd..bdb366e 100644
--- a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
+++ b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
@@ -46,6 +46,9 @@
'{"otbn", '{
'{32'h50000000, 32'h503fffff}
}},
+ '{"keymgr", '{
+ '{32'h401a0000, 32'h401a0fff}
+ }},
'{"uart", '{
'{32'h40000000, 32'h40000fff}
}},
@@ -112,7 +115,8 @@
"padctrl",
"alert_handler",
"nmi_gen",
- "otbn"}}
+ "otbn",
+ "keymgr"}}
,
'{"dm_sba", 2, '{
"rom",
diff --git a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
index 5a1e996..1a9f721 100644
--- a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
+++ b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
@@ -30,7 +30,7 @@
{ name: "NAlerts",
desc: "Number of peripheral inputs",
type: "int",
- default: "13",
+ default: "14",
local: "true"
},
{ name: "EscCntDw",
@@ -54,7 +54,7 @@
{ name: "AsyncOn",
desc: "Number of peripheral outputs",
type: "logic [NAlerts-1:0]",
- default: "13'b1111111000000",
+ default: "14'b01111111000000",
local: "true"
},
{ name: "N_CLASSES",
diff --git a/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_env_pkg__params.sv b/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_env_pkg__params.sv
index d5abde7..6aab9b6 100644
--- a/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_env_pkg__params.sv
+++ b/hw/top_earlgrey/ip/alert_handler/dv/alert_handler_env_pkg__params.sv
@@ -10,5 +10,5 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-parameter uint NUM_ALERTS = 13;
-parameter bit [NUM_ALERTS-1:0] ASYNC_ON = 13'b1111111000000;
+parameter uint NUM_ALERTS = 14;
+parameter bit [NUM_ALERTS-1:0] ASYNC_ON = 14'b01111111000000;
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
index 2135bc2..e732bd3 100644
--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
@@ -7,11 +7,11 @@
package alert_handler_reg_pkg;
// Param list
- parameter int NAlerts = 13;
+ parameter int NAlerts = 14;
parameter int EscCntDw = 32;
parameter int AccuCntDw = 16;
parameter int LfsrSeed = 2147483647;
- parameter logic [NAlerts-1:0] AsyncOn = 13'b1111111000000;
+ parameter logic [NAlerts-1:0] AsyncOn = 14'b01111111000000;
parameter int N_CLASSES = 4;
parameter int N_ESC_SEV = 4;
parameter int N_PHASES = 4;
@@ -455,14 +455,14 @@
// Register to internal design logic //
///////////////////////////////////////
typedef struct packed {
- alert_handler_reg2hw_intr_state_reg_t intr_state; // [876:873]
- alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [872:869]
- alert_handler_reg2hw_intr_test_reg_t intr_test; // [868:861]
- alert_handler_reg2hw_regen_reg_t regen; // [860:860]
- alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [859:836]
- alert_handler_reg2hw_alert_en_mreg_t [12:0] alert_en; // [835:823]
- alert_handler_reg2hw_alert_class_mreg_t [12:0] alert_class; // [822:797]
- alert_handler_reg2hw_alert_cause_mreg_t [12:0] alert_cause; // [796:784]
+ alert_handler_reg2hw_intr_state_reg_t intr_state; // [880:877]
+ alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [876:873]
+ alert_handler_reg2hw_intr_test_reg_t intr_test; // [872:865]
+ alert_handler_reg2hw_regen_reg_t regen; // [864:864]
+ alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [863:840]
+ alert_handler_reg2hw_alert_en_mreg_t [13:0] alert_en; // [839:826]
+ alert_handler_reg2hw_alert_class_mreg_t [13:0] alert_class; // [825:798]
+ alert_handler_reg2hw_alert_cause_mreg_t [13:0] alert_cause; // [797:784]
alert_handler_reg2hw_loc_alert_en_mreg_t [3:0] loc_alert_en; // [783:780]
alert_handler_reg2hw_loc_alert_class_mreg_t [3:0] loc_alert_class; // [779:772]
alert_handler_reg2hw_loc_alert_cause_mreg_t [3:0] loc_alert_cause; // [771:768]
@@ -504,8 +504,8 @@
// Internal design logic to register //
///////////////////////////////////////
typedef struct packed {
- alert_handler_hw2reg_intr_state_reg_t intr_state; // [253:250]
- alert_handler_hw2reg_alert_cause_mreg_t [12:0] alert_cause; // [249:224]
+ alert_handler_hw2reg_intr_state_reg_t intr_state; // [255:252]
+ alert_handler_hw2reg_alert_cause_mreg_t [13:0] alert_cause; // [251:224]
alert_handler_hw2reg_loc_alert_cause_mreg_t [3:0] loc_alert_cause; // [223:216]
alert_handler_hw2reg_classa_clren_reg_t classa_clren; // [215:216]
alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [215:216]
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
index 32496b9..38c7628 100644
--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
@@ -148,6 +148,9 @@
logic alert_en_en_a_12_qs;
logic alert_en_en_a_12_wd;
logic alert_en_en_a_12_we;
+ logic alert_en_en_a_13_qs;
+ logic alert_en_en_a_13_wd;
+ logic alert_en_en_a_13_we;
logic [1:0] alert_class_class_a_0_qs;
logic [1:0] alert_class_class_a_0_wd;
logic alert_class_class_a_0_we;
@@ -187,6 +190,9 @@
logic [1:0] alert_class_class_a_12_qs;
logic [1:0] alert_class_class_a_12_wd;
logic alert_class_class_a_12_we;
+ logic [1:0] alert_class_class_a_13_qs;
+ logic [1:0] alert_class_class_a_13_wd;
+ logic alert_class_class_a_13_we;
logic alert_cause_a_0_qs;
logic alert_cause_a_0_wd;
logic alert_cause_a_0_we;
@@ -226,6 +232,9 @@
logic alert_cause_a_12_qs;
logic alert_cause_a_12_wd;
logic alert_cause_a_12_we;
+ logic alert_cause_a_13_qs;
+ logic alert_cause_a_13_wd;
+ logic alert_cause_a_13_we;
logic loc_alert_en_en_la_0_qs;
logic loc_alert_en_en_la_0_wd;
logic loc_alert_en_en_la_0_we;
@@ -1170,6 +1179,32 @@
);
+ // F[en_a_13]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_alert_en_en_a_13 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (alert_en_en_a_13_we & regen_qs),
+ .wd (alert_en_en_a_13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en[13].q ),
+
+ // to register interface (read)
+ .qs (alert_en_en_a_13_qs)
+ );
+
+
// Subregister 0 of Multireg alert_class
@@ -1513,6 +1548,32 @@
);
+ // F[class_a_13]: 27:26
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_alert_class_class_a_13 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (alert_class_class_a_13_we & regen_qs),
+ .wd (alert_class_class_a_13_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class[13].q ),
+
+ // to register interface (read)
+ .qs (alert_class_class_a_13_qs)
+ );
+
+
// Subregister 0 of Multireg alert_cause
@@ -1856,6 +1917,32 @@
);
+ // F[a_13]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_alert_cause_a_13 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (alert_cause_a_13_we),
+ .wd (alert_cause_a_13_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[13].de),
+ .d (hw2reg.alert_cause[13].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[13].q ),
+
+ // to register interface (read)
+ .qs (alert_cause_a_13_qs)
+ );
+
+
// Subregister 0 of Multireg loc_alert_en
@@ -4497,6 +4584,9 @@
assign alert_en_en_a_12_we = addr_hit[5] & reg_we & ~wr_err;
assign alert_en_en_a_12_wd = reg_wdata[12];
+ assign alert_en_en_a_13_we = addr_hit[5] & reg_we & ~wr_err;
+ assign alert_en_en_a_13_wd = reg_wdata[13];
+
assign alert_class_class_a_0_we = addr_hit[6] & reg_we & ~wr_err;
assign alert_class_class_a_0_wd = reg_wdata[1:0];
@@ -4536,6 +4626,9 @@
assign alert_class_class_a_12_we = addr_hit[6] & reg_we & ~wr_err;
assign alert_class_class_a_12_wd = reg_wdata[25:24];
+ assign alert_class_class_a_13_we = addr_hit[6] & reg_we & ~wr_err;
+ assign alert_class_class_a_13_wd = reg_wdata[27:26];
+
assign alert_cause_a_0_we = addr_hit[7] & reg_we & ~wr_err;
assign alert_cause_a_0_wd = reg_wdata[0];
@@ -4575,6 +4668,9 @@
assign alert_cause_a_12_we = addr_hit[7] & reg_we & ~wr_err;
assign alert_cause_a_12_wd = reg_wdata[12];
+ assign alert_cause_a_13_we = addr_hit[7] & reg_we & ~wr_err;
+ assign alert_cause_a_13_wd = reg_wdata[13];
+
assign loc_alert_en_en_la_0_we = addr_hit[8] & reg_we & ~wr_err;
assign loc_alert_en_en_la_0_wd = reg_wdata[0];
@@ -4898,6 +4994,7 @@
reg_rdata_next[10] = alert_en_en_a_10_qs;
reg_rdata_next[11] = alert_en_en_a_11_qs;
reg_rdata_next[12] = alert_en_en_a_12_qs;
+ reg_rdata_next[13] = alert_en_en_a_13_qs;
end
addr_hit[6]: begin
@@ -4914,6 +5011,7 @@
reg_rdata_next[21:20] = alert_class_class_a_10_qs;
reg_rdata_next[23:22] = alert_class_class_a_11_qs;
reg_rdata_next[25:24] = alert_class_class_a_12_qs;
+ reg_rdata_next[27:26] = alert_class_class_a_13_qs;
end
addr_hit[7]: begin
@@ -4930,6 +5028,7 @@
reg_rdata_next[10] = alert_cause_a_10_qs;
reg_rdata_next[11] = alert_cause_a_11_qs;
reg_rdata_next[12] = alert_cause_a_12_qs;
+ reg_rdata_next[13] = alert_cause_a_13_qs;
end
addr_hit[8]: begin
diff --git a/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson b/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson
index dc83f40..338d24d 100644
--- a/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson
+++ b/hw/top_earlgrey/ip/rv_plic/data/autogen/rv_plic.hjson
@@ -25,7 +25,7 @@
{ name: "NumSrc",
desc: "Number of interrupt sources",
type: "int",
- default: "82",
+ default: "84",
local: "true"
},
{ name: "NumTarget",
@@ -725,6 +725,22 @@
{ bits: "1:0" }
],
}
+ { name: "PRIO82",
+ desc: "Interrupt Source 82 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
+ { name: "PRIO83",
+ desc: "Interrupt Source 83 Priority",
+ swaccess: "rw",
+ hwaccess: "hro",
+ fields: [
+ { bits: "1:0" }
+ ],
+ }
{ skipto: "512" }
{ multireg: {
name: "IE0",
diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv
index cd6e64e..6853d57 100644
--- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv
+++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic.sv
@@ -176,11 +176,13 @@
assign prio[79] = reg2hw.prio79.q;
assign prio[80] = reg2hw.prio80.q;
assign prio[81] = reg2hw.prio81.q;
+ assign prio[82] = reg2hw.prio82.q;
+ assign prio[83] = reg2hw.prio83.q;
//////////////////////
// Interrupt Enable //
//////////////////////
- for (genvar s = 0; s < 82; s++) begin : gen_ie0
+ for (genvar s = 0; s < 84; s++) begin : gen_ie0
assign ie[0][s] = reg2hw.ie0[s].q;
end
@@ -206,7 +208,7 @@
////////
// IP //
////////
- for (genvar s = 0; s < 82; s++) begin : gen_ip
+ for (genvar s = 0; s < 84; s++) begin : gen_ip
assign hw2reg.ip[s].de = 1'b1; // Always write
assign hw2reg.ip[s].d = ip[s];
end
@@ -214,7 +216,7 @@
///////////////////////////////////
// Detection:: 0: Level, 1: Edge //
///////////////////////////////////
- for (genvar s = 0; s < 82; s++) begin : gen_le
+ for (genvar s = 0; s < 84; s++) begin : gen_le
assign le[s] = reg2hw.le[s].q;
end
diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv
index dacec8b..f8d828b 100644
--- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv
@@ -7,7 +7,7 @@
package rv_plic_reg_pkg;
// Param list
- parameter int NumSrc = 82;
+ parameter int NumSrc = 84;
parameter int NumTarget = 1;
parameter int PrioWidth = 2;
@@ -347,6 +347,14 @@
} rv_plic_reg2hw_prio81_reg_t;
typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio82_reg_t;
+
+ typedef struct packed {
+ logic [1:0] q;
+ } rv_plic_reg2hw_prio83_reg_t;
+
+ typedef struct packed {
logic q;
} rv_plic_reg2hw_ie0_mreg_t;
@@ -379,90 +387,92 @@
// Register to internal design logic //
///////////////////////////////////////
typedef struct packed {
- rv_plic_reg2hw_le_mreg_t [81:0] le; // [339:258]
- rv_plic_reg2hw_prio0_reg_t prio0; // [257:256]
- rv_plic_reg2hw_prio1_reg_t prio1; // [255:254]
- rv_plic_reg2hw_prio2_reg_t prio2; // [253:252]
- rv_plic_reg2hw_prio3_reg_t prio3; // [251:250]
- rv_plic_reg2hw_prio4_reg_t prio4; // [249:248]
- rv_plic_reg2hw_prio5_reg_t prio5; // [247:246]
- rv_plic_reg2hw_prio6_reg_t prio6; // [245:244]
- rv_plic_reg2hw_prio7_reg_t prio7; // [243:242]
- rv_plic_reg2hw_prio8_reg_t prio8; // [241:240]
- rv_plic_reg2hw_prio9_reg_t prio9; // [239:238]
- rv_plic_reg2hw_prio10_reg_t prio10; // [237:236]
- rv_plic_reg2hw_prio11_reg_t prio11; // [235:234]
- rv_plic_reg2hw_prio12_reg_t prio12; // [233:232]
- rv_plic_reg2hw_prio13_reg_t prio13; // [231:230]
- rv_plic_reg2hw_prio14_reg_t prio14; // [229:228]
- rv_plic_reg2hw_prio15_reg_t prio15; // [227:226]
- rv_plic_reg2hw_prio16_reg_t prio16; // [225:224]
- rv_plic_reg2hw_prio17_reg_t prio17; // [223:222]
- rv_plic_reg2hw_prio18_reg_t prio18; // [221:220]
- rv_plic_reg2hw_prio19_reg_t prio19; // [219:218]
- rv_plic_reg2hw_prio20_reg_t prio20; // [217:216]
- rv_plic_reg2hw_prio21_reg_t prio21; // [215:214]
- rv_plic_reg2hw_prio22_reg_t prio22; // [213:212]
- rv_plic_reg2hw_prio23_reg_t prio23; // [211:210]
- rv_plic_reg2hw_prio24_reg_t prio24; // [209:208]
- rv_plic_reg2hw_prio25_reg_t prio25; // [207:206]
- rv_plic_reg2hw_prio26_reg_t prio26; // [205:204]
- rv_plic_reg2hw_prio27_reg_t prio27; // [203:202]
- rv_plic_reg2hw_prio28_reg_t prio28; // [201:200]
- rv_plic_reg2hw_prio29_reg_t prio29; // [199:198]
- rv_plic_reg2hw_prio30_reg_t prio30; // [197:196]
- rv_plic_reg2hw_prio31_reg_t prio31; // [195:194]
- rv_plic_reg2hw_prio32_reg_t prio32; // [193:192]
- rv_plic_reg2hw_prio33_reg_t prio33; // [191:190]
- rv_plic_reg2hw_prio34_reg_t prio34; // [189:188]
- rv_plic_reg2hw_prio35_reg_t prio35; // [187:186]
- rv_plic_reg2hw_prio36_reg_t prio36; // [185:184]
- rv_plic_reg2hw_prio37_reg_t prio37; // [183:182]
- rv_plic_reg2hw_prio38_reg_t prio38; // [181:180]
- rv_plic_reg2hw_prio39_reg_t prio39; // [179:178]
- rv_plic_reg2hw_prio40_reg_t prio40; // [177:176]
- rv_plic_reg2hw_prio41_reg_t prio41; // [175:174]
- rv_plic_reg2hw_prio42_reg_t prio42; // [173:172]
- rv_plic_reg2hw_prio43_reg_t prio43; // [171:170]
- rv_plic_reg2hw_prio44_reg_t prio44; // [169:168]
- rv_plic_reg2hw_prio45_reg_t prio45; // [167:166]
- rv_plic_reg2hw_prio46_reg_t prio46; // [165:164]
- rv_plic_reg2hw_prio47_reg_t prio47; // [163:162]
- rv_plic_reg2hw_prio48_reg_t prio48; // [161:160]
- rv_plic_reg2hw_prio49_reg_t prio49; // [159:158]
- rv_plic_reg2hw_prio50_reg_t prio50; // [157:156]
- rv_plic_reg2hw_prio51_reg_t prio51; // [155:154]
- rv_plic_reg2hw_prio52_reg_t prio52; // [153:152]
- rv_plic_reg2hw_prio53_reg_t prio53; // [151:150]
- rv_plic_reg2hw_prio54_reg_t prio54; // [149:148]
- rv_plic_reg2hw_prio55_reg_t prio55; // [147:146]
- rv_plic_reg2hw_prio56_reg_t prio56; // [145:144]
- rv_plic_reg2hw_prio57_reg_t prio57; // [143:142]
- rv_plic_reg2hw_prio58_reg_t prio58; // [141:140]
- rv_plic_reg2hw_prio59_reg_t prio59; // [139:138]
- rv_plic_reg2hw_prio60_reg_t prio60; // [137:136]
- rv_plic_reg2hw_prio61_reg_t prio61; // [135:134]
- rv_plic_reg2hw_prio62_reg_t prio62; // [133:132]
- rv_plic_reg2hw_prio63_reg_t prio63; // [131:130]
- rv_plic_reg2hw_prio64_reg_t prio64; // [129:128]
- rv_plic_reg2hw_prio65_reg_t prio65; // [127:126]
- rv_plic_reg2hw_prio66_reg_t prio66; // [125:124]
- rv_plic_reg2hw_prio67_reg_t prio67; // [123:122]
- rv_plic_reg2hw_prio68_reg_t prio68; // [121:120]
- rv_plic_reg2hw_prio69_reg_t prio69; // [119:118]
- rv_plic_reg2hw_prio70_reg_t prio70; // [117:116]
- rv_plic_reg2hw_prio71_reg_t prio71; // [115:114]
- rv_plic_reg2hw_prio72_reg_t prio72; // [113:112]
- rv_plic_reg2hw_prio73_reg_t prio73; // [111:110]
- rv_plic_reg2hw_prio74_reg_t prio74; // [109:108]
- rv_plic_reg2hw_prio75_reg_t prio75; // [107:106]
- rv_plic_reg2hw_prio76_reg_t prio76; // [105:104]
- rv_plic_reg2hw_prio77_reg_t prio77; // [103:102]
- rv_plic_reg2hw_prio78_reg_t prio78; // [101:100]
- rv_plic_reg2hw_prio79_reg_t prio79; // [99:98]
- rv_plic_reg2hw_prio80_reg_t prio80; // [97:96]
- rv_plic_reg2hw_prio81_reg_t prio81; // [95:94]
- rv_plic_reg2hw_ie0_mreg_t [81:0] ie0; // [93:12]
+ rv_plic_reg2hw_le_mreg_t [83:0] le; // [347:264]
+ rv_plic_reg2hw_prio0_reg_t prio0; // [263:262]
+ rv_plic_reg2hw_prio1_reg_t prio1; // [261:260]
+ rv_plic_reg2hw_prio2_reg_t prio2; // [259:258]
+ rv_plic_reg2hw_prio3_reg_t prio3; // [257:256]
+ rv_plic_reg2hw_prio4_reg_t prio4; // [255:254]
+ rv_plic_reg2hw_prio5_reg_t prio5; // [253:252]
+ rv_plic_reg2hw_prio6_reg_t prio6; // [251:250]
+ rv_plic_reg2hw_prio7_reg_t prio7; // [249:248]
+ rv_plic_reg2hw_prio8_reg_t prio8; // [247:246]
+ rv_plic_reg2hw_prio9_reg_t prio9; // [245:244]
+ rv_plic_reg2hw_prio10_reg_t prio10; // [243:242]
+ rv_plic_reg2hw_prio11_reg_t prio11; // [241:240]
+ rv_plic_reg2hw_prio12_reg_t prio12; // [239:238]
+ rv_plic_reg2hw_prio13_reg_t prio13; // [237:236]
+ rv_plic_reg2hw_prio14_reg_t prio14; // [235:234]
+ rv_plic_reg2hw_prio15_reg_t prio15; // [233:232]
+ rv_plic_reg2hw_prio16_reg_t prio16; // [231:230]
+ rv_plic_reg2hw_prio17_reg_t prio17; // [229:228]
+ rv_plic_reg2hw_prio18_reg_t prio18; // [227:226]
+ rv_plic_reg2hw_prio19_reg_t prio19; // [225:224]
+ rv_plic_reg2hw_prio20_reg_t prio20; // [223:222]
+ rv_plic_reg2hw_prio21_reg_t prio21; // [221:220]
+ rv_plic_reg2hw_prio22_reg_t prio22; // [219:218]
+ rv_plic_reg2hw_prio23_reg_t prio23; // [217:216]
+ rv_plic_reg2hw_prio24_reg_t prio24; // [215:214]
+ rv_plic_reg2hw_prio25_reg_t prio25; // [213:212]
+ rv_plic_reg2hw_prio26_reg_t prio26; // [211:210]
+ rv_plic_reg2hw_prio27_reg_t prio27; // [209:208]
+ rv_plic_reg2hw_prio28_reg_t prio28; // [207:206]
+ rv_plic_reg2hw_prio29_reg_t prio29; // [205:204]
+ rv_plic_reg2hw_prio30_reg_t prio30; // [203:202]
+ rv_plic_reg2hw_prio31_reg_t prio31; // [201:200]
+ rv_plic_reg2hw_prio32_reg_t prio32; // [199:198]
+ rv_plic_reg2hw_prio33_reg_t prio33; // [197:196]
+ rv_plic_reg2hw_prio34_reg_t prio34; // [195:194]
+ rv_plic_reg2hw_prio35_reg_t prio35; // [193:192]
+ rv_plic_reg2hw_prio36_reg_t prio36; // [191:190]
+ rv_plic_reg2hw_prio37_reg_t prio37; // [189:188]
+ rv_plic_reg2hw_prio38_reg_t prio38; // [187:186]
+ rv_plic_reg2hw_prio39_reg_t prio39; // [185:184]
+ rv_plic_reg2hw_prio40_reg_t prio40; // [183:182]
+ rv_plic_reg2hw_prio41_reg_t prio41; // [181:180]
+ rv_plic_reg2hw_prio42_reg_t prio42; // [179:178]
+ rv_plic_reg2hw_prio43_reg_t prio43; // [177:176]
+ rv_plic_reg2hw_prio44_reg_t prio44; // [175:174]
+ rv_plic_reg2hw_prio45_reg_t prio45; // [173:172]
+ rv_plic_reg2hw_prio46_reg_t prio46; // [171:170]
+ rv_plic_reg2hw_prio47_reg_t prio47; // [169:168]
+ rv_plic_reg2hw_prio48_reg_t prio48; // [167:166]
+ rv_plic_reg2hw_prio49_reg_t prio49; // [165:164]
+ rv_plic_reg2hw_prio50_reg_t prio50; // [163:162]
+ rv_plic_reg2hw_prio51_reg_t prio51; // [161:160]
+ rv_plic_reg2hw_prio52_reg_t prio52; // [159:158]
+ rv_plic_reg2hw_prio53_reg_t prio53; // [157:156]
+ rv_plic_reg2hw_prio54_reg_t prio54; // [155:154]
+ rv_plic_reg2hw_prio55_reg_t prio55; // [153:152]
+ rv_plic_reg2hw_prio56_reg_t prio56; // [151:150]
+ rv_plic_reg2hw_prio57_reg_t prio57; // [149:148]
+ rv_plic_reg2hw_prio58_reg_t prio58; // [147:146]
+ rv_plic_reg2hw_prio59_reg_t prio59; // [145:144]
+ rv_plic_reg2hw_prio60_reg_t prio60; // [143:142]
+ rv_plic_reg2hw_prio61_reg_t prio61; // [141:140]
+ rv_plic_reg2hw_prio62_reg_t prio62; // [139:138]
+ rv_plic_reg2hw_prio63_reg_t prio63; // [137:136]
+ rv_plic_reg2hw_prio64_reg_t prio64; // [135:134]
+ rv_plic_reg2hw_prio65_reg_t prio65; // [133:132]
+ rv_plic_reg2hw_prio66_reg_t prio66; // [131:130]
+ rv_plic_reg2hw_prio67_reg_t prio67; // [129:128]
+ rv_plic_reg2hw_prio68_reg_t prio68; // [127:126]
+ rv_plic_reg2hw_prio69_reg_t prio69; // [125:124]
+ rv_plic_reg2hw_prio70_reg_t prio70; // [123:122]
+ rv_plic_reg2hw_prio71_reg_t prio71; // [121:120]
+ rv_plic_reg2hw_prio72_reg_t prio72; // [119:118]
+ rv_plic_reg2hw_prio73_reg_t prio73; // [117:116]
+ rv_plic_reg2hw_prio74_reg_t prio74; // [115:114]
+ rv_plic_reg2hw_prio75_reg_t prio75; // [113:112]
+ rv_plic_reg2hw_prio76_reg_t prio76; // [111:110]
+ rv_plic_reg2hw_prio77_reg_t prio77; // [109:108]
+ rv_plic_reg2hw_prio78_reg_t prio78; // [107:106]
+ rv_plic_reg2hw_prio79_reg_t prio79; // [105:104]
+ rv_plic_reg2hw_prio80_reg_t prio80; // [103:102]
+ rv_plic_reg2hw_prio81_reg_t prio81; // [101:100]
+ rv_plic_reg2hw_prio82_reg_t prio82; // [99:98]
+ rv_plic_reg2hw_prio83_reg_t prio83; // [97:96]
+ rv_plic_reg2hw_ie0_mreg_t [83:0] ie0; // [95:12]
rv_plic_reg2hw_threshold0_reg_t threshold0; // [11:10]
rv_plic_reg2hw_cc0_reg_t cc0; // [9:1]
rv_plic_reg2hw_msip0_reg_t msip0; // [0:0]
@@ -472,7 +482,7 @@
// Internal design logic to register //
///////////////////////////////////////
typedef struct packed {
- rv_plic_hw2reg_ip_mreg_t [81:0] ip; // [170:7]
+ rv_plic_hw2reg_ip_mreg_t [83:0] ip; // [174:7]
rv_plic_hw2reg_cc0_reg_t cc0; // [6:-2]
} rv_plic_hw2reg_t;
@@ -565,6 +575,8 @@
parameter logic [9:0] RV_PLIC_PRIO79_OFFSET = 10'h 154;
parameter logic [9:0] RV_PLIC_PRIO80_OFFSET = 10'h 158;
parameter logic [9:0] RV_PLIC_PRIO81_OFFSET = 10'h 15c;
+ parameter logic [9:0] RV_PLIC_PRIO82_OFFSET = 10'h 160;
+ parameter logic [9:0] RV_PLIC_PRIO83_OFFSET = 10'h 164;
parameter logic [9:0] RV_PLIC_IE0_0_OFFSET = 10'h 200;
parameter logic [9:0] RV_PLIC_IE0_1_OFFSET = 10'h 204;
parameter logic [9:0] RV_PLIC_IE0_2_OFFSET = 10'h 208;
@@ -663,6 +675,8 @@
RV_PLIC_PRIO79,
RV_PLIC_PRIO80,
RV_PLIC_PRIO81,
+ RV_PLIC_PRIO82,
+ RV_PLIC_PRIO83,
RV_PLIC_IE0_0,
RV_PLIC_IE0_1,
RV_PLIC_IE0_2,
@@ -672,7 +686,7 @@
} rv_plic_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] RV_PLIC_PERMIT [94] = '{
+ parameter logic [3:0] RV_PLIC_PERMIT [96] = '{
4'b 1111, // index[ 0] RV_PLIC_IP_0
4'b 1111, // index[ 1] RV_PLIC_IP_1
4'b 0111, // index[ 2] RV_PLIC_IP_2
@@ -761,12 +775,14 @@
4'b 0001, // index[85] RV_PLIC_PRIO79
4'b 0001, // index[86] RV_PLIC_PRIO80
4'b 0001, // index[87] RV_PLIC_PRIO81
- 4'b 1111, // index[88] RV_PLIC_IE0_0
- 4'b 1111, // index[89] RV_PLIC_IE0_1
- 4'b 0111, // index[90] RV_PLIC_IE0_2
- 4'b 0001, // index[91] RV_PLIC_THRESHOLD0
- 4'b 0001, // index[92] RV_PLIC_CC0
- 4'b 0001 // index[93] RV_PLIC_MSIP0
+ 4'b 0001, // index[88] RV_PLIC_PRIO82
+ 4'b 0001, // index[89] RV_PLIC_PRIO83
+ 4'b 1111, // index[90] RV_PLIC_IE0_0
+ 4'b 1111, // index[91] RV_PLIC_IE0_1
+ 4'b 0111, // index[92] RV_PLIC_IE0_2
+ 4'b 0001, // index[93] RV_PLIC_THRESHOLD0
+ 4'b 0001, // index[94] RV_PLIC_CC0
+ 4'b 0001 // index[95] RV_PLIC_MSIP0
};
endpackage
diff --git a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
index f59d278..e3b8374 100644
--- a/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
+++ b/hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv
@@ -153,6 +153,8 @@
logic ip_2_p_79_qs;
logic ip_2_p_80_qs;
logic ip_2_p_81_qs;
+ logic ip_2_p_82_qs;
+ logic ip_2_p_83_qs;
logic le_0_le_0_qs;
logic le_0_le_0_wd;
logic le_0_le_0_we;
@@ -399,6 +401,12 @@
logic le_2_le_81_qs;
logic le_2_le_81_wd;
logic le_2_le_81_we;
+ logic le_2_le_82_qs;
+ logic le_2_le_82_wd;
+ logic le_2_le_82_we;
+ logic le_2_le_83_qs;
+ logic le_2_le_83_wd;
+ logic le_2_le_83_we;
logic [1:0] prio0_qs;
logic [1:0] prio0_wd;
logic prio0_we;
@@ -645,6 +653,12 @@
logic [1:0] prio81_qs;
logic [1:0] prio81_wd;
logic prio81_we;
+ logic [1:0] prio82_qs;
+ logic [1:0] prio82_wd;
+ logic prio82_we;
+ logic [1:0] prio83_qs;
+ logic [1:0] prio83_wd;
+ logic prio83_we;
logic ie0_0_e_0_qs;
logic ie0_0_e_0_wd;
logic ie0_0_e_0_we;
@@ -891,6 +905,12 @@
logic ie0_2_e_81_qs;
logic ie0_2_e_81_wd;
logic ie0_2_e_81_we;
+ logic ie0_2_e_82_qs;
+ logic ie0_2_e_82_wd;
+ logic ie0_2_e_82_we;
+ logic ie0_2_e_83_qs;
+ logic ie0_2_e_83_wd;
+ logic ie0_2_e_83_we;
logic [1:0] threshold0_qs;
logic [1:0] threshold0_wd;
logic threshold0_we;
@@ -2963,6 +2983,56 @@
);
+ // F[p_82]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_82 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[82].de),
+ .d (hw2reg.ip[82].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_2_p_82_qs)
+ );
+
+
+ // F[p_83]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RO"),
+ .RESVAL (1'h0)
+ ) u_ip_2_p_83 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ .we (1'b0),
+ .wd ('0 ),
+
+ // from internal hardware
+ .de (hw2reg.ip[83].de),
+ .d (hw2reg.ip[83].d ),
+
+ // to internal hardware
+ .qe (),
+ .q (),
+
+ // to register interface (read)
+ .qs (ip_2_p_83_qs)
+ );
+
+
// Subregister 0 of Multireg le
@@ -5106,6 +5176,58 @@
);
+ // F[le_82]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_2_le_82 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_2_le_82_we),
+ .wd (le_2_le_82_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[82].q ),
+
+ // to register interface (read)
+ .qs (le_2_le_82_qs)
+ );
+
+
+ // F[le_83]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_le_2_le_83 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (le_2_le_83_we),
+ .wd (le_2_le_83_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.le[83].q ),
+
+ // to register interface (read)
+ .qs (le_2_le_83_qs)
+ );
+
+
// R[prio0]: V(False)
@@ -7321,6 +7443,60 @@
);
+ // R[prio82]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio82 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio82_we),
+ .wd (prio82_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio82.q ),
+
+ // to register interface (read)
+ .qs (prio82_qs)
+ );
+
+
+ // R[prio83]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_prio83 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (prio83_we),
+ .wd (prio83_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.prio83.q ),
+
+ // to register interface (read)
+ .qs (prio83_qs)
+ );
+
+
// Subregister 0 of Multireg ie0
// R[ie0_0]: V(False)
@@ -9463,6 +9639,58 @@
);
+ // F[e_82]: 18:18
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_82 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_2_e_82_we),
+ .wd (ie0_2_e_82_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[82].q ),
+
+ // to register interface (read)
+ .qs (ie0_2_e_82_qs)
+ );
+
+
+ // F[e_83]: 19:19
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ie0_2_e_83 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ie0_2_e_83_we),
+ .wd (ie0_2_e_83_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ie0[83].q ),
+
+ // to register interface (read)
+ .qs (ie0_2_e_83_qs)
+ );
+
+
// R[threshold0]: V(False)
@@ -9536,7 +9764,7 @@
- logic [93:0] addr_hit;
+ logic [95:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == RV_PLIC_IP_0_OFFSET);
@@ -9627,12 +9855,14 @@
addr_hit[85] = (reg_addr == RV_PLIC_PRIO79_OFFSET);
addr_hit[86] = (reg_addr == RV_PLIC_PRIO80_OFFSET);
addr_hit[87] = (reg_addr == RV_PLIC_PRIO81_OFFSET);
- addr_hit[88] = (reg_addr == RV_PLIC_IE0_0_OFFSET);
- addr_hit[89] = (reg_addr == RV_PLIC_IE0_1_OFFSET);
- addr_hit[90] = (reg_addr == RV_PLIC_IE0_2_OFFSET);
- addr_hit[91] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET);
- addr_hit[92] = (reg_addr == RV_PLIC_CC0_OFFSET);
- addr_hit[93] = (reg_addr == RV_PLIC_MSIP0_OFFSET);
+ addr_hit[88] = (reg_addr == RV_PLIC_PRIO82_OFFSET);
+ addr_hit[89] = (reg_addr == RV_PLIC_PRIO83_OFFSET);
+ addr_hit[90] = (reg_addr == RV_PLIC_IE0_0_OFFSET);
+ addr_hit[91] = (reg_addr == RV_PLIC_IE0_1_OFFSET);
+ addr_hit[92] = (reg_addr == RV_PLIC_IE0_2_OFFSET);
+ addr_hit[93] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET);
+ addr_hit[94] = (reg_addr == RV_PLIC_CC0_OFFSET);
+ addr_hit[95] = (reg_addr == RV_PLIC_MSIP0_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -9734,6 +9964,8 @@
if (addr_hit[91] && reg_we && (RV_PLIC_PERMIT[91] != (RV_PLIC_PERMIT[91] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[92] && reg_we && (RV_PLIC_PERMIT[92] != (RV_PLIC_PERMIT[92] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[93] && reg_we && (RV_PLIC_PERMIT[93] != (RV_PLIC_PERMIT[93] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[94] && reg_we && (RV_PLIC_PERMIT[94] != (RV_PLIC_PERMIT[94] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[95] && reg_we && (RV_PLIC_PERMIT[95] != (RV_PLIC_PERMIT[95] & reg_be))) wr_err = 1'b1 ;
end
@@ -9818,6 +10050,8 @@
+
+
assign le_0_le_0_we = addr_hit[3] & reg_we & ~wr_err;
assign le_0_le_0_wd = reg_wdata[0];
@@ -10064,6 +10298,12 @@
assign le_2_le_81_we = addr_hit[5] & reg_we & ~wr_err;
assign le_2_le_81_wd = reg_wdata[17];
+ assign le_2_le_82_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le_2_le_82_wd = reg_wdata[18];
+
+ assign le_2_le_83_we = addr_hit[5] & reg_we & ~wr_err;
+ assign le_2_le_83_wd = reg_wdata[19];
+
assign prio0_we = addr_hit[6] & reg_we & ~wr_err;
assign prio0_wd = reg_wdata[1:0];
@@ -10310,260 +10550,272 @@
assign prio81_we = addr_hit[87] & reg_we & ~wr_err;
assign prio81_wd = reg_wdata[1:0];
- assign ie0_0_e_0_we = addr_hit[88] & reg_we & ~wr_err;
+ assign prio82_we = addr_hit[88] & reg_we & ~wr_err;
+ assign prio82_wd = reg_wdata[1:0];
+
+ assign prio83_we = addr_hit[89] & reg_we & ~wr_err;
+ assign prio83_wd = reg_wdata[1:0];
+
+ assign ie0_0_e_0_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_0_wd = reg_wdata[0];
- assign ie0_0_e_1_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_1_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_1_wd = reg_wdata[1];
- assign ie0_0_e_2_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_2_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_2_wd = reg_wdata[2];
- assign ie0_0_e_3_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_3_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_3_wd = reg_wdata[3];
- assign ie0_0_e_4_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_4_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_4_wd = reg_wdata[4];
- assign ie0_0_e_5_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_5_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_5_wd = reg_wdata[5];
- assign ie0_0_e_6_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_6_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_6_wd = reg_wdata[6];
- assign ie0_0_e_7_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_7_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_7_wd = reg_wdata[7];
- assign ie0_0_e_8_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_8_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_8_wd = reg_wdata[8];
- assign ie0_0_e_9_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_9_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_9_wd = reg_wdata[9];
- assign ie0_0_e_10_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_10_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_10_wd = reg_wdata[10];
- assign ie0_0_e_11_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_11_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_11_wd = reg_wdata[11];
- assign ie0_0_e_12_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_12_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_12_wd = reg_wdata[12];
- assign ie0_0_e_13_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_13_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_13_wd = reg_wdata[13];
- assign ie0_0_e_14_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_14_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_14_wd = reg_wdata[14];
- assign ie0_0_e_15_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_15_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_15_wd = reg_wdata[15];
- assign ie0_0_e_16_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_16_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_16_wd = reg_wdata[16];
- assign ie0_0_e_17_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_17_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_17_wd = reg_wdata[17];
- assign ie0_0_e_18_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_18_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_18_wd = reg_wdata[18];
- assign ie0_0_e_19_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_19_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_19_wd = reg_wdata[19];
- assign ie0_0_e_20_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_20_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_20_wd = reg_wdata[20];
- assign ie0_0_e_21_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_21_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_21_wd = reg_wdata[21];
- assign ie0_0_e_22_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_22_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_22_wd = reg_wdata[22];
- assign ie0_0_e_23_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_23_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_23_wd = reg_wdata[23];
- assign ie0_0_e_24_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_24_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_24_wd = reg_wdata[24];
- assign ie0_0_e_25_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_25_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_25_wd = reg_wdata[25];
- assign ie0_0_e_26_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_26_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_26_wd = reg_wdata[26];
- assign ie0_0_e_27_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_27_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_27_wd = reg_wdata[27];
- assign ie0_0_e_28_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_28_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_28_wd = reg_wdata[28];
- assign ie0_0_e_29_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_29_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_29_wd = reg_wdata[29];
- assign ie0_0_e_30_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_30_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_30_wd = reg_wdata[30];
- assign ie0_0_e_31_we = addr_hit[88] & reg_we & ~wr_err;
+ assign ie0_0_e_31_we = addr_hit[90] & reg_we & ~wr_err;
assign ie0_0_e_31_wd = reg_wdata[31];
- assign ie0_1_e_32_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_32_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_32_wd = reg_wdata[0];
- assign ie0_1_e_33_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_33_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_33_wd = reg_wdata[1];
- assign ie0_1_e_34_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_34_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_34_wd = reg_wdata[2];
- assign ie0_1_e_35_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_35_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_35_wd = reg_wdata[3];
- assign ie0_1_e_36_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_36_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_36_wd = reg_wdata[4];
- assign ie0_1_e_37_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_37_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_37_wd = reg_wdata[5];
- assign ie0_1_e_38_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_38_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_38_wd = reg_wdata[6];
- assign ie0_1_e_39_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_39_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_39_wd = reg_wdata[7];
- assign ie0_1_e_40_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_40_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_40_wd = reg_wdata[8];
- assign ie0_1_e_41_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_41_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_41_wd = reg_wdata[9];
- assign ie0_1_e_42_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_42_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_42_wd = reg_wdata[10];
- assign ie0_1_e_43_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_43_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_43_wd = reg_wdata[11];
- assign ie0_1_e_44_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_44_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_44_wd = reg_wdata[12];
- assign ie0_1_e_45_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_45_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_45_wd = reg_wdata[13];
- assign ie0_1_e_46_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_46_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_46_wd = reg_wdata[14];
- assign ie0_1_e_47_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_47_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_47_wd = reg_wdata[15];
- assign ie0_1_e_48_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_48_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_48_wd = reg_wdata[16];
- assign ie0_1_e_49_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_49_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_49_wd = reg_wdata[17];
- assign ie0_1_e_50_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_50_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_50_wd = reg_wdata[18];
- assign ie0_1_e_51_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_51_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_51_wd = reg_wdata[19];
- assign ie0_1_e_52_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_52_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_52_wd = reg_wdata[20];
- assign ie0_1_e_53_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_53_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_53_wd = reg_wdata[21];
- assign ie0_1_e_54_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_54_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_54_wd = reg_wdata[22];
- assign ie0_1_e_55_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_55_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_55_wd = reg_wdata[23];
- assign ie0_1_e_56_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_56_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_56_wd = reg_wdata[24];
- assign ie0_1_e_57_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_57_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_57_wd = reg_wdata[25];
- assign ie0_1_e_58_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_58_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_58_wd = reg_wdata[26];
- assign ie0_1_e_59_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_59_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_59_wd = reg_wdata[27];
- assign ie0_1_e_60_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_60_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_60_wd = reg_wdata[28];
- assign ie0_1_e_61_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_61_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_61_wd = reg_wdata[29];
- assign ie0_1_e_62_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_62_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_62_wd = reg_wdata[30];
- assign ie0_1_e_63_we = addr_hit[89] & reg_we & ~wr_err;
+ assign ie0_1_e_63_we = addr_hit[91] & reg_we & ~wr_err;
assign ie0_1_e_63_wd = reg_wdata[31];
- assign ie0_2_e_64_we = addr_hit[90] & reg_we & ~wr_err;
+ assign ie0_2_e_64_we = addr_hit[92] & reg_we & ~wr_err;
assign ie0_2_e_64_wd = reg_wdata[0];
- assign ie0_2_e_65_we = addr_hit[90] & reg_we & ~wr_err;
+ assign ie0_2_e_65_we = addr_hit[92] & reg_we & ~wr_err;
assign ie0_2_e_65_wd = reg_wdata[1];
- assign ie0_2_e_66_we = addr_hit[90] & reg_we & ~wr_err;
+ assign ie0_2_e_66_we = addr_hit[92] & reg_we & ~wr_err;
assign ie0_2_e_66_wd = reg_wdata[2];
- assign ie0_2_e_67_we = addr_hit[90] & reg_we & ~wr_err;
+ assign ie0_2_e_67_we = addr_hit[92] & reg_we & ~wr_err;
assign ie0_2_e_67_wd = reg_wdata[3];
- assign ie0_2_e_68_we = addr_hit[90] & reg_we & ~wr_err;
+ assign ie0_2_e_68_we = addr_hit[92] & reg_we & ~wr_err;
assign ie0_2_e_68_wd = reg_wdata[4];
- assign ie0_2_e_69_we = addr_hit[90] & reg_we & ~wr_err;
+ assign ie0_2_e_69_we = addr_hit[92] & reg_we & ~wr_err;
assign ie0_2_e_69_wd = reg_wdata[5];
- assign ie0_2_e_70_we = addr_hit[90] & reg_we & ~wr_err;
+ assign ie0_2_e_70_we = addr_hit[92] & reg_we & ~wr_err;
assign ie0_2_e_70_wd = reg_wdata[6];
- assign ie0_2_e_71_we = addr_hit[90] & reg_we & ~wr_err;
+ assign ie0_2_e_71_we = addr_hit[92] & reg_we & ~wr_err;
assign ie0_2_e_71_wd = reg_wdata[7];
- assign ie0_2_e_72_we = addr_hit[90] & reg_we & ~wr_err;
+ assign ie0_2_e_72_we = addr_hit[92] & reg_we & ~wr_err;
assign ie0_2_e_72_wd = reg_wdata[8];
- assign ie0_2_e_73_we = addr_hit[90] & reg_we & ~wr_err;
+ assign ie0_2_e_73_we = addr_hit[92] & reg_we & ~wr_err;
assign ie0_2_e_73_wd = reg_wdata[9];
- assign ie0_2_e_74_we = addr_hit[90] & reg_we & ~wr_err;
+ assign ie0_2_e_74_we = addr_hit[92] & reg_we & ~wr_err;
assign ie0_2_e_74_wd = reg_wdata[10];
- assign ie0_2_e_75_we = addr_hit[90] & reg_we & ~wr_err;
+ assign ie0_2_e_75_we = addr_hit[92] & reg_we & ~wr_err;
assign ie0_2_e_75_wd = reg_wdata[11];
- assign ie0_2_e_76_we = addr_hit[90] & reg_we & ~wr_err;
+ assign ie0_2_e_76_we = addr_hit[92] & reg_we & ~wr_err;
assign ie0_2_e_76_wd = reg_wdata[12];
- assign ie0_2_e_77_we = addr_hit[90] & reg_we & ~wr_err;
+ assign ie0_2_e_77_we = addr_hit[92] & reg_we & ~wr_err;
assign ie0_2_e_77_wd = reg_wdata[13];
- assign ie0_2_e_78_we = addr_hit[90] & reg_we & ~wr_err;
+ assign ie0_2_e_78_we = addr_hit[92] & reg_we & ~wr_err;
assign ie0_2_e_78_wd = reg_wdata[14];
- assign ie0_2_e_79_we = addr_hit[90] & reg_we & ~wr_err;
+ assign ie0_2_e_79_we = addr_hit[92] & reg_we & ~wr_err;
assign ie0_2_e_79_wd = reg_wdata[15];
- assign ie0_2_e_80_we = addr_hit[90] & reg_we & ~wr_err;
+ assign ie0_2_e_80_we = addr_hit[92] & reg_we & ~wr_err;
assign ie0_2_e_80_wd = reg_wdata[16];
- assign ie0_2_e_81_we = addr_hit[90] & reg_we & ~wr_err;
+ assign ie0_2_e_81_we = addr_hit[92] & reg_we & ~wr_err;
assign ie0_2_e_81_wd = reg_wdata[17];
- assign threshold0_we = addr_hit[91] & reg_we & ~wr_err;
+ assign ie0_2_e_82_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_2_e_82_wd = reg_wdata[18];
+
+ assign ie0_2_e_83_we = addr_hit[92] & reg_we & ~wr_err;
+ assign ie0_2_e_83_wd = reg_wdata[19];
+
+ assign threshold0_we = addr_hit[93] & reg_we & ~wr_err;
assign threshold0_wd = reg_wdata[1:0];
- assign cc0_we = addr_hit[92] & reg_we & ~wr_err;
+ assign cc0_we = addr_hit[94] & reg_we & ~wr_err;
assign cc0_wd = reg_wdata[6:0];
- assign cc0_re = addr_hit[92] && reg_re;
+ assign cc0_re = addr_hit[94] && reg_re;
- assign msip0_we = addr_hit[93] & reg_we & ~wr_err;
+ assign msip0_we = addr_hit[95] & reg_we & ~wr_err;
assign msip0_wd = reg_wdata[0];
// Read data return
@@ -10659,6 +10911,8 @@
reg_rdata_next[15] = ip_2_p_79_qs;
reg_rdata_next[16] = ip_2_p_80_qs;
reg_rdata_next[17] = ip_2_p_81_qs;
+ reg_rdata_next[18] = ip_2_p_82_qs;
+ reg_rdata_next[19] = ip_2_p_83_qs;
end
addr_hit[3]: begin
@@ -10750,6 +11004,8 @@
reg_rdata_next[15] = le_2_le_79_qs;
reg_rdata_next[16] = le_2_le_80_qs;
reg_rdata_next[17] = le_2_le_81_qs;
+ reg_rdata_next[18] = le_2_le_82_qs;
+ reg_rdata_next[19] = le_2_le_83_qs;
end
addr_hit[6]: begin
@@ -11081,6 +11337,14 @@
end
addr_hit[88]: begin
+ reg_rdata_next[1:0] = prio82_qs;
+ end
+
+ addr_hit[89]: begin
+ reg_rdata_next[1:0] = prio83_qs;
+ end
+
+ addr_hit[90]: begin
reg_rdata_next[0] = ie0_0_e_0_qs;
reg_rdata_next[1] = ie0_0_e_1_qs;
reg_rdata_next[2] = ie0_0_e_2_qs;
@@ -11115,7 +11379,7 @@
reg_rdata_next[31] = ie0_0_e_31_qs;
end
- addr_hit[89]: begin
+ addr_hit[91]: begin
reg_rdata_next[0] = ie0_1_e_32_qs;
reg_rdata_next[1] = ie0_1_e_33_qs;
reg_rdata_next[2] = ie0_1_e_34_qs;
@@ -11150,7 +11414,7 @@
reg_rdata_next[31] = ie0_1_e_63_qs;
end
- addr_hit[90]: begin
+ addr_hit[92]: begin
reg_rdata_next[0] = ie0_2_e_64_qs;
reg_rdata_next[1] = ie0_2_e_65_qs;
reg_rdata_next[2] = ie0_2_e_66_qs;
@@ -11169,17 +11433,19 @@
reg_rdata_next[15] = ie0_2_e_79_qs;
reg_rdata_next[16] = ie0_2_e_80_qs;
reg_rdata_next[17] = ie0_2_e_81_qs;
- end
-
- addr_hit[91]: begin
- reg_rdata_next[1:0] = threshold0_qs;
- end
-
- addr_hit[92]: begin
- reg_rdata_next[6:0] = cc0_qs;
+ reg_rdata_next[18] = ie0_2_e_82_qs;
+ reg_rdata_next[19] = ie0_2_e_83_qs;
end
addr_hit[93]: begin
+ reg_rdata_next[1:0] = threshold0_qs;
+ end
+
+ addr_hit[94]: begin
+ reg_rdata_next[6:0] = cc0_qs;
+ end
+
+ addr_hit[95]: begin
reg_rdata_next[0] = msip0_qs;
end
diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
index 7afbb82..3a4156f 100644
--- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
+++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
@@ -51,6 +51,7 @@
alert_handler
nmi_gen
otbn
+ keymgr
]
dm_sba:
[
@@ -373,6 +374,24 @@
stub: false
pipeline: "true"
}
+ {
+ name: keymgr
+ type: device
+ clock: clk_main_i
+ reset: rst_main_ni
+ pipeline_byp: "false"
+ inst_type: keymgr
+ addr_range:
+ [
+ {
+ base_addr: 0x401a0000
+ size_byte: 0x1000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline: "true"
+ }
]
clock: clk_main_i
type: xbar
diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson
index 0fa41d3..02c0331 100644
--- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson
+++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson
@@ -115,5 +115,11 @@
act: "req"
package: "tlul_pkg"
}
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_keymgr"
+ act: "req"
+ package: "tlul_pkg"
+ }
]
}
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv
index 0429508..e12f473 100644
--- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv
+++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv
@@ -36,3 +36,4 @@
`CONNECT_TL_DEVICE_IF(alert_handler, dut, clk_main_i, rst_n)
`CONNECT_TL_DEVICE_IF(nmi_gen, dut, clk_main_i, rst_n)
`CONNECT_TL_DEVICE_IF(otbn, dut, clk_main_i, rst_n)
+`CONNECT_TL_DEVICE_IF(keymgr, dut, clk_main_i, rst_n)
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
index 9c8604c..cba37ef 100644
--- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
+++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
@@ -53,6 +53,9 @@
}},
'{"otbn", '{
'{32'h50000000, 32'h503fffff}
+ }},
+ '{"keymgr", '{
+ '{32'h401a0000, 32'h401a0fff}
}}};
// List of Xbar hosts
@@ -77,7 +80,8 @@
"padctrl",
"alert_handler",
"nmi_gen",
- "otbn"}}
+ "otbn",
+ "keymgr"}}
,
'{"dm_sba", 2, '{
"rom",
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv
index 10e0c6c..00c05a3 100644
--- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv
+++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv
@@ -110,5 +110,11 @@
.h2d (tl_otbn_o),
.d2h (tl_otbn_i)
);
+ bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_keymgr (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .h2d (tl_keymgr_o),
+ .d2h (tl_keymgr_i)
+ );
endmodule
diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
index a777bf3..f9483a6 100644
--- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
+++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
@@ -27,6 +27,7 @@
localparam logic [31:0] ADDR_SPACE_ALERT_HANDLER = 32'h 40130000;
localparam logic [31:0] ADDR_SPACE_NMI_GEN = 32'h 40140000;
localparam logic [31:0] ADDR_SPACE_OTBN = 32'h 50000000;
+ localparam logic [31:0] ADDR_SPACE_KEYMGR = 32'h 401a0000;
localparam logic [31:0] ADDR_MASK_ROM = 32'h 00003fff;
localparam logic [31:0] ADDR_MASK_DEBUG_MEM = 32'h 00000fff;
@@ -49,9 +50,10 @@
localparam logic [31:0] ADDR_MASK_ALERT_HANDLER = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_NMI_GEN = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_OTBN = 32'h 003fffff;
+ localparam logic [31:0] ADDR_MASK_KEYMGR = 32'h 00000fff;
localparam int N_HOST = 3;
- localparam int N_DEVICE = 14;
+ localparam int N_DEVICE = 15;
typedef enum int {
TlRom = 0,
@@ -67,7 +69,8 @@
TlPadctrl = 10,
TlAlertHandler = 11,
TlNmiGen = 12,
- TlOtbn = 13
+ TlOtbn = 13,
+ TlKeymgr = 14
} tl_device_e;
typedef enum int {
diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv
index 0e8c03f..b697c6d 100644
--- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv
+++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv
@@ -7,74 +7,75 @@
//
// Interconnect
// corei
-// -> s1n_17
-// -> sm1_18
-// -> rom
+// -> s1n_18
// -> sm1_19
-// -> debug_mem
+// -> rom
// -> sm1_20
-// -> ram_main
+// -> debug_mem
// -> sm1_21
+// -> ram_main
+// -> sm1_22
// -> eflash
// cored
-// -> s1n_22
-// -> sm1_18
-// -> rom
+// -> s1n_23
// -> sm1_19
-// -> debug_mem
-// -> sm1_20
-// -> ram_main
-// -> sm1_21
-// -> eflash
-// -> sm1_24
-// -> asf_23
-// -> peri
-// -> sm1_25
-// -> flash_ctrl
-// -> sm1_26
-// -> aes
-// -> sm1_27
-// -> hmac
-// -> sm1_28
-// -> rv_plic
-// -> sm1_29
-// -> pinmux
-// -> sm1_30
-// -> padctrl
-// -> sm1_31
-// -> alert_handler
-// -> sm1_32
-// -> nmi_gen
-// -> sm1_33
-// -> otbn
-// dm_sba
-// -> s1n_34
-// -> sm1_18
// -> rom
// -> sm1_20
-// -> ram_main
+// -> debug_mem
// -> sm1_21
+// -> ram_main
+// -> sm1_22
// -> eflash
-// -> sm1_24
-// -> asf_23
-// -> peri
// -> sm1_25
-// -> flash_ctrl
+// -> asf_24
+// -> peri
// -> sm1_26
-// -> aes
+// -> flash_ctrl
// -> sm1_27
-// -> hmac
+// -> aes
// -> sm1_28
-// -> rv_plic
+// -> hmac
// -> sm1_29
-// -> pinmux
+// -> rv_plic
// -> sm1_30
-// -> padctrl
+// -> pinmux
// -> sm1_31
-// -> alert_handler
+// -> padctrl
// -> sm1_32
-// -> nmi_gen
+// -> alert_handler
// -> sm1_33
+// -> nmi_gen
+// -> sm1_34
+// -> otbn
+// -> keymgr
+// dm_sba
+// -> s1n_35
+// -> sm1_19
+// -> rom
+// -> sm1_21
+// -> ram_main
+// -> sm1_22
+// -> eflash
+// -> sm1_25
+// -> asf_24
+// -> peri
+// -> sm1_26
+// -> flash_ctrl
+// -> sm1_27
+// -> aes
+// -> sm1_28
+// -> hmac
+// -> sm1_29
+// -> rv_plic
+// -> sm1_30
+// -> pinmux
+// -> sm1_31
+// -> padctrl
+// -> sm1_32
+// -> alert_handler
+// -> sm1_33
+// -> nmi_gen
+// -> sm1_34
// -> otbn
module xbar_main (
@@ -120,6 +121,8 @@
input tlul_pkg::tl_d2h_t tl_nmi_gen_i,
output tlul_pkg::tl_h2d_t tl_otbn_o,
input tlul_pkg::tl_d2h_t tl_otbn_i,
+ output tlul_pkg::tl_h2d_t tl_keymgr_o,
+ input tlul_pkg::tl_d2h_t tl_keymgr_i,
input scanmode_i
);
@@ -132,33 +135,26 @@
logic unused_scanmode;
assign unused_scanmode = scanmode_i;
- tl_h2d_t tl_s1n_17_us_h2d ;
- tl_d2h_t tl_s1n_17_us_d2h ;
+ tl_h2d_t tl_s1n_18_us_h2d ;
+ tl_d2h_t tl_s1n_18_us_d2h ;
- tl_h2d_t tl_s1n_17_ds_h2d [4];
- tl_d2h_t tl_s1n_17_ds_d2h [4];
+ tl_h2d_t tl_s1n_18_ds_h2d [4];
+ tl_d2h_t tl_s1n_18_ds_d2h [4];
// Create steering signal
- logic [2:0] dev_sel_s1n_17;
+ logic [2:0] dev_sel_s1n_18;
- tl_h2d_t tl_sm1_18_us_h2d [3];
- tl_d2h_t tl_sm1_18_us_d2h [3];
-
- tl_h2d_t tl_sm1_18_ds_h2d ;
- tl_d2h_t tl_sm1_18_ds_d2h ;
-
-
- tl_h2d_t tl_sm1_19_us_h2d [2];
- tl_d2h_t tl_sm1_19_us_d2h [2];
+ tl_h2d_t tl_sm1_19_us_h2d [3];
+ tl_d2h_t tl_sm1_19_us_d2h [3];
tl_h2d_t tl_sm1_19_ds_h2d ;
tl_d2h_t tl_sm1_19_ds_d2h ;
- tl_h2d_t tl_sm1_20_us_h2d [3];
- tl_d2h_t tl_sm1_20_us_d2h [3];
+ tl_h2d_t tl_sm1_20_us_h2d [2];
+ tl_d2h_t tl_sm1_20_us_d2h [2];
tl_h2d_t tl_sm1_20_ds_h2d ;
tl_d2h_t tl_sm1_20_ds_d2h ;
@@ -170,27 +166,27 @@
tl_h2d_t tl_sm1_21_ds_h2d ;
tl_d2h_t tl_sm1_21_ds_d2h ;
- tl_h2d_t tl_s1n_22_us_h2d ;
- tl_d2h_t tl_s1n_22_us_d2h ;
+
+ tl_h2d_t tl_sm1_22_us_h2d [3];
+ tl_d2h_t tl_sm1_22_us_d2h [3];
+
+ tl_h2d_t tl_sm1_22_ds_h2d ;
+ tl_d2h_t tl_sm1_22_ds_d2h ;
+
+ tl_h2d_t tl_s1n_23_us_h2d ;
+ tl_d2h_t tl_s1n_23_us_d2h ;
- tl_h2d_t tl_s1n_22_ds_h2d [14];
- tl_d2h_t tl_s1n_22_ds_d2h [14];
+ tl_h2d_t tl_s1n_23_ds_h2d [15];
+ tl_d2h_t tl_s1n_23_ds_d2h [15];
// Create steering signal
- logic [3:0] dev_sel_s1n_22;
+ logic [3:0] dev_sel_s1n_23;
- tl_h2d_t tl_asf_23_us_h2d ;
- tl_d2h_t tl_asf_23_us_d2h ;
- tl_h2d_t tl_asf_23_ds_h2d ;
- tl_d2h_t tl_asf_23_ds_d2h ;
-
-
- tl_h2d_t tl_sm1_24_us_h2d [2];
- tl_d2h_t tl_sm1_24_us_d2h [2];
-
- tl_h2d_t tl_sm1_24_ds_h2d ;
- tl_d2h_t tl_sm1_24_ds_d2h ;
+ tl_h2d_t tl_asf_24_us_h2d ;
+ tl_d2h_t tl_asf_24_us_d2h ;
+ tl_h2d_t tl_asf_24_ds_h2d ;
+ tl_d2h_t tl_asf_24_ds_d2h ;
tl_h2d_t tl_sm1_25_us_h2d [2];
@@ -255,294 +251,307 @@
tl_h2d_t tl_sm1_33_ds_h2d ;
tl_d2h_t tl_sm1_33_ds_d2h ;
- tl_h2d_t tl_s1n_34_us_h2d ;
- tl_d2h_t tl_s1n_34_us_d2h ;
+
+ tl_h2d_t tl_sm1_34_us_h2d [2];
+ tl_d2h_t tl_sm1_34_us_d2h [2];
+
+ tl_h2d_t tl_sm1_34_ds_h2d ;
+ tl_d2h_t tl_sm1_34_ds_d2h ;
+
+ tl_h2d_t tl_s1n_35_us_h2d ;
+ tl_d2h_t tl_s1n_35_us_d2h ;
- tl_h2d_t tl_s1n_34_ds_h2d [13];
- tl_d2h_t tl_s1n_34_ds_d2h [13];
+ tl_h2d_t tl_s1n_35_ds_h2d [13];
+ tl_d2h_t tl_s1n_35_ds_d2h [13];
// Create steering signal
- logic [3:0] dev_sel_s1n_34;
+ logic [3:0] dev_sel_s1n_35;
- assign tl_sm1_18_us_h2d[0] = tl_s1n_17_ds_h2d[0];
- assign tl_s1n_17_ds_d2h[0] = tl_sm1_18_us_d2h[0];
+ assign tl_sm1_19_us_h2d[0] = tl_s1n_18_ds_h2d[0];
+ assign tl_s1n_18_ds_d2h[0] = tl_sm1_19_us_d2h[0];
- assign tl_sm1_19_us_h2d[0] = tl_s1n_17_ds_h2d[1];
- assign tl_s1n_17_ds_d2h[1] = tl_sm1_19_us_d2h[0];
+ assign tl_sm1_20_us_h2d[0] = tl_s1n_18_ds_h2d[1];
+ assign tl_s1n_18_ds_d2h[1] = tl_sm1_20_us_d2h[0];
- assign tl_sm1_20_us_h2d[0] = tl_s1n_17_ds_h2d[2];
- assign tl_s1n_17_ds_d2h[2] = tl_sm1_20_us_d2h[0];
+ assign tl_sm1_21_us_h2d[0] = tl_s1n_18_ds_h2d[2];
+ assign tl_s1n_18_ds_d2h[2] = tl_sm1_21_us_d2h[0];
- assign tl_sm1_21_us_h2d[0] = tl_s1n_17_ds_h2d[3];
- assign tl_s1n_17_ds_d2h[3] = tl_sm1_21_us_d2h[0];
+ assign tl_sm1_22_us_h2d[0] = tl_s1n_18_ds_h2d[3];
+ assign tl_s1n_18_ds_d2h[3] = tl_sm1_22_us_d2h[0];
- assign tl_sm1_18_us_h2d[1] = tl_s1n_22_ds_h2d[0];
- assign tl_s1n_22_ds_d2h[0] = tl_sm1_18_us_d2h[1];
+ assign tl_sm1_19_us_h2d[1] = tl_s1n_23_ds_h2d[0];
+ assign tl_s1n_23_ds_d2h[0] = tl_sm1_19_us_d2h[1];
- assign tl_sm1_19_us_h2d[1] = tl_s1n_22_ds_h2d[1];
- assign tl_s1n_22_ds_d2h[1] = tl_sm1_19_us_d2h[1];
+ assign tl_sm1_20_us_h2d[1] = tl_s1n_23_ds_h2d[1];
+ assign tl_s1n_23_ds_d2h[1] = tl_sm1_20_us_d2h[1];
- assign tl_sm1_20_us_h2d[1] = tl_s1n_22_ds_h2d[2];
- assign tl_s1n_22_ds_d2h[2] = tl_sm1_20_us_d2h[1];
+ assign tl_sm1_21_us_h2d[1] = tl_s1n_23_ds_h2d[2];
+ assign tl_s1n_23_ds_d2h[2] = tl_sm1_21_us_d2h[1];
- assign tl_sm1_21_us_h2d[1] = tl_s1n_22_ds_h2d[3];
- assign tl_s1n_22_ds_d2h[3] = tl_sm1_21_us_d2h[1];
+ assign tl_sm1_22_us_h2d[1] = tl_s1n_23_ds_h2d[3];
+ assign tl_s1n_23_ds_d2h[3] = tl_sm1_22_us_d2h[1];
- assign tl_sm1_24_us_h2d[0] = tl_s1n_22_ds_h2d[4];
- assign tl_s1n_22_ds_d2h[4] = tl_sm1_24_us_d2h[0];
+ assign tl_sm1_25_us_h2d[0] = tl_s1n_23_ds_h2d[4];
+ assign tl_s1n_23_ds_d2h[4] = tl_sm1_25_us_d2h[0];
- assign tl_sm1_25_us_h2d[0] = tl_s1n_22_ds_h2d[5];
- assign tl_s1n_22_ds_d2h[5] = tl_sm1_25_us_d2h[0];
+ assign tl_sm1_26_us_h2d[0] = tl_s1n_23_ds_h2d[5];
+ assign tl_s1n_23_ds_d2h[5] = tl_sm1_26_us_d2h[0];
- assign tl_sm1_26_us_h2d[0] = tl_s1n_22_ds_h2d[6];
- assign tl_s1n_22_ds_d2h[6] = tl_sm1_26_us_d2h[0];
+ assign tl_sm1_27_us_h2d[0] = tl_s1n_23_ds_h2d[6];
+ assign tl_s1n_23_ds_d2h[6] = tl_sm1_27_us_d2h[0];
- assign tl_sm1_27_us_h2d[0] = tl_s1n_22_ds_h2d[7];
- assign tl_s1n_22_ds_d2h[7] = tl_sm1_27_us_d2h[0];
+ assign tl_sm1_28_us_h2d[0] = tl_s1n_23_ds_h2d[7];
+ assign tl_s1n_23_ds_d2h[7] = tl_sm1_28_us_d2h[0];
- assign tl_sm1_28_us_h2d[0] = tl_s1n_22_ds_h2d[8];
- assign tl_s1n_22_ds_d2h[8] = tl_sm1_28_us_d2h[0];
+ assign tl_sm1_29_us_h2d[0] = tl_s1n_23_ds_h2d[8];
+ assign tl_s1n_23_ds_d2h[8] = tl_sm1_29_us_d2h[0];
- assign tl_sm1_29_us_h2d[0] = tl_s1n_22_ds_h2d[9];
- assign tl_s1n_22_ds_d2h[9] = tl_sm1_29_us_d2h[0];
+ assign tl_sm1_30_us_h2d[0] = tl_s1n_23_ds_h2d[9];
+ assign tl_s1n_23_ds_d2h[9] = tl_sm1_30_us_d2h[0];
- assign tl_sm1_30_us_h2d[0] = tl_s1n_22_ds_h2d[10];
- assign tl_s1n_22_ds_d2h[10] = tl_sm1_30_us_d2h[0];
+ assign tl_sm1_31_us_h2d[0] = tl_s1n_23_ds_h2d[10];
+ assign tl_s1n_23_ds_d2h[10] = tl_sm1_31_us_d2h[0];
- assign tl_sm1_31_us_h2d[0] = tl_s1n_22_ds_h2d[11];
- assign tl_s1n_22_ds_d2h[11] = tl_sm1_31_us_d2h[0];
+ assign tl_sm1_32_us_h2d[0] = tl_s1n_23_ds_h2d[11];
+ assign tl_s1n_23_ds_d2h[11] = tl_sm1_32_us_d2h[0];
- assign tl_sm1_32_us_h2d[0] = tl_s1n_22_ds_h2d[12];
- assign tl_s1n_22_ds_d2h[12] = tl_sm1_32_us_d2h[0];
+ assign tl_sm1_33_us_h2d[0] = tl_s1n_23_ds_h2d[12];
+ assign tl_s1n_23_ds_d2h[12] = tl_sm1_33_us_d2h[0];
- assign tl_sm1_33_us_h2d[0] = tl_s1n_22_ds_h2d[13];
- assign tl_s1n_22_ds_d2h[13] = tl_sm1_33_us_d2h[0];
+ assign tl_sm1_34_us_h2d[0] = tl_s1n_23_ds_h2d[13];
+ assign tl_s1n_23_ds_d2h[13] = tl_sm1_34_us_d2h[0];
- assign tl_sm1_18_us_h2d[2] = tl_s1n_34_ds_h2d[0];
- assign tl_s1n_34_ds_d2h[0] = tl_sm1_18_us_d2h[2];
+ assign tl_keymgr_o = tl_s1n_23_ds_h2d[14];
+ assign tl_s1n_23_ds_d2h[14] = tl_keymgr_i;
- assign tl_sm1_20_us_h2d[2] = tl_s1n_34_ds_h2d[1];
- assign tl_s1n_34_ds_d2h[1] = tl_sm1_20_us_d2h[2];
+ assign tl_sm1_19_us_h2d[2] = tl_s1n_35_ds_h2d[0];
+ assign tl_s1n_35_ds_d2h[0] = tl_sm1_19_us_d2h[2];
- assign tl_sm1_21_us_h2d[2] = tl_s1n_34_ds_h2d[2];
- assign tl_s1n_34_ds_d2h[2] = tl_sm1_21_us_d2h[2];
+ assign tl_sm1_21_us_h2d[2] = tl_s1n_35_ds_h2d[1];
+ assign tl_s1n_35_ds_d2h[1] = tl_sm1_21_us_d2h[2];
- assign tl_sm1_24_us_h2d[1] = tl_s1n_34_ds_h2d[3];
- assign tl_s1n_34_ds_d2h[3] = tl_sm1_24_us_d2h[1];
+ assign tl_sm1_22_us_h2d[2] = tl_s1n_35_ds_h2d[2];
+ assign tl_s1n_35_ds_d2h[2] = tl_sm1_22_us_d2h[2];
- assign tl_sm1_25_us_h2d[1] = tl_s1n_34_ds_h2d[4];
- assign tl_s1n_34_ds_d2h[4] = tl_sm1_25_us_d2h[1];
+ assign tl_sm1_25_us_h2d[1] = tl_s1n_35_ds_h2d[3];
+ assign tl_s1n_35_ds_d2h[3] = tl_sm1_25_us_d2h[1];
- assign tl_sm1_26_us_h2d[1] = tl_s1n_34_ds_h2d[5];
- assign tl_s1n_34_ds_d2h[5] = tl_sm1_26_us_d2h[1];
+ assign tl_sm1_26_us_h2d[1] = tl_s1n_35_ds_h2d[4];
+ assign tl_s1n_35_ds_d2h[4] = tl_sm1_26_us_d2h[1];
- assign tl_sm1_27_us_h2d[1] = tl_s1n_34_ds_h2d[6];
- assign tl_s1n_34_ds_d2h[6] = tl_sm1_27_us_d2h[1];
+ assign tl_sm1_27_us_h2d[1] = tl_s1n_35_ds_h2d[5];
+ assign tl_s1n_35_ds_d2h[5] = tl_sm1_27_us_d2h[1];
- assign tl_sm1_28_us_h2d[1] = tl_s1n_34_ds_h2d[7];
- assign tl_s1n_34_ds_d2h[7] = tl_sm1_28_us_d2h[1];
+ assign tl_sm1_28_us_h2d[1] = tl_s1n_35_ds_h2d[6];
+ assign tl_s1n_35_ds_d2h[6] = tl_sm1_28_us_d2h[1];
- assign tl_sm1_29_us_h2d[1] = tl_s1n_34_ds_h2d[8];
- assign tl_s1n_34_ds_d2h[8] = tl_sm1_29_us_d2h[1];
+ assign tl_sm1_29_us_h2d[1] = tl_s1n_35_ds_h2d[7];
+ assign tl_s1n_35_ds_d2h[7] = tl_sm1_29_us_d2h[1];
- assign tl_sm1_30_us_h2d[1] = tl_s1n_34_ds_h2d[9];
- assign tl_s1n_34_ds_d2h[9] = tl_sm1_30_us_d2h[1];
+ assign tl_sm1_30_us_h2d[1] = tl_s1n_35_ds_h2d[8];
+ assign tl_s1n_35_ds_d2h[8] = tl_sm1_30_us_d2h[1];
- assign tl_sm1_31_us_h2d[1] = tl_s1n_34_ds_h2d[10];
- assign tl_s1n_34_ds_d2h[10] = tl_sm1_31_us_d2h[1];
+ assign tl_sm1_31_us_h2d[1] = tl_s1n_35_ds_h2d[9];
+ assign tl_s1n_35_ds_d2h[9] = tl_sm1_31_us_d2h[1];
- assign tl_sm1_32_us_h2d[1] = tl_s1n_34_ds_h2d[11];
- assign tl_s1n_34_ds_d2h[11] = tl_sm1_32_us_d2h[1];
+ assign tl_sm1_32_us_h2d[1] = tl_s1n_35_ds_h2d[10];
+ assign tl_s1n_35_ds_d2h[10] = tl_sm1_32_us_d2h[1];
- assign tl_sm1_33_us_h2d[1] = tl_s1n_34_ds_h2d[12];
- assign tl_s1n_34_ds_d2h[12] = tl_sm1_33_us_d2h[1];
+ assign tl_sm1_33_us_h2d[1] = tl_s1n_35_ds_h2d[11];
+ assign tl_s1n_35_ds_d2h[11] = tl_sm1_33_us_d2h[1];
- assign tl_s1n_17_us_h2d = tl_corei_i;
- assign tl_corei_o = tl_s1n_17_us_d2h;
+ assign tl_sm1_34_us_h2d[1] = tl_s1n_35_ds_h2d[12];
+ assign tl_s1n_35_ds_d2h[12] = tl_sm1_34_us_d2h[1];
- assign tl_rom_o = tl_sm1_18_ds_h2d;
- assign tl_sm1_18_ds_d2h = tl_rom_i;
+ assign tl_s1n_18_us_h2d = tl_corei_i;
+ assign tl_corei_o = tl_s1n_18_us_d2h;
- assign tl_debug_mem_o = tl_sm1_19_ds_h2d;
- assign tl_sm1_19_ds_d2h = tl_debug_mem_i;
+ assign tl_rom_o = tl_sm1_19_ds_h2d;
+ assign tl_sm1_19_ds_d2h = tl_rom_i;
- assign tl_ram_main_o = tl_sm1_20_ds_h2d;
- assign tl_sm1_20_ds_d2h = tl_ram_main_i;
+ assign tl_debug_mem_o = tl_sm1_20_ds_h2d;
+ assign tl_sm1_20_ds_d2h = tl_debug_mem_i;
- assign tl_eflash_o = tl_sm1_21_ds_h2d;
- assign tl_sm1_21_ds_d2h = tl_eflash_i;
+ assign tl_ram_main_o = tl_sm1_21_ds_h2d;
+ assign tl_sm1_21_ds_d2h = tl_ram_main_i;
- assign tl_s1n_22_us_h2d = tl_cored_i;
- assign tl_cored_o = tl_s1n_22_us_d2h;
+ assign tl_eflash_o = tl_sm1_22_ds_h2d;
+ assign tl_sm1_22_ds_d2h = tl_eflash_i;
- assign tl_peri_o = tl_asf_23_ds_h2d;
- assign tl_asf_23_ds_d2h = tl_peri_i;
+ assign tl_s1n_23_us_h2d = tl_cored_i;
+ assign tl_cored_o = tl_s1n_23_us_d2h;
- assign tl_asf_23_us_h2d = tl_sm1_24_ds_h2d;
- assign tl_sm1_24_ds_d2h = tl_asf_23_us_d2h;
+ assign tl_peri_o = tl_asf_24_ds_h2d;
+ assign tl_asf_24_ds_d2h = tl_peri_i;
- assign tl_flash_ctrl_o = tl_sm1_25_ds_h2d;
- assign tl_sm1_25_ds_d2h = tl_flash_ctrl_i;
+ assign tl_asf_24_us_h2d = tl_sm1_25_ds_h2d;
+ assign tl_sm1_25_ds_d2h = tl_asf_24_us_d2h;
- assign tl_aes_o = tl_sm1_26_ds_h2d;
- assign tl_sm1_26_ds_d2h = tl_aes_i;
+ assign tl_flash_ctrl_o = tl_sm1_26_ds_h2d;
+ assign tl_sm1_26_ds_d2h = tl_flash_ctrl_i;
- assign tl_hmac_o = tl_sm1_27_ds_h2d;
- assign tl_sm1_27_ds_d2h = tl_hmac_i;
+ assign tl_aes_o = tl_sm1_27_ds_h2d;
+ assign tl_sm1_27_ds_d2h = tl_aes_i;
- assign tl_rv_plic_o = tl_sm1_28_ds_h2d;
- assign tl_sm1_28_ds_d2h = tl_rv_plic_i;
+ assign tl_hmac_o = tl_sm1_28_ds_h2d;
+ assign tl_sm1_28_ds_d2h = tl_hmac_i;
- assign tl_pinmux_o = tl_sm1_29_ds_h2d;
- assign tl_sm1_29_ds_d2h = tl_pinmux_i;
+ assign tl_rv_plic_o = tl_sm1_29_ds_h2d;
+ assign tl_sm1_29_ds_d2h = tl_rv_plic_i;
- assign tl_padctrl_o = tl_sm1_30_ds_h2d;
- assign tl_sm1_30_ds_d2h = tl_padctrl_i;
+ assign tl_pinmux_o = tl_sm1_30_ds_h2d;
+ assign tl_sm1_30_ds_d2h = tl_pinmux_i;
- assign tl_alert_handler_o = tl_sm1_31_ds_h2d;
- assign tl_sm1_31_ds_d2h = tl_alert_handler_i;
+ assign tl_padctrl_o = tl_sm1_31_ds_h2d;
+ assign tl_sm1_31_ds_d2h = tl_padctrl_i;
- assign tl_nmi_gen_o = tl_sm1_32_ds_h2d;
- assign tl_sm1_32_ds_d2h = tl_nmi_gen_i;
+ assign tl_alert_handler_o = tl_sm1_32_ds_h2d;
+ assign tl_sm1_32_ds_d2h = tl_alert_handler_i;
- assign tl_otbn_o = tl_sm1_33_ds_h2d;
- assign tl_sm1_33_ds_d2h = tl_otbn_i;
+ assign tl_nmi_gen_o = tl_sm1_33_ds_h2d;
+ assign tl_sm1_33_ds_d2h = tl_nmi_gen_i;
- assign tl_s1n_34_us_h2d = tl_dm_sba_i;
- assign tl_dm_sba_o = tl_s1n_34_us_d2h;
+ assign tl_otbn_o = tl_sm1_34_ds_h2d;
+ assign tl_sm1_34_ds_d2h = tl_otbn_i;
+
+ assign tl_s1n_35_us_h2d = tl_dm_sba_i;
+ assign tl_dm_sba_o = tl_s1n_35_us_d2h;
always_comb begin
// default steering to generate error response if address is not within the range
- dev_sel_s1n_17 = 3'd4;
- if ((tl_s1n_17_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
- dev_sel_s1n_17 = 3'd0;
+ dev_sel_s1n_18 = 3'd4;
+ if ((tl_s1n_18_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
+ dev_sel_s1n_18 = 3'd0;
- end else if ((tl_s1n_17_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin
- dev_sel_s1n_17 = 3'd1;
+ end else if ((tl_s1n_18_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin
+ dev_sel_s1n_18 = 3'd1;
- end else if ((tl_s1n_17_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
- dev_sel_s1n_17 = 3'd2;
+ end else if ((tl_s1n_18_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
+ dev_sel_s1n_18 = 3'd2;
- end else if ((tl_s1n_17_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
- dev_sel_s1n_17 = 3'd3;
+ end else if ((tl_s1n_18_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
+ dev_sel_s1n_18 = 3'd3;
end
end
always_comb begin
// default steering to generate error response if address is not within the range
- dev_sel_s1n_22 = 4'd14;
- if ((tl_s1n_22_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
- dev_sel_s1n_22 = 4'd0;
+ dev_sel_s1n_23 = 4'd15;
+ if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
+ dev_sel_s1n_23 = 4'd0;
- end else if ((tl_s1n_22_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin
- dev_sel_s1n_22 = 4'd1;
+ end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin
+ dev_sel_s1n_23 = 4'd1;
- end else if ((tl_s1n_22_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
- dev_sel_s1n_22 = 4'd2;
+ end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
+ dev_sel_s1n_23 = 4'd2;
- end else if ((tl_s1n_22_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
- dev_sel_s1n_22 = 4'd3;
+ end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
+ dev_sel_s1n_23 = 4'd3;
end else if (
- ((tl_s1n_22_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) ||
- ((tl_s1n_22_us_h2d.a_address <= (ADDR_MASK_PERI[1] + ADDR_SPACE_PERI[1])) &&
- (tl_s1n_22_us_h2d.a_address >= ADDR_SPACE_PERI[1])) ||
- ((tl_s1n_22_us_h2d.a_address <= (ADDR_MASK_PERI[2] + ADDR_SPACE_PERI[2])) &&
- (tl_s1n_22_us_h2d.a_address >= ADDR_SPACE_PERI[2])) ||
- ((tl_s1n_22_us_h2d.a_address <= (ADDR_MASK_PERI[3] + ADDR_SPACE_PERI[3])) &&
- (tl_s1n_22_us_h2d.a_address >= ADDR_SPACE_PERI[3])) ||
- ((tl_s1n_22_us_h2d.a_address <= (ADDR_MASK_PERI[4] + ADDR_SPACE_PERI[4])) &&
- (tl_s1n_22_us_h2d.a_address >= ADDR_SPACE_PERI[4])) ||
- ((tl_s1n_22_us_h2d.a_address <= (ADDR_MASK_PERI[5] + ADDR_SPACE_PERI[5])) &&
- (tl_s1n_22_us_h2d.a_address >= ADDR_SPACE_PERI[5]))
+ ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) ||
+ ((tl_s1n_23_us_h2d.a_address <= (ADDR_MASK_PERI[1] + ADDR_SPACE_PERI[1])) &&
+ (tl_s1n_23_us_h2d.a_address >= ADDR_SPACE_PERI[1])) ||
+ ((tl_s1n_23_us_h2d.a_address <= (ADDR_MASK_PERI[2] + ADDR_SPACE_PERI[2])) &&
+ (tl_s1n_23_us_h2d.a_address >= ADDR_SPACE_PERI[2])) ||
+ ((tl_s1n_23_us_h2d.a_address <= (ADDR_MASK_PERI[3] + ADDR_SPACE_PERI[3])) &&
+ (tl_s1n_23_us_h2d.a_address >= ADDR_SPACE_PERI[3])) ||
+ ((tl_s1n_23_us_h2d.a_address <= (ADDR_MASK_PERI[4] + ADDR_SPACE_PERI[4])) &&
+ (tl_s1n_23_us_h2d.a_address >= ADDR_SPACE_PERI[4])) ||
+ ((tl_s1n_23_us_h2d.a_address <= (ADDR_MASK_PERI[5] + ADDR_SPACE_PERI[5])) &&
+ (tl_s1n_23_us_h2d.a_address >= ADDR_SPACE_PERI[5]))
) begin
- dev_sel_s1n_22 = 4'd4;
+ dev_sel_s1n_23 = 4'd4;
- end else if ((tl_s1n_22_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin
- dev_sel_s1n_22 = 4'd5;
+ end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin
+ dev_sel_s1n_23 = 4'd5;
- end else if ((tl_s1n_22_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
- dev_sel_s1n_22 = 4'd6;
+ end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
+ dev_sel_s1n_23 = 4'd6;
- end else if ((tl_s1n_22_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
- dev_sel_s1n_22 = 4'd7;
+ end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
+ dev_sel_s1n_23 = 4'd7;
- end else if ((tl_s1n_22_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
- dev_sel_s1n_22 = 4'd8;
+ end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
+ dev_sel_s1n_23 = 4'd8;
- end else if ((tl_s1n_22_us_h2d.a_address & ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin
- dev_sel_s1n_22 = 4'd9;
+ end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin
+ dev_sel_s1n_23 = 4'd9;
- end else if ((tl_s1n_22_us_h2d.a_address & ~(ADDR_MASK_PADCTRL)) == ADDR_SPACE_PADCTRL) begin
- dev_sel_s1n_22 = 4'd10;
+ end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_PADCTRL)) == ADDR_SPACE_PADCTRL) begin
+ dev_sel_s1n_23 = 4'd10;
- end else if ((tl_s1n_22_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin
- dev_sel_s1n_22 = 4'd11;
+ end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin
+ dev_sel_s1n_23 = 4'd11;
- end else if ((tl_s1n_22_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin
- dev_sel_s1n_22 = 4'd12;
+ end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin
+ dev_sel_s1n_23 = 4'd12;
- end else if ((tl_s1n_22_us_h2d.a_address & ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin
- dev_sel_s1n_22 = 4'd13;
+ end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin
+ dev_sel_s1n_23 = 4'd13;
+
+ end else if ((tl_s1n_23_us_h2d.a_address & ~(ADDR_MASK_KEYMGR)) == ADDR_SPACE_KEYMGR) begin
+ dev_sel_s1n_23 = 4'd14;
end
end
always_comb begin
// default steering to generate error response if address is not within the range
- dev_sel_s1n_34 = 4'd13;
- if ((tl_s1n_34_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
- dev_sel_s1n_34 = 4'd0;
+ dev_sel_s1n_35 = 4'd13;
+ if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
+ dev_sel_s1n_35 = 4'd0;
- end else if ((tl_s1n_34_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
- dev_sel_s1n_34 = 4'd1;
+ end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
+ dev_sel_s1n_35 = 4'd1;
- end else if ((tl_s1n_34_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
- dev_sel_s1n_34 = 4'd2;
+ end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
+ dev_sel_s1n_35 = 4'd2;
end else if (
- ((tl_s1n_34_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) ||
- ((tl_s1n_34_us_h2d.a_address <= (ADDR_MASK_PERI[1] + ADDR_SPACE_PERI[1])) &&
- (tl_s1n_34_us_h2d.a_address >= ADDR_SPACE_PERI[1])) ||
- ((tl_s1n_34_us_h2d.a_address <= (ADDR_MASK_PERI[2] + ADDR_SPACE_PERI[2])) &&
- (tl_s1n_34_us_h2d.a_address >= ADDR_SPACE_PERI[2])) ||
- ((tl_s1n_34_us_h2d.a_address <= (ADDR_MASK_PERI[3] + ADDR_SPACE_PERI[3])) &&
- (tl_s1n_34_us_h2d.a_address >= ADDR_SPACE_PERI[3])) ||
- ((tl_s1n_34_us_h2d.a_address <= (ADDR_MASK_PERI[4] + ADDR_SPACE_PERI[4])) &&
- (tl_s1n_34_us_h2d.a_address >= ADDR_SPACE_PERI[4])) ||
- ((tl_s1n_34_us_h2d.a_address <= (ADDR_MASK_PERI[5] + ADDR_SPACE_PERI[5])) &&
- (tl_s1n_34_us_h2d.a_address >= ADDR_SPACE_PERI[5]))
+ ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_PERI[0])) == ADDR_SPACE_PERI[0]) ||
+ ((tl_s1n_35_us_h2d.a_address <= (ADDR_MASK_PERI[1] + ADDR_SPACE_PERI[1])) &&
+ (tl_s1n_35_us_h2d.a_address >= ADDR_SPACE_PERI[1])) ||
+ ((tl_s1n_35_us_h2d.a_address <= (ADDR_MASK_PERI[2] + ADDR_SPACE_PERI[2])) &&
+ (tl_s1n_35_us_h2d.a_address >= ADDR_SPACE_PERI[2])) ||
+ ((tl_s1n_35_us_h2d.a_address <= (ADDR_MASK_PERI[3] + ADDR_SPACE_PERI[3])) &&
+ (tl_s1n_35_us_h2d.a_address >= ADDR_SPACE_PERI[3])) ||
+ ((tl_s1n_35_us_h2d.a_address <= (ADDR_MASK_PERI[4] + ADDR_SPACE_PERI[4])) &&
+ (tl_s1n_35_us_h2d.a_address >= ADDR_SPACE_PERI[4])) ||
+ ((tl_s1n_35_us_h2d.a_address <= (ADDR_MASK_PERI[5] + ADDR_SPACE_PERI[5])) &&
+ (tl_s1n_35_us_h2d.a_address >= ADDR_SPACE_PERI[5]))
) begin
- dev_sel_s1n_34 = 4'd3;
+ dev_sel_s1n_35 = 4'd3;
- end else if ((tl_s1n_34_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin
- dev_sel_s1n_34 = 4'd4;
+ end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin
+ dev_sel_s1n_35 = 4'd4;
- end else if ((tl_s1n_34_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
- dev_sel_s1n_34 = 4'd5;
+ end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
+ dev_sel_s1n_35 = 4'd5;
- end else if ((tl_s1n_34_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
- dev_sel_s1n_34 = 4'd6;
+ end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
+ dev_sel_s1n_35 = 4'd6;
- end else if ((tl_s1n_34_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
- dev_sel_s1n_34 = 4'd7;
+ end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
+ dev_sel_s1n_35 = 4'd7;
- end else if ((tl_s1n_34_us_h2d.a_address & ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin
- dev_sel_s1n_34 = 4'd8;
+ end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin
+ dev_sel_s1n_35 = 4'd8;
- end else if ((tl_s1n_34_us_h2d.a_address & ~(ADDR_MASK_PADCTRL)) == ADDR_SPACE_PADCTRL) begin
- dev_sel_s1n_34 = 4'd9;
+ end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_PADCTRL)) == ADDR_SPACE_PADCTRL) begin
+ dev_sel_s1n_35 = 4'd9;
- end else if ((tl_s1n_34_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin
- dev_sel_s1n_34 = 4'd10;
+ end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin
+ dev_sel_s1n_35 = 4'd10;
- end else if ((tl_s1n_34_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin
- dev_sel_s1n_34 = 4'd11;
+ end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin
+ dev_sel_s1n_35 = 4'd11;
- end else if ((tl_s1n_34_us_h2d.a_address & ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin
- dev_sel_s1n_34 = 4'd12;
+ end else if ((tl_s1n_35_us_h2d.a_address & ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin
+ dev_sel_s1n_35 = 4'd12;
end
end
@@ -554,14 +563,14 @@
.DReqDepth (16'h0),
.DRspDepth (16'h0),
.N (4)
- ) u_s1n_17 (
+ ) u_s1n_18 (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
- .tl_h_i (tl_s1n_17_us_h2d),
- .tl_h_o (tl_s1n_17_us_d2h),
- .tl_d_o (tl_s1n_17_ds_h2d),
- .tl_d_i (tl_s1n_17_ds_d2h),
- .dev_select_i (dev_sel_s1n_17)
+ .tl_h_i (tl_s1n_18_us_h2d),
+ .tl_h_o (tl_s1n_18_us_d2h),
+ .tl_d_o (tl_s1n_18_ds_h2d),
+ .tl_d_i (tl_s1n_18_ds_d2h),
+ .dev_select_i (dev_sel_s1n_18)
);
tlul_socket_m1 #(
.HReqDepth (12'h0),
@@ -569,20 +578,6 @@
.DReqDepth (4'h0),
.DRspDepth (4'h0),
.M (3)
- ) u_sm1_18 (
- .clk_i (clk_main_i),
- .rst_ni (rst_main_ni),
- .tl_h_i (tl_sm1_18_us_h2d),
- .tl_h_o (tl_sm1_18_us_d2h),
- .tl_d_o (tl_sm1_18_ds_h2d),
- .tl_d_i (tl_sm1_18_ds_d2h)
- );
- tlul_socket_m1 #(
- .HReqDepth (8'h0),
- .HRspDepth (8'h0),
- .DReqPass (1'b0),
- .DRspPass (1'b0),
- .M (2)
) u_sm1_19 (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
@@ -592,11 +587,11 @@
.tl_d_i (tl_sm1_19_ds_d2h)
);
tlul_socket_m1 #(
- .HReqDepth (12'h0),
- .HRspDepth (12'h0),
- .DReqDepth (4'h0),
- .DRspDepth (4'h0),
- .M (3)
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
) u_sm1_20 (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
@@ -619,33 +614,49 @@
.tl_d_o (tl_sm1_21_ds_h2d),
.tl_d_i (tl_sm1_21_ds_d2h)
);
+ tlul_socket_m1 #(
+ .HReqDepth (12'h0),
+ .HRspDepth (12'h0),
+ .DReqDepth (4'h0),
+ .DRspDepth (4'h0),
+ .M (3)
+ ) u_sm1_22 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_22_us_h2d),
+ .tl_h_o (tl_sm1_22_us_d2h),
+ .tl_d_o (tl_sm1_22_ds_h2d),
+ .tl_d_i (tl_sm1_22_ds_d2h)
+ );
tlul_socket_1n #(
.HReqDepth (4'h0),
.HRspDepth (4'h0),
- .DReqDepth (56'h0),
- .DRspDepth (56'h0),
- .N (14)
- ) u_s1n_22 (
+ .DReqPass (15'h3fff),
+ .DRspPass (15'h3fff),
+ .DReqDepth (60'h200000000000000),
+ .DRspDepth (60'h200000000000000),
+ .N (15)
+ ) u_s1n_23 (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
- .tl_h_i (tl_s1n_22_us_h2d),
- .tl_h_o (tl_s1n_22_us_d2h),
- .tl_d_o (tl_s1n_22_ds_h2d),
- .tl_d_i (tl_s1n_22_ds_d2h),
- .dev_select_i (dev_sel_s1n_22)
+ .tl_h_i (tl_s1n_23_us_h2d),
+ .tl_h_o (tl_s1n_23_us_d2h),
+ .tl_d_o (tl_s1n_23_ds_h2d),
+ .tl_d_i (tl_s1n_23_ds_d2h),
+ .dev_select_i (dev_sel_s1n_23)
);
tlul_fifo_async #(
.ReqDepth (3),// At least 3 to make async work
.RspDepth (3) // At least 3 to make async work
- ) u_asf_23 (
+ ) u_asf_24 (
.clk_h_i (clk_main_i),
.rst_h_ni (rst_main_ni),
.clk_d_i (clk_fixed_i),
.rst_d_ni (rst_fixed_ni),
- .tl_h_i (tl_asf_23_us_h2d),
- .tl_h_o (tl_asf_23_us_d2h),
- .tl_d_o (tl_asf_23_ds_h2d),
- .tl_d_i (tl_asf_23_ds_d2h)
+ .tl_h_i (tl_asf_24_us_h2d),
+ .tl_h_o (tl_asf_24_us_d2h),
+ .tl_d_o (tl_asf_24_ds_h2d),
+ .tl_d_i (tl_asf_24_ds_d2h)
);
tlul_socket_m1 #(
.HReqDepth (8'h0),
@@ -653,20 +664,6 @@
.DReqDepth (4'h0),
.DRspDepth (4'h0),
.M (2)
- ) u_sm1_24 (
- .clk_i (clk_main_i),
- .rst_ni (rst_main_ni),
- .tl_h_i (tl_sm1_24_us_h2d),
- .tl_h_o (tl_sm1_24_us_d2h),
- .tl_d_o (tl_sm1_24_ds_h2d),
- .tl_d_i (tl_sm1_24_ds_d2h)
- );
- tlul_socket_m1 #(
- .HReqDepth (8'h0),
- .HRspDepth (8'h0),
- .DReqPass (1'b0),
- .DRspPass (1'b0),
- .M (2)
) u_sm1_25 (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
@@ -787,20 +784,34 @@
.tl_d_o (tl_sm1_33_ds_h2d),
.tl_d_i (tl_sm1_33_ds_d2h)
);
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_34 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_34_us_h2d),
+ .tl_h_o (tl_sm1_34_us_d2h),
+ .tl_d_o (tl_sm1_34_ds_h2d),
+ .tl_d_i (tl_sm1_34_ds_d2h)
+ );
tlul_socket_1n #(
.HReqPass (1'b0),
.HRspPass (1'b0),
.DReqDepth (52'h0),
.DRspDepth (52'h0),
.N (13)
- ) u_s1n_34 (
+ ) u_s1n_35 (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
- .tl_h_i (tl_s1n_34_us_h2d),
- .tl_h_o (tl_s1n_34_us_d2h),
- .tl_d_o (tl_s1n_34_ds_h2d),
- .tl_d_i (tl_s1n_34_ds_d2h),
- .dev_select_i (dev_sel_s1n_34)
+ .tl_h_i (tl_s1n_35_us_h2d),
+ .tl_h_o (tl_s1n_35_us_d2h),
+ .tl_d_o (tl_s1n_35_ds_h2d),
+ .tl_d_i (tl_s1n_35_ds_d2h),
+ .dev_select_i (dev_sel_s1n_35)
);
endmodule
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index c05a351..d6da257 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -124,10 +124,11 @@
logic cio_usbdev_dn_d2p;
logic cio_usbdev_dn_en_d2p;
// sensor_ctrl
+ // keymgr
// otbn
- logic [81:0] intr_vector;
+ logic [83:0] intr_vector;
// Interrupt source list
logic intr_uart_tx_watermark;
logic intr_uart_rx_watermark;
@@ -178,6 +179,8 @@
logic intr_usbdev_rx_bitstuff_err;
logic intr_usbdev_frame;
logic intr_usbdev_connected;
+ logic intr_keymgr_op_done;
+ logic intr_keymgr_err;
logic intr_otbn_done;
logic intr_otbn_err;
@@ -208,6 +211,7 @@
pwrmgr_pkg::pwr_rst_rsp_t pwrmgr_pwr_rst_rsp;
pwrmgr_pkg::pwr_clk_req_t pwrmgr_pwr_clk_req;
pwrmgr_pkg::pwr_clk_rsp_t pwrmgr_pwr_clk_rsp;
+ flash_ctrl_pkg::keymgr_flash_t flash_ctrl_keymgr;
logic pwrmgr_wakeups;
tlul_pkg::tl_h2d_t rom_tl_req;
tlul_pkg::tl_d2h_t rom_tl_rsp;
@@ -235,6 +239,8 @@
tlul_pkg::tl_d2h_t nmi_gen_tl_rsp;
tlul_pkg::tl_h2d_t otbn_tl_req;
tlul_pkg::tl_d2h_t otbn_tl_rsp;
+ tlul_pkg::tl_h2d_t keymgr_tl_req;
+ tlul_pkg::tl_d2h_t keymgr_tl_rsp;
tlul_pkg::tl_h2d_t uart_tl_req;
tlul_pkg::tl_d2h_t uart_tl_rsp;
tlul_pkg::tl_h2d_t gpio_tl_req;
@@ -651,6 +657,7 @@
.edn_i(flash_ctrl_pkg::EDN_ENTROPY_DEFAULT),
.pwrmgr_i(pwrmgr_pwr_flash_req),
.pwrmgr_o(pwrmgr_pwr_flash_rsp),
+ .keymgr_o(flash_ctrl_keymgr),
.tl_i(flash_ctrl_tl_req),
.tl_o(flash_ctrl_tl_rsp),
.clk_i (clkmgr_clocks.clk_main_infra),
@@ -955,17 +962,42 @@
.rst_ni (rstmgr_resets.rst_sys_io_div4_n)
);
+ keymgr u_keymgr (
+
+ // Interrupt
+ .intr_op_done_o (intr_keymgr_op_done),
+ .intr_err_o (intr_keymgr_err),
+
+ // [10]: err
+ .alert_tx_o ( alert_tx[10:10] ),
+ .alert_rx_i ( alert_rx[10:10] ),
+
+ // Inter-module signals
+ .aes_key_o(),
+ .hmac_key_o(),
+ .kmac_key_o(),
+ .kmac_data_o(),
+ .kmac_data_i(keymgr_pkg::KMAC_DATA_RSP_DEFAULT),
+ .lc_i(keymgr_pkg::LC_DATA_DEFAULT),
+ .otp_i(keymgr_pkg::OTP_DATA_DEFAULT),
+ .flash_i(flash_ctrl_keymgr),
+ .tl_i(keymgr_tl_req),
+ .tl_o(keymgr_tl_rsp),
+ .clk_i (clkmgr_clocks.clk_main_secure),
+ .rst_ni (rstmgr_resets.rst_sys_n)
+ );
+
otbn u_otbn (
// Interrupt
.intr_done_o (intr_otbn_done),
.intr_err_o (intr_otbn_err),
- // [10]: imem_uncorrectable
- // [11]: dmem_uncorrectable
- // [12]: reg_uncorrectable
- .alert_tx_o ( alert_tx[12:10] ),
- .alert_rx_i ( alert_rx[12:10] ),
+ // [11]: imem_uncorrectable
+ // [12]: dmem_uncorrectable
+ // [13]: reg_uncorrectable
+ .alert_tx_o ( alert_tx[13:11] ),
+ .alert_rx_i ( alert_rx[13:11] ),
// Inter-module signals
.idle_o(),
@@ -977,6 +1009,8 @@
// interrupt assignments
assign intr_vector = {
+ intr_keymgr_err,
+ intr_keymgr_op_done,
intr_otbn_err,
intr_otbn_done,
intr_pwrmgr_wakeup,
@@ -1105,6 +1139,10 @@
.tl_otbn_o(otbn_tl_req),
.tl_otbn_i(otbn_tl_rsp),
+ // port: tl_keymgr
+ .tl_keymgr_o(keymgr_tl_req),
+ .tl_keymgr_i(keymgr_tl_rsp),
+
.scanmode_i
);
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
index a046478..36688a4 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
@@ -22,6 +22,7 @@
parameter logic [31:0] TOP_EARLGREY_NMI_GEN_BASE_ADDR = 32'h40140000;
parameter logic [31:0] TOP_EARLGREY_USBDEV_BASE_ADDR = 32'h40150000;
parameter logic [31:0] TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR = 32'h40170000;
+ parameter logic [31:0] TOP_EARLGREY_KEYMGR_BASE_ADDR = 32'h401a0000;
parameter logic [31:0] TOP_EARLGREY_OTBN_BASE_ADDR = 32'h50000000;
// Enumeration for DIO pins.
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
index 88ded3d..186bdc4 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
@@ -11,7 +11,7 @@
* `top_earlgrey_plic_peripheral_t`.
*/
const top_earlgrey_plic_peripheral_t
- top_earlgrey_plic_interrupt_for_peripheral[82] = {
+ top_earlgrey_plic_interrupt_for_peripheral[84] = {
[kTopEarlgreyPlicIrqIdNone] = kTopEarlgreyPlicPeripheralUnknown,
[kTopEarlgreyPlicIrqIdGpioGpio0] = kTopEarlgreyPlicPeripheralGpio,
[kTopEarlgreyPlicIrqIdGpioGpio1] = kTopEarlgreyPlicPeripheralGpio,
@@ -94,6 +94,8 @@
[kTopEarlgreyPlicIrqIdPwrmgrWakeup] = kTopEarlgreyPlicPeripheralPwrmgr,
[kTopEarlgreyPlicIrqIdOtbnDone] = kTopEarlgreyPlicPeripheralOtbn,
[kTopEarlgreyPlicIrqIdOtbnErr] = kTopEarlgreyPlicPeripheralOtbn,
+ [kTopEarlgreyPlicIrqIdKeymgrOpDone] = kTopEarlgreyPlicPeripheralKeymgr,
+ [kTopEarlgreyPlicIrqIdKeymgrErr] = kTopEarlgreyPlicPeripheralKeymgr,
};
@@ -104,7 +106,7 @@
* `top_earlgrey_alert_peripheral_t`.
*/
const top_earlgrey_alert_peripheral_t
- top_earlgrey_alert_for_peripheral[13] = {
+ top_earlgrey_alert_for_peripheral[14] = {
[kTopEarlgreyAlertIdAesCtrlErrUpdate] = kTopEarlgreyAlertPeripheralAes,
[kTopEarlgreyAlertIdAesCtrlErrStorage] = kTopEarlgreyAlertPeripheralAes,
[kTopEarlgreyAlertIdHmacMsgPushShaDisabled] = kTopEarlgreyAlertPeripheralHmac,
@@ -118,5 +120,6 @@
[kTopEarlgreyAlertIdSensorCtrlAstAlerts4] = kTopEarlgreyAlertPeripheralSensorCtrl,
[kTopEarlgreyAlertIdSensorCtrlAstAlerts5] = kTopEarlgreyAlertPeripheralSensorCtrl,
[kTopEarlgreyAlertIdSensorCtrlAstAlerts6] = kTopEarlgreyAlertPeripheralSensorCtrl,
+ [kTopEarlgreyAlertIdKeymgrErr] = kTopEarlgreyAlertPeripheralKeymgr,
};
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index e0cd8ac..81759bb 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -333,6 +333,24 @@
#define TOP_EARLGREY_SENSOR_CTRL_SIZE_BYTES 0x1000u
/**
+ * Peripheral base address for keymgr in top earlgrey.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_EARLGREY_KEYMGR_BASE_ADDR 0x401a0000u
+
+/**
+ * Peripheral size for keymgr in top earlgrey.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_EARLGREY_KEYMGR_BASE_ADDR and
+ * `TOP_EARLGREY_KEYMGR_BASE_ADDR + TOP_EARLGREY_KEYMGR_SIZE_BYTES`.
+ */
+#define TOP_EARLGREY_KEYMGR_SIZE_BYTES 0x1000u
+
+/**
* Peripheral base address for otbn in top earlgrey.
*
* This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -410,7 +428,8 @@
kTopEarlgreyPlicPeripheralUsbdev = 8, /**< usbdev */
kTopEarlgreyPlicPeripheralPwrmgr = 9, /**< pwrmgr */
kTopEarlgreyPlicPeripheralOtbn = 10, /**< otbn */
- kTopEarlgreyPlicPeripheralLast = 10, /**< \internal Final PLIC peripheral */
+ kTopEarlgreyPlicPeripheralKeymgr = 11, /**< keymgr */
+ kTopEarlgreyPlicPeripheralLast = 11, /**< \internal Final PLIC peripheral */
} top_earlgrey_plic_peripheral_t;
/**
@@ -502,7 +521,9 @@
kTopEarlgreyPlicIrqIdPwrmgrWakeup = 79, /**< pwrmgr_wakeup */
kTopEarlgreyPlicIrqIdOtbnDone = 80, /**< otbn_done */
kTopEarlgreyPlicIrqIdOtbnErr = 81, /**< otbn_err */
- kTopEarlgreyPlicIrqIdLast = 81, /**< \internal The Last Valid Interrupt ID. */
+ kTopEarlgreyPlicIrqIdKeymgrOpDone = 82, /**< keymgr_op_done */
+ kTopEarlgreyPlicIrqIdKeymgrErr = 83, /**< keymgr_err */
+ kTopEarlgreyPlicIrqIdLast = 83, /**< \internal The Last Valid Interrupt ID. */
} top_earlgrey_plic_irq_id_t;
/**
@@ -512,7 +533,7 @@
* `top_earlgrey_plic_peripheral_t`.
*/
extern const top_earlgrey_plic_peripheral_t
- top_earlgrey_plic_interrupt_for_peripheral[82];
+ top_earlgrey_plic_interrupt_for_peripheral[84];
/**
* PLIC Interrupt Target.
@@ -536,7 +557,8 @@
kTopEarlgreyAlertPeripheralHmac = 1, /**< hmac */
kTopEarlgreyAlertPeripheralOtbn = 2, /**< otbn */
kTopEarlgreyAlertPeripheralSensorCtrl = 3, /**< sensor_ctrl */
- kTopEarlgreyAlertPeripheralLast = 3, /**< \internal Final Alert peripheral */
+ kTopEarlgreyAlertPeripheralKeymgr = 4, /**< keymgr */
+ kTopEarlgreyAlertPeripheralLast = 4, /**< \internal Final Alert peripheral */
} top_earlgrey_alert_peripheral_t;
/**
@@ -559,7 +581,8 @@
kTopEarlgreyAlertIdSensorCtrlAstAlerts4 = 10, /**< sensor_ctrl_ast_alerts 4 */
kTopEarlgreyAlertIdSensorCtrlAstAlerts5 = 11, /**< sensor_ctrl_ast_alerts 5 */
kTopEarlgreyAlertIdSensorCtrlAstAlerts6 = 12, /**< sensor_ctrl_ast_alerts 6 */
- kTopEarlgreyAlertIdLast = 12, /**< \internal The Last Valid Alert ID. */
+ kTopEarlgreyAlertIdKeymgrErr = 13, /**< keymgr_err */
+ kTopEarlgreyAlertIdLast = 13, /**< \internal The Last Valid Alert ID. */
} top_earlgrey_alert_id_t;
/**
@@ -569,7 +592,7 @@
* `top_earlgrey_alert_peripheral_t`.
*/
extern const top_earlgrey_alert_peripheral_t
- top_earlgrey_alert_for_peripheral[13];
+ top_earlgrey_alert_for_peripheral[14];
#define PINMUX_PERIPH_INSEL_IDX_OFFSET 2
