[prim] Split prim:subreg out of prim:all
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
diff --git a/hw/ip/prim/lint/prim.vlt b/hw/ip/prim/lint/prim.vlt
index c1663e5..d3093a0 100644
--- a/hw/ip/prim/lint/prim.vlt
+++ b/hw/ip/prim/lint/prim.vlt
@@ -4,10 +4,6 @@
`verilator_config
-// prim_subreg
-// for RO wd is not used
-lint_off -rule UNUSED -file "*/rtl/prim_subreg.sv" -match "Signal is not used: 'wd'"
-
// prim_lfsr
// lfsr_perm_test is just used for an SVA
lint_off -rule UNUSED -file "*/rtl/prim_lfsr.sv" -match "*lfsr_perm_test*"
diff --git a/hw/ip/prim/lint/prim.waiver b/hw/ip/prim/lint/prim.waiver
index e0c5dc1..1bf4d1c 100644
--- a/hw/ip/prim/lint/prim.waiver
+++ b/hw/ip/prim/lint/prim.waiver
@@ -16,10 +16,6 @@
waive -rules INTEGER -location {prim_packer.sv} -msg {'i' of type int used as a non-constant value} \
-comment "This assigns int i (signed) to a multibit logic variable (unsigned), which is fine"
-# primitives: prim_subreg
-waive -rules INPUT_NOT_READ -location {prim_subreg.sv} -regexp {Input port 'wd' is not read from} \
- -comment "for RO wd is not used"
-
# TL-UL fifo
waive -rules {HIER_BRANCH_NOT_READ} -location {tlul_fifo_sync.sv} -regexp {Connected net '(clk_i|rst_ni)' at prim_fifo_sync.sv:.* is not read from in module 'prim_fifo_sync'} \
-comment "In passthrough mode, clk and reset are not read form within this module"
diff --git a/hw/ip/prim/lint/prim_subreg.vlt b/hw/ip/prim/lint/prim_subreg.vlt
new file mode 100644
index 0000000..620f1d2
--- /dev/null
+++ b/hw/ip/prim/lint/prim_subreg.vlt
@@ -0,0 +1,9 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+`verilator_config
+
+// prim_subreg
+// for RO wd is not used
+lint_off -rule UNUSED -file "*/rtl/prim_subreg.sv" -match "Signal is not used: 'wd'"
diff --git a/hw/ip/prim/lint/prim_subreg.waiver b/hw/ip/prim/lint/prim_subreg.waiver
new file mode 100644
index 0000000..e0c83fa
--- /dev/null
+++ b/hw/ip/prim/lint/prim_subreg.waiver
@@ -0,0 +1,6 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+waive -rules INPUT_NOT_READ -location {prim_subreg.sv} -regexp {Input port 'wd' is not read from} \
+ -comment "for RO wd is not used"
diff --git a/hw/ip/prim/prim.core b/hw/ip/prim/prim.core
index 3bd92c0..31d9adc 100644
--- a/hw/ip/prim/prim.core
+++ b/hw/ip/prim/prim.core
@@ -22,6 +22,7 @@
- lowrisc:prim:arbiter
- lowrisc:prim:fifo
- lowrisc:prim:alert
+ - lowrisc:prim:subreg
files:
- rtl/prim_clock_gating_sync.sv
- rtl/prim_esc_pkg.sv
@@ -42,10 +43,6 @@
- rtl/prim_pulse_sync.sv
- rtl/prim_filter.sv
- rtl/prim_filter_ctr.sv
- - rtl/prim_subreg_arb.sv
- - rtl/prim_subreg.sv
- - rtl/prim_subreg_ext.sv
- - rtl/prim_subreg_shadow.sv
- rtl/prim_intr_hw.sv
file_type: systemVerilogSource
diff --git a/hw/ip/prim/prim_subreg.core b/hw/ip/prim/prim_subreg.core
new file mode 100644
index 0000000..a2d4d68
--- /dev/null
+++ b/hw/ip/prim/prim_subreg.core
@@ -0,0 +1,44 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "lowrisc:prim:subreg"
+description: "Register slices"
+filesets:
+ files_rtl:
+ files:
+ - rtl/prim_subreg_arb.sv
+ - rtl/prim_subreg.sv
+ - rtl/prim_subreg_ext.sv
+ - rtl/prim_subreg_shadow.sv
+ file_type: systemVerilogSource
+
+ files_verilator_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ files:
+ - lint/prim_subreg.vlt
+ file_type: vlt
+
+ files_ascentlint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ files:
+ - lint/prim_subreg.waiver
+ file_type: waiver
+
+ files_veriblelint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+
+targets:
+ default:
+ filesets:
+ - tool_verilator ? (files_verilator_waiver)
+ - tool_ascentlint ? (files_ascentlint_waiver)
+ - tool_veriblelint ? (files_veriblelint_waiver)
+ - files_rtl
