[top/chip] Rename chip-level tops
This renames all target specific toplevels such that they are prefixed
with chip_* instead of top_*. This is done to distinguish the
autogenerated toplevel, which contains all the IPs, crossbar, etc, from
the chiplevel wrappers that are target-specific.
Note that another option would have been to rename
top_<name> -> <name>, but we refrained from doing so as this would
change the definition of what we have so far referred to as the top,
and would have a more profound impact on tooling scripts, generated
headers and packages that use the name top_<name> inline (e.g.
hierarchical paths) or as part of the file name.
Signed-off-by: Michael Schaffner <msf@google.com>
diff --git a/doc/rm/ref_manual_fpga.md b/doc/rm/ref_manual_fpga.md
index aad79e2..f25bacf 100644
--- a/doc/rm/ref_manual_fpga.md
+++ b/doc/rm/ref_manual_fpga.md
@@ -39,13 +39,13 @@
```console
$ cd $REPO_TOP
$ ./util/fpga/splice_nexysvideo.sh
-$ fusesoc --cores-root . pgm lowrisc:systems:top_earlgrey_nexysvideo
+$ fusesoc --cores-root . pgm lowrisc:systems:chip_earlgrey_nexysvideo
```
-The script assumes that there is an existing bitfile `build/lowrisc_systems_top_earlgrey_nexysvideo_0.1/synth-vivado/lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit` (this is created after following the steps in [getting_started_fpga]({{< relref "doc/ug/getting_started_fpga" >}})).
+The script assumes that there is an existing bitfile `build/lowrisc_systems_chip_earlgrey_nexysvideo_0.1/synth-vivado/lowrisc_systems_chip_earlgrey_nexysvideo_0.1.bit` (this is created after following the steps in [getting_started_fpga]({{< relref "doc/ug/getting_started_fpga" >}})).
The script rebuilds the contents in `sw/devices/boot_rom` and then creates a new bitfile of the same name at the same location.
-The original input bitfile is moved to `build/lowrisc_systems_top_earlgrey_nexysvideo_0.1/synth-vivado/lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit.orig`.
+The original input bitfile is moved to `build/lowrisc_systems_chip_earlgrey_nexysvideo_0.1/synth-vivado/lowrisc_systems_chip_earlgrey_nexysvideo_0.1.bit.orig`.
The fusesoc command can then be directly invoked to flash the FPGA.
@@ -64,7 +64,7 @@
$ cd ${REPO_TOP}
$ ./meson_init.sh
$ ninja -C build-out
-$ build-bin/sw/host/spiflash/spiflash \
+$ build-bin/sw/host/spiflash/spiflash \
--input build-bin/sw/device/examples/hello_world/hello_world_fpga_nexysvideo.bin
Running SPI flash update.
diff --git a/doc/ug/getting_started_fpga.md b/doc/ug/getting_started_fpga.md
index 5c6d1ac..121bd2f 100644
--- a/doc/ug/getting_started_fpga.md
+++ b/doc/ug/getting_started_fpga.md
@@ -27,7 +27,7 @@
The FPGA build will pull in a program to act as the boot ROM.
This must be built before running the FPGA build.
-This is pulled in from the `sw/device/boot_rom` directory (see the `parameters:` section of the `hw/top_earlgrey/top_earlgrey_nexysvideo.core` file).
+This is pulled in from the `sw/device/boot_rom` directory (see the `parameters:` section of the `hw/top_earlgrey/chip_earlgrey_nexysvideo.core` file).
To build it:
```console
@@ -55,11 +55,11 @@
$ ./meson_init.sh
$ ./hw/top_earlgrey/util/top_earlgrey_reduce.py
$ ninja -C build-out all
-$ fusesoc --cores-root . run --flag=fileset_top --target=synth lowrisc:systems:top_earlgrey_nexysvideo
+$ fusesoc --cores-root . run --flag=fileset_top --target=synth lowrisc:systems:chip_earlgrey_nexysvideo
```
The `fileset_top` flag used above is specific to the OpenTitan project to select the correct fileset.
-The resulting bitstream is located at `build/lowrisc_systems_top_earlgrey_nexysvideo_0.1/synth-vivado/lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit`.
+The resulting bitstream is located at `build/lowrisc_systems_chip_earlgrey_nexysvideo_0.1/synth-vivado/lowrisc_systems_chip_earlgrey_nexysvideo_0.1.bit`.
See the [reference manual]({{< relref "ref_manual_fpga.md" >}}) for more information.
## Connecting the board
@@ -80,7 +80,7 @@
```console
$ . /tools/xilinx/Vivado/2020.1/settings64.sh
$ cd $REPO_TOP
-$ fusesoc --cores-root . pgm lowrisc:systems:top_earlgrey_nexysvideo:0.1
+$ fusesoc --cores-root . pgm lowrisc:systems:chip_earlgrey_nexysvideo:0.1
```
This should produce a message like this from the UART:
@@ -101,7 +101,7 @@
```console
$ . /tools/xilinx/Vivado/2020.1/settings64.sh
$ cd $REPO_TOP
-$ make -C build/lowrisc_systems_top_earlgrey_nexysvideo_0.1/synth-vivado build-gui
+$ make -C build/lowrisc_systems_chip_earlgrey_nexysvideo_0.1/synth-vivado build-gui
```
Now the Vivado GUI opens and loads the project.
@@ -110,7 +110,7 @@
* In the navigation on the left, click on *PROGRAM AND DEBUG* > *Open Hardware Manager* > *Open Target* > *Auto Connect*.
* Vivado now enumerates all boards and connects to it.
* Click on *Program Device* in the menu on the left (or at the top of the screen).
-* A dialog titled *Program Device* pops up. Select the file `lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit` as *Bitstream file*, and leave the *Debug probes file* empty.
+* A dialog titled *Program Device* pops up. Select the file `lowrisc_systems_chip_earlgrey_nexysvideo_0.1.bit` as *Bitstream file*, and leave the *Debug probes file* empty.
* Click on *Program* to flash the FPGA with the bitstream.
* The FPGA is ready as soon as the programming finishes.
@@ -186,7 +186,7 @@
```console
$ # only create Vivado project file
-$ fusesoc --cores-root . build --no-export --setup lowrisc:systems:top_earlgrey_nexysvideo
+$ fusesoc --cores-root . build --no-export --setup lowrisc:systems:chip_earlgrey_nexysvideo
```
## Connect with OpenOCD and debug
diff --git a/doc/ug/getting_started_verilator.md b/doc/ug/getting_started_verilator.md
index a9cbc6e..f63ef48 100644
--- a/doc/ug/getting_started_verilator.md
+++ b/doc/ug/getting_started_verilator.md
@@ -19,7 +19,7 @@
```console
$ cd $REPO_TOP
-$ fusesoc --cores-root . run --flag=fileset_top --target=sim --setup --build lowrisc:systems:top_earlgrey_verilator
+$ fusesoc --cores-root . run --flag=fileset_top --target=sim --setup --build lowrisc:systems:chip_earlgrey_verilator
```
The fsel_top flag used above is specific to the OpenTitan project to select the correct fileset.
@@ -46,7 +46,7 @@
```console
$ cd $REPO_TOP
-$ build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator \
+$ build/lowrisc_systems_chip_earlgrey_verilator_0.1/sim-verilator/Vchip_earlgrey_verilator \
--meminit=rom,build-bin/sw/device/boot_rom/boot_rom_sim_verilator.elf \
--meminit=flash,build-bin/sw/device/examples/hello_world/hello_world_sim_verilator.elf \
--meminit=otp,build-bin/sw/device/otp_img/otp_img_sim_verilator.vmem
@@ -103,7 +103,7 @@
A full command-line invocation of the simulation could then look like that:
```console
$ cd $REPO_TOP
-$ build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator \
+$ build/lowrisc_systems_chip_earlgrey_verilator_0.1/sim-verilator/Vchip_earlgrey_verilator \
--meminit=rom,build-bin/sw/device/boot_rom/boot_rom_sim_verilator.elf \
--meminit=flash,build-bin/sw/device/examples/hello_world/hello_world_sim_verilator.elf \
--meminit=otp,build-bin/sw/device/otp_img/otp_img_sim_verilator.vmem \
@@ -195,7 +195,7 @@
```console
$ cd $REPO_TOP
-$ build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator \
+$ build/lowrisc_systems_chip_earlgrey_verilator_0.1/sim-verilator/Vchip_earlgrey_verilator \
--meminit=rom,build-bin/sw/device/boot_rom/boot_rom_sim_verilator.elf \
--meminit=flash,build-bin/sw/device/examples/hello_world/hello_world_sim_verilator.elf \
--meminit=otp,build-bin/sw/device/otp_img/otp_img_sim_verilator.vmem \
diff --git a/doc/ug/quickstart.md b/doc/ug/quickstart.md
index de63579..d8d1a25 100644
--- a/doc/ug/quickstart.md
+++ b/doc/ug/quickstart.md
@@ -33,10 +33,10 @@
## Simulation with Verilator
-Run the provided simulator binary with
+Run the provided simulator binary with
```console
$ cd $OT_TOP
-$ ./hw/top_earlgrey/Vtop_earlgrey_verilator --rominit=./sw/device/sim/boot_rom/rom.vmem --flashinit=./sw/device/sim/examples/hello_world/sw.vmem
+$ ./hw/top_earlgrey/Vchip_earlgrey_verilator --rominit=./sw/device/sim/boot_rom/rom.vmem --flashinit=./sw/device/sim/examples/hello_world/sw.vmem
Simulation of OpenTitan Earl Grey
=================================
@@ -68,7 +68,7 @@
$ screen /dev/pts/6
Simulation running, end by pressing CTRL-c.
-TOP.top_earlgrey_verilator.top_earlgrey.core.ibex_tracer_i: Writing execution trace to trace_core_00000000.log
+TOP.chip_earlgrey_verilator.top_earlgrey.core.ibex_tracer_i: Writing execution trace to trace_core_00000000.log
```
Note the UART output will be available on `/dev/pts/N`, `/dev/pts/6` in this example.
@@ -141,7 +141,7 @@
6. Copy the bit file image to the storage device.
```console
$ cd $OT_TOP
- $ cp hw/top_earlgrey/lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit ~/ot-img-mount/
+ $ cp hw/top_earlgrey/lowrisc_systems_chip_earlgrey_nexysvideo_0.1.bit ~/ot-img-mount/
```
For more information on programming the Nexsys Video FPGA board refer to Section 2.3 of [Nexys Video reference manual](https://reference.digilentinc.com/_media/reference/programmable-logic/nexys-video/nexysvideo_rm.pdf).
