[top/chip] Rename chip-level tops
This renames all target specific toplevels such that they are prefixed
with chip_* instead of top_*. This is done to distinguish the
autogenerated toplevel, which contains all the IPs, crossbar, etc, from
the chiplevel wrappers that are target-specific.
Note that another option would have been to rename
top_<name> -> <name>, but we refrained from doing so as this would
change the definition of what we have so far referred to as the top,
and would have a more profound impact on tooling scripts, generated
headers and packages that use the name top_<name> inline (e.g.
hierarchical paths) or as part of the file name.
Signed-off-by: Michael Schaffner <msf@google.com>
diff --git a/azure-pipelines.yml b/azure-pipelines.yml
index 6e9c7eb..7321907 100644
--- a/azure-pipelines.yml
+++ b/azure-pipelines.yml
@@ -200,7 +200,7 @@
ninja -C "$OBJ_DIR" test
displayName: Run unit tests
-- job: top_earlgrey_verilator
+- job: chip_earlgrey_verilator
displayName: Build Verilator simulation of the Earl Grey toplevel design
dependsOn: lint
condition: and(succeeded(), eq(dependencies.lint.outputs['DetermineBuildType.onlyDocChanges'], '0'))
@@ -225,18 +225,18 @@
fusesoc --cores-root=. \
run --flag=fileset_top --target=sim --setup --build \
--build-root="$OBJ_DIR/hw" \
- lowrisc:systems:top_earlgrey_verilator \
+ lowrisc:systems:chip_earlgrey_verilator \
--verilator_options="--no-threads"
- cp "$OBJ_DIR/hw/sim-verilator/Vtop_earlgrey_verilator" \
+ cp "$OBJ_DIR/hw/sim-verilator/Vchip_earlgrey_verilator" \
"$BIN_DIR/hw/top_earlgrey"
displayName: Build simulation with Verilator
- template: ci/upload-artifacts-template.yml
parameters:
includePatterns:
- - "/hw/top_earlgrey/Vtop_earlgrey_verilator"
+ - "/hw/top_earlgrey/Vchip_earlgrey_verilator"
-- job: top_englishbreakfast_verilator
+- job: chip_englishbreakfast_verilator
displayName: Build Verilator simulation of the English Breakfast toplevel design
dependsOn: lint
condition: and(succeeded(), eq(dependencies.lint.outputs['DetermineBuildType.onlyDocChanges'], '0'))
@@ -261,30 +261,30 @@
fusesoc --cores-root=. \
run --flag=fileset_topgen --target=sim --setup --build \
--build-root="$OBJ_DIR/hw" \
- lowrisc:systems:top_englishbreakfast_verilator \
+ lowrisc:systems:chip_englishbreakfast_verilator \
--verilator_options="--no-threads"
- cp "$OBJ_DIR/hw/sim-verilator/Vtop_englishbreakfast_verilator" \
+ cp "$OBJ_DIR/hw/sim-verilator/Vchip_englishbreakfast_verilator" \
"$BIN_DIR/hw/top_englishbreakfast"
displayName: Build simulation with Verilator
- template: ci/upload-artifacts-template.yml
parameters:
includePatterns:
- - "/hw/top_englishbreakfast/Vtop_englishbreakfast_verilator"
+ - "/hw/top_englishbreakfast/Vchip_englishbreakfast_verilator"
- job: execute_verilated_tests
displayName: Execute tests on the Verilated system
pool:
vmImage: ubuntu-18.04
dependsOn:
- - top_earlgrey_verilator
+ - chip_earlgrey_verilator
- sw_build
steps:
- template: ci/install-package-dependencies.yml
- template: ci/download-artifacts-template.yml
parameters:
downloadPartialBuildBinFrom:
- - top_earlgrey_verilator
+ - chip_earlgrey_verilator
- sw_build
- bash: |
# Install an additional pytest dependency for result upload.
@@ -342,7 +342,7 @@
make -C hw/ip/otbn/util asm-check
displayName: Assemble and link code snippets
-- job: top_earlgrey_nexysvideo
+- job: chip_earlgrey_nexysvideo
displayName: Build NexysVideo variant of the Earl Grey toplevel design using Vivado
dependsOn:
- lint
@@ -376,28 +376,28 @@
fusesoc --cores-root=. \
run --flag=fileset_top --target=synth --setup --build \
--build-root="$OBJ_DIR/hw" \
- lowrisc:systems:top_earlgrey_nexysvideo \
+ lowrisc:systems:chip_earlgrey_nexysvideo \
--BootRomInitFile="$BOOTROM_VMEM" \
--OtpCtrlMemInitFile="$OTP_VMEM"
- cp "$OBJ_DIR/hw/synth-vivado/lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit" \
+ cp "$OBJ_DIR/hw/synth-vivado/lowrisc_systems_chip_earlgrey_nexysvideo_0.1.bit" \
"$BIN_DIR/hw/top_earlgrey"
displayName: Build bitstream with Vivado
- bash: |
. util/build_consts.sh
echo Synthesis log
- cat $OBJ_DIR/hw/synth-vivado/lowrisc_systems_top_earlgrey_nexysvideo_0.1.runs/synth_1/runme.log || true
+ cat $OBJ_DIR/hw/synth-vivado/lowrisc_systems_chip_earlgrey_nexysvideo_0.1.runs/synth_1/runme.log || true
echo Implementation log
- cat $OBJ_DIR/hw/synth-vivado/lowrisc_systems_top_earlgrey_nexysvideo_0.1.runs/impl_1/runme.log || true
+ cat $OBJ_DIR/hw/synth-vivado/lowrisc_systems_chip_earlgrey_nexysvideo_0.1.runs/impl_1/runme.log || true
condition: always()
displayName: Display synthesis and implementation logs
- template: ci/upload-artifacts-template.yml
parameters:
includePatterns:
- - "/hw/top_earlgrey/lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit"
+ - "/hw/top_earlgrey/lowrisc_systems_chip_earlgrey_nexysvideo_0.1.bit"
-- job: top_englishbreakfast_cw305
+- job: chip_englishbreakfast_cw305
displayName: Build CW305 variant of the English Breakfast toplevel design using Vivado
dependsOn:
- lint
@@ -431,23 +431,23 @@
fusesoc --cores-root=. \
run --flag=fileset_topgen --target=synth --setup --build \
--build-root="$OBJ_DIR/hw" \
- lowrisc:systems:top_englishbreakfast_cw305 \
+ lowrisc:systems:chip_englishbreakfast_cw305 \
--BootRomInitFile="$BOOTROM_VMEM"
- cp "$OBJ_DIR/hw/synth-vivado/lowrisc_systems_top_englishbreakfast_cw305_0.1.bit" \
+ cp "$OBJ_DIR/hw/synth-vivado/lowrisc_systems_chip_englishbreakfast_cw305_0.1.bit" \
"$BIN_DIR/hw/top_englishbreakfast"
displayName: Build bitstream with Vivado
- template: ci/upload-artifacts-template.yml
parameters:
includePatterns:
- - "/hw/top_englishbreakfast/lowrisc_systems_top_englishbreakfast_cw305_0.1.bit"
+ - "/hw/top_englishbreakfast/lowrisc_systems_chip_englishbreakfast_cw305_0.1.bit"
- job: execute_fpga_tests
displayName: Execute tests on FPGA
pool: FPGA
timeoutInMinutes: 30
dependsOn:
- - top_earlgrey_nexysvideo
+ - chip_earlgrey_nexysvideo
- sw_build_nexysvideo
- sw_build
steps:
@@ -455,7 +455,7 @@
- template: ci/download-artifacts-template.yml
parameters:
downloadPartialBuildBinFrom:
- - top_earlgrey_nexysvideo
+ - chip_earlgrey_nexysvideo
- sw_build_nexysvideo
- sw_build
- bash: |
@@ -481,8 +481,8 @@
dependsOn:
- lint
- sw_build
- - top_earlgrey_verilator
- - top_earlgrey_nexysvideo
+ - chip_earlgrey_verilator
+ - chip_earlgrey_nexysvideo
condition: and(eq(dependencies.lint.outputs['DetermineBuildType.onlyDocChanges'], '0'), eq(dependencies.lint.outputs['DetermineBuildType.onlyDvChanges'], '0'))
steps:
- template: ci/install-package-dependencies.yml
@@ -491,9 +491,9 @@
downloadPartialBuildBinFrom:
- sw_build
- sw_build_nexysvideo
- - top_earlgrey_verilator
- - top_earlgrey_nexysvideo
- - top_englishbreakfast_verilator
+ - chip_earlgrey_verilator
+ - chip_earlgrey_nexysvideo
+ - chip_englishbreakfast_verilator
- bash: |
. util/build_consts.sh
diff --git a/ci/run-riscv-compliance.yml b/ci/run-riscv-compliance.yml
index 4e15474..a94d951 100644
--- a/ci/run-riscv-compliance.yml
+++ b/ci/run-riscv-compliance.yml
@@ -14,7 +14,7 @@
pool:
vmImage: ubuntu-18.04
dependsOn:
- - top_earlgrey_verilator
+ - chip_earlgrey_verilator
- sw_build
steps:
- template: install-package-dependencies.yml
diff --git a/ci/run_riscv_compliance.sh b/ci/run_riscv_compliance.sh
index cb5d641..24be1e2 100755
--- a/ci/run_riscv_compliance.sh
+++ b/ci/run_riscv_compliance.sh
@@ -6,7 +6,7 @@
. util/build_consts.sh
-export TARGET_SIM="$BIN_DIR/hw/top_earlgrey/Vtop_earlgrey_verilator"
+export TARGET_SIM="$BIN_DIR/hw/top_earlgrey/Vchip_earlgrey_verilator"
export RISCV_DEVICE=rv32imc
export RISCV_TARGET=opentitan
export OT_BIN="$BIN_DIR"
diff --git a/doc/rm/ref_manual_fpga.md b/doc/rm/ref_manual_fpga.md
index aad79e2..f25bacf 100644
--- a/doc/rm/ref_manual_fpga.md
+++ b/doc/rm/ref_manual_fpga.md
@@ -39,13 +39,13 @@
```console
$ cd $REPO_TOP
$ ./util/fpga/splice_nexysvideo.sh
-$ fusesoc --cores-root . pgm lowrisc:systems:top_earlgrey_nexysvideo
+$ fusesoc --cores-root . pgm lowrisc:systems:chip_earlgrey_nexysvideo
```
-The script assumes that there is an existing bitfile `build/lowrisc_systems_top_earlgrey_nexysvideo_0.1/synth-vivado/lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit` (this is created after following the steps in [getting_started_fpga]({{< relref "doc/ug/getting_started_fpga" >}})).
+The script assumes that there is an existing bitfile `build/lowrisc_systems_chip_earlgrey_nexysvideo_0.1/synth-vivado/lowrisc_systems_chip_earlgrey_nexysvideo_0.1.bit` (this is created after following the steps in [getting_started_fpga]({{< relref "doc/ug/getting_started_fpga" >}})).
The script rebuilds the contents in `sw/devices/boot_rom` and then creates a new bitfile of the same name at the same location.
-The original input bitfile is moved to `build/lowrisc_systems_top_earlgrey_nexysvideo_0.1/synth-vivado/lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit.orig`.
+The original input bitfile is moved to `build/lowrisc_systems_chip_earlgrey_nexysvideo_0.1/synth-vivado/lowrisc_systems_chip_earlgrey_nexysvideo_0.1.bit.orig`.
The fusesoc command can then be directly invoked to flash the FPGA.
@@ -64,7 +64,7 @@
$ cd ${REPO_TOP}
$ ./meson_init.sh
$ ninja -C build-out
-$ build-bin/sw/host/spiflash/spiflash \
+$ build-bin/sw/host/spiflash/spiflash \
--input build-bin/sw/device/examples/hello_world/hello_world_fpga_nexysvideo.bin
Running SPI flash update.
diff --git a/doc/ug/getting_started_fpga.md b/doc/ug/getting_started_fpga.md
index 5c6d1ac..121bd2f 100644
--- a/doc/ug/getting_started_fpga.md
+++ b/doc/ug/getting_started_fpga.md
@@ -27,7 +27,7 @@
The FPGA build will pull in a program to act as the boot ROM.
This must be built before running the FPGA build.
-This is pulled in from the `sw/device/boot_rom` directory (see the `parameters:` section of the `hw/top_earlgrey/top_earlgrey_nexysvideo.core` file).
+This is pulled in from the `sw/device/boot_rom` directory (see the `parameters:` section of the `hw/top_earlgrey/chip_earlgrey_nexysvideo.core` file).
To build it:
```console
@@ -55,11 +55,11 @@
$ ./meson_init.sh
$ ./hw/top_earlgrey/util/top_earlgrey_reduce.py
$ ninja -C build-out all
-$ fusesoc --cores-root . run --flag=fileset_top --target=synth lowrisc:systems:top_earlgrey_nexysvideo
+$ fusesoc --cores-root . run --flag=fileset_top --target=synth lowrisc:systems:chip_earlgrey_nexysvideo
```
The `fileset_top` flag used above is specific to the OpenTitan project to select the correct fileset.
-The resulting bitstream is located at `build/lowrisc_systems_top_earlgrey_nexysvideo_0.1/synth-vivado/lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit`.
+The resulting bitstream is located at `build/lowrisc_systems_chip_earlgrey_nexysvideo_0.1/synth-vivado/lowrisc_systems_chip_earlgrey_nexysvideo_0.1.bit`.
See the [reference manual]({{< relref "ref_manual_fpga.md" >}}) for more information.
## Connecting the board
@@ -80,7 +80,7 @@
```console
$ . /tools/xilinx/Vivado/2020.1/settings64.sh
$ cd $REPO_TOP
-$ fusesoc --cores-root . pgm lowrisc:systems:top_earlgrey_nexysvideo:0.1
+$ fusesoc --cores-root . pgm lowrisc:systems:chip_earlgrey_nexysvideo:0.1
```
This should produce a message like this from the UART:
@@ -101,7 +101,7 @@
```console
$ . /tools/xilinx/Vivado/2020.1/settings64.sh
$ cd $REPO_TOP
-$ make -C build/lowrisc_systems_top_earlgrey_nexysvideo_0.1/synth-vivado build-gui
+$ make -C build/lowrisc_systems_chip_earlgrey_nexysvideo_0.1/synth-vivado build-gui
```
Now the Vivado GUI opens and loads the project.
@@ -110,7 +110,7 @@
* In the navigation on the left, click on *PROGRAM AND DEBUG* > *Open Hardware Manager* > *Open Target* > *Auto Connect*.
* Vivado now enumerates all boards and connects to it.
* Click on *Program Device* in the menu on the left (or at the top of the screen).
-* A dialog titled *Program Device* pops up. Select the file `lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit` as *Bitstream file*, and leave the *Debug probes file* empty.
+* A dialog titled *Program Device* pops up. Select the file `lowrisc_systems_chip_earlgrey_nexysvideo_0.1.bit` as *Bitstream file*, and leave the *Debug probes file* empty.
* Click on *Program* to flash the FPGA with the bitstream.
* The FPGA is ready as soon as the programming finishes.
@@ -186,7 +186,7 @@
```console
$ # only create Vivado project file
-$ fusesoc --cores-root . build --no-export --setup lowrisc:systems:top_earlgrey_nexysvideo
+$ fusesoc --cores-root . build --no-export --setup lowrisc:systems:chip_earlgrey_nexysvideo
```
## Connect with OpenOCD and debug
diff --git a/doc/ug/getting_started_verilator.md b/doc/ug/getting_started_verilator.md
index a9cbc6e..f63ef48 100644
--- a/doc/ug/getting_started_verilator.md
+++ b/doc/ug/getting_started_verilator.md
@@ -19,7 +19,7 @@
```console
$ cd $REPO_TOP
-$ fusesoc --cores-root . run --flag=fileset_top --target=sim --setup --build lowrisc:systems:top_earlgrey_verilator
+$ fusesoc --cores-root . run --flag=fileset_top --target=sim --setup --build lowrisc:systems:chip_earlgrey_verilator
```
The fsel_top flag used above is specific to the OpenTitan project to select the correct fileset.
@@ -46,7 +46,7 @@
```console
$ cd $REPO_TOP
-$ build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator \
+$ build/lowrisc_systems_chip_earlgrey_verilator_0.1/sim-verilator/Vchip_earlgrey_verilator \
--meminit=rom,build-bin/sw/device/boot_rom/boot_rom_sim_verilator.elf \
--meminit=flash,build-bin/sw/device/examples/hello_world/hello_world_sim_verilator.elf \
--meminit=otp,build-bin/sw/device/otp_img/otp_img_sim_verilator.vmem
@@ -103,7 +103,7 @@
A full command-line invocation of the simulation could then look like that:
```console
$ cd $REPO_TOP
-$ build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator \
+$ build/lowrisc_systems_chip_earlgrey_verilator_0.1/sim-verilator/Vchip_earlgrey_verilator \
--meminit=rom,build-bin/sw/device/boot_rom/boot_rom_sim_verilator.elf \
--meminit=flash,build-bin/sw/device/examples/hello_world/hello_world_sim_verilator.elf \
--meminit=otp,build-bin/sw/device/otp_img/otp_img_sim_verilator.vmem \
@@ -195,7 +195,7 @@
```console
$ cd $REPO_TOP
-$ build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator \
+$ build/lowrisc_systems_chip_earlgrey_verilator_0.1/sim-verilator/Vchip_earlgrey_verilator \
--meminit=rom,build-bin/sw/device/boot_rom/boot_rom_sim_verilator.elf \
--meminit=flash,build-bin/sw/device/examples/hello_world/hello_world_sim_verilator.elf \
--meminit=otp,build-bin/sw/device/otp_img/otp_img_sim_verilator.vmem \
diff --git a/doc/ug/quickstart.md b/doc/ug/quickstart.md
index de63579..d8d1a25 100644
--- a/doc/ug/quickstart.md
+++ b/doc/ug/quickstart.md
@@ -33,10 +33,10 @@
## Simulation with Verilator
-Run the provided simulator binary with
+Run the provided simulator binary with
```console
$ cd $OT_TOP
-$ ./hw/top_earlgrey/Vtop_earlgrey_verilator --rominit=./sw/device/sim/boot_rom/rom.vmem --flashinit=./sw/device/sim/examples/hello_world/sw.vmem
+$ ./hw/top_earlgrey/Vchip_earlgrey_verilator --rominit=./sw/device/sim/boot_rom/rom.vmem --flashinit=./sw/device/sim/examples/hello_world/sw.vmem
Simulation of OpenTitan Earl Grey
=================================
@@ -68,7 +68,7 @@
$ screen /dev/pts/6
Simulation running, end by pressing CTRL-c.
-TOP.top_earlgrey_verilator.top_earlgrey.core.ibex_tracer_i: Writing execution trace to trace_core_00000000.log
+TOP.chip_earlgrey_verilator.top_earlgrey.core.ibex_tracer_i: Writing execution trace to trace_core_00000000.log
```
Note the UART output will be available on `/dev/pts/N`, `/dev/pts/6` in this example.
@@ -141,7 +141,7 @@
6. Copy the bit file image to the storage device.
```console
$ cd $OT_TOP
- $ cp hw/top_earlgrey/lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit ~/ot-img-mount/
+ $ cp hw/top_earlgrey/lowrisc_systems_chip_earlgrey_nexysvideo_0.1.bit ~/ot-img-mount/
```
For more information on programming the Nexsys Video FPGA board refer to Section 2.3 of [Nexys Video reference manual](https://reference.digilentinc.com/_media/reference/programmable-logic/nexys-video/nexysvideo_rm.pdf).
diff --git a/hw/ip/otbn/README.md b/hw/ip/otbn/README.md
index 7e5c7be..948cc57 100644
--- a/hw/ip/otbn/README.md
+++ b/hw/ip/otbn/README.md
@@ -95,7 +95,7 @@
can be used to switch between the RTL implementation and the model, without
recompiling the simulation.
-The Verilator simulation of Earl Grey (`lowrisc:systems:top_earlgrey_verilator`)
+The Verilator simulation of Earl Grey (`lowrisc:systems:chip_earlgrey_verilator`)
builds the model by default when compiling the simulation and nothing else needs
to be done. For other simulation targets, set the `OTBN_BUILD_MODEL` define,
e.g. by passing `--OTBN_BUILD_MODEL` to fusesoc.
@@ -104,7 +104,7 @@
simulation run, e.g.
```sh
-build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator \
+build/lowrisc_systems_chip_earlgrey_verilator_0.1/sim-verilator/Vchip_earlgrey_verilator \
--meminit=rom,build-bin/sw/device/boot_rom/boot_rom_sim_verilator.elf \
--meminit=flash,build-bin/sw/device/tests/dif_otbn_smoketest_sim_verilator.elf \
--meminit=otp,build-bin/sw/device/otp_img/otp_img_sim_verilator.vmem \
diff --git a/hw/syn/tools/dc/run-syn.tcl b/hw/syn/tools/dc/run-syn.tcl
index fb78197..96784aa 100644
--- a/hw/syn/tools/dc/run-syn.tcl
+++ b/hw/syn/tools/dc/run-syn.tcl
@@ -41,7 +41,7 @@
set BUILD_DIR $::env(BUILD_DIR)
# just compile the "core" toplevel at the moment
-# might want to switch to top_earlgrey_asic later on (with pads)
+# might want to switch to chip_earlgrey_asic later on (with pads)
set DUT $::env(DUT)
set CONSTRAINT $::env(CONSTRAINT)
set FOUNDRY_CONSTRAINT $::env(FOUNDRY_CONSTRAINT)
diff --git a/hw/top_earlgrey/top_earlgrey_asic.core b/hw/top_earlgrey/chip_earlgrey_asic.core
similarity index 89%
rename from hw/top_earlgrey/top_earlgrey_asic.core
rename to hw/top_earlgrey/chip_earlgrey_asic.core
index 3b480d9..84546aa 100644
--- a/hw/top_earlgrey/top_earlgrey_asic.core
+++ b/hw/top_earlgrey/chip_earlgrey_asic.core
@@ -2,7 +2,7 @@
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:systems:top_earlgrey_asic:0.1"
+name: "lowrisc:systems:chip_earlgrey_asic:0.1"
description: "Earl Grey chip level"
filesets:
files_rtl:
@@ -12,7 +12,7 @@
- "!fileset_partner ? (lowrisc:systems:ast)"
- "fileset_partner ? (partner:systems:ast)"
files:
- - rtl/autogen/top_earlgrey_asic.sv
+ - rtl/autogen/chip_earlgrey_asic.sv
file_type: systemVerilogSource
files_verilator_waiver:
@@ -47,7 +47,7 @@
- tool_ascentlint ? (files_ascentlint_waiver)
- tool_veriblelint ? (files_veriblelint_waiver)
- files_rtl
- toplevel: top_earlgrey_asic
+ toplevel: chip_earlgrey_asic
lint:
<<: *default_target
@@ -68,8 +68,8 @@
default_tool: icarus
parameters:
- SYNTHESIS=true
- toplevel: top_earlgrey_asic
+ toplevel: chip_earlgrey_asic
formal:
<<: *default_target
- toplevel: top_earlgrey_asic
+ toplevel: chip_earlgrey_asic
diff --git a/hw/top_earlgrey/top_earlgrey_nexysvideo.core b/hw/top_earlgrey/chip_earlgrey_nexysvideo.core
similarity index 92%
rename from hw/top_earlgrey/top_earlgrey_nexysvideo.core
rename to hw/top_earlgrey/chip_earlgrey_nexysvideo.core
index 658ab49..1eefe6b 100644
--- a/hw/top_earlgrey/top_earlgrey_nexysvideo.core
+++ b/hw/top_earlgrey/chip_earlgrey_nexysvideo.core
@@ -2,17 +2,17 @@
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:systems:top_earlgrey_nexysvideo:0.1"
+name: "lowrisc:systems:chip_earlgrey_nexysvideo:0.1"
description: "Earl Grey toplevel for the Nexys Video board"
filesets:
files_rtl_nexysvideo:
depend:
- lowrisc:systems:top_earlgrey:0.1
- lowrisc:systems:top_earlgrey_pkg
- - lowrisc:tool:top_earlgrey_nexysvideo_size_check
+ - lowrisc:tool:chip_earlgrey_nexysvideo_size_check
files:
- rtl/clkgen_xil7series.sv
- - rtl/autogen/top_earlgrey_nexysvideo.sv
+ - rtl/autogen/chip_earlgrey_nexysvideo.sv
file_type: systemVerilogSource
files_constraints:
@@ -58,7 +58,7 @@
default: &default_target
filesets:
- files_rtl_nexysvideo
- toplevel: top_earlgrey_nexysvideo
+ toplevel: chip_earlgrey_nexysvideo
synth:
default_tool: vivado
@@ -66,7 +66,7 @@
- files_rtl_nexysvideo
- files_constraints
- files_tcl
- toplevel: top_earlgrey_nexysvideo
+ toplevel: chip_earlgrey_nexysvideo
parameters:
- BootRomInitFile
- OtpCtrlMemInitFile
diff --git a/hw/top_earlgrey/top_earlgrey_verilator.cc b/hw/top_earlgrey/chip_earlgrey_verilator.cc
similarity index 92%
rename from hw/top_earlgrey/top_earlgrey_verilator.cc
rename to hw/top_earlgrey/chip_earlgrey_verilator.cc
index b5b90a8..7b5856a 100644
--- a/hw/top_earlgrey/top_earlgrey_verilator.cc
+++ b/hw/top_earlgrey/chip_earlgrey_verilator.cc
@@ -10,13 +10,13 @@
#include "verilator_sim_ctrl.h"
int main(int argc, char **argv) {
- top_earlgrey_verilator top;
+ chip_earlgrey_verilator top;
VerilatorMemUtil memutil;
VerilatorSimCtrl &simctrl = VerilatorSimCtrl::GetInstance();
simctrl.SetTop(&top, &top.clk_i, &top.rst_ni,
VerilatorSimCtrlFlags::ResetPolarityNegative);
- std::string top_scope("TOP.top_earlgrey_verilator.top_earlgrey");
+ std::string top_scope("TOP.chip_earlgrey_verilator.top_earlgrey");
std::string ram1p_adv_scope(
"u_prim_ram_1p_adv.u_mem."
"gen_generic.u_impl_generic");
@@ -45,7 +45,7 @@
// release clocks to the entire design. This allows for synchronous resets
// to appropriately propagate.
// The reset duration must be appropriately sized to the divider for clk_aon
- // in top_earlgrey_verilator.sv. It must be at least 2 cycles of clk_aon.
+ // in chip_earlgrey_verilator.sv. It must be at least 2 cycles of clk_aon.
simctrl.SetInitialResetDelay(500);
simctrl.SetResetDuration(10);
diff --git a/hw/top_earlgrey/top_earlgrey_verilator.core b/hw/top_earlgrey/chip_earlgrey_verilator.core
similarity index 92%
rename from hw/top_earlgrey/top_earlgrey_verilator.core
rename to hw/top_earlgrey/chip_earlgrey_verilator.core
index bf3166b..a54d0ce 100644
--- a/hw/top_earlgrey/top_earlgrey_verilator.core
+++ b/hw/top_earlgrey/chip_earlgrey_verilator.core
@@ -2,7 +2,7 @@
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:systems:top_earlgrey_verilator:0.1"
+name: "lowrisc:systems:chip_earlgrey_verilator:0.1"
description: "Earl Grey toplevel for simulation with Verilator"
filesets:
files_sim_verilator:
@@ -24,8 +24,8 @@
- lowrisc:prim:clock_div
files:
- - rtl/top_earlgrey_verilator.sv: { file_type: systemVerilogSource }
- - top_earlgrey_verilator.cc: { file_type: cppSource }
+ - rtl/chip_earlgrey_verilator.sv: { file_type: systemVerilogSource }
+ - chip_earlgrey_verilator.cc: { file_type: cppSource }
parameters:
# For value definition, please see ip/prim/rtl/prim_pkg.sv
@@ -75,7 +75,7 @@
default: &default_target
filesets:
- files_sim_verilator
- toplevel: top_earlgrey_verilator
+ toplevel: chip_earlgrey_verilator
sim:
parameters:
@@ -94,7 +94,7 @@
default_tool: verilator
filesets:
- files_sim_verilator
- toplevel: top_earlgrey_verilator
+ toplevel: chip_earlgrey_verilator
tools:
verilator:
mode: cc
@@ -108,7 +108,7 @@
- '--trace-params'
- '--trace-max-array 1024'
- '--unroll-count 512'
- - '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DVL_USER_STOP -DTOPLEVEL_NAME=top_earlgrey_verilator -g"'
+ - '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DVL_USER_STOP -DTOPLEVEL_NAME=chip_earlgrey_verilator -g"'
- '-LDFLAGS "-pthread -lutil -lelf"'
- '-Wall'
# Execute simulation with four threads by default, which works best
diff --git a/hw/top_earlgrey/doc/_index.md b/hw/top_earlgrey/doc/_index.md
index c9420c7..368a14c 100644
--- a/hw/top_earlgrey/doc/_index.md
+++ b/hw/top_earlgrey/doc/_index.md
@@ -63,7 +63,7 @@
It should first be **NOTED** that there is some subtlety on the notion of hierarchy within the top level.
There is netlist automation to create the module `top_earlgrey` as indicated in sections of this specification that follow.
**On top** of that module, hierarchically in the repo, are top level instantiation targets directed towards a particular use case.
-This includes `top_earlgrey_nexsysvideo` for use in FPGA, and `top_earlgrey_asic` for use (eventually) in a silicon implementation.
+This includes `chip_earlgrey_nexsysvideo` for use in FPGA, and `chip_earlgrey_asic` for use (eventually) in a silicon implementation.
These top level targets will include the actual pads as needed by the target platform.
At the time of this writing the two are not in perfect synchronization, but the intention will be for them to be as identical as possible.
Where appropriate, including the block diagram below, notes will be provided where the hierarchy subtleties are explained.
@@ -77,12 +77,12 @@
In this diagram, the instantiation of the Ibex processor and all of the memories and comportable IPs are shown.
The IO shown at this level are the internal signals between the IP and the pads instantiated at the target top level netlist.
-In the block diagram below, the target netlist `top_earlgrey_nexsysvideo` is shown, including the FPGA pad names created.
+In the block diagram below, the target netlist `chip_earlgrey_nexsysvideo` is shown, including the FPGA pad names created.
-
+
In this diagram, pads for clock and reset are shown, as well as pads for JTAG, SPI device, UART, and GPIO.
-In this platform, at the moment, the logic for the JTAG and the SPI device are multiplexed within `top_earlgrey_nexsysvideo`.
+In this platform, at the moment, the logic for the JTAG and the SPI device are multiplexed within `chip_earlgrey_nexsysvideo`.
This is done for ease of programming by the external host.
In addition, at the moment, the UART pins and GPIO pins are separated out from the multipurpose `MIO` pins.
This will change as software and scripting matures and pin selection is defined more efficiently.
@@ -114,7 +114,7 @@
| `mio_out_o[31:0]` | output | Multiplexible output pins (currently only connected to GPIO) |
| `mio_oe_o[31:0]` | output | Multiplexible output enables (currently only connected to GPIO) |
-Below are the hardware interfaces of the FPGA target `top_earlgrey_nexsysvideo` netlist.
+Below are the hardware interfaces of the FPGA target `chip_earlgrey_nexsysvideo` netlist.
| Signal Name | Direction | Description |
| --- | --- | --- |
diff --git a/hw/top_earlgrey/doc/top_earlgrey_nexsysvideo_block_diagram.svg b/hw/top_earlgrey/doc/chip_earlgrey_nexsysvideo_block_diagram.svg
similarity index 100%
rename from hw/top_earlgrey/doc/top_earlgrey_nexsysvideo_block_diagram.svg
rename to hw/top_earlgrey/doc/chip_earlgrey_nexsysvideo_block_diagram.svg
diff --git a/hw/top_earlgrey/doc/dv/index.md b/hw/top_earlgrey/doc/dv/index.md
index 5c34b16..4e5fa7d 100644
--- a/hw/top_earlgrey/doc/dv/index.md
+++ b/hw/top_earlgrey/doc/dv/index.md
@@ -31,7 +31,7 @@
### Top level testbench
Top level testbench is located at `hw/ip/top_earlgrey/dv/tb/tb.sv`.
-It instantiates the `top_earlgrey` DUT module `hw/top_earlgrey/rtl/top_earlgrey_asic.sv`.
+It instantiates the `top_earlgrey` DUT module `hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv`.
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`:
* [Clock and reset interface]({{< relref "hw/dv/sv/common_ifs" >}})
* Main clock as well as USB clock
diff --git a/hw/top_earlgrey/dv/chip_sim.core b/hw/top_earlgrey/dv/chip_sim.core
index 8314221..7073696 100644
--- a/hw/top_earlgrey/dv/chip_sim.core
+++ b/hw/top_earlgrey/dv/chip_sim.core
@@ -7,7 +7,7 @@
filesets:
files_rtl:
depend:
- - lowrisc:systems:top_earlgrey_asic
+ - lowrisc:systems:chip_earlgrey_asic
- lowrisc:ibex:ibex_tracer
files_dv:
diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
index 2a834cc..1b588ac 100644
--- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson
+++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
@@ -6,7 +6,7 @@
name: chip
// Top level dut name (sv module).
- dut: top_earlgrey_asic
+ dut: chip_earlgrey_asic
// Top level testbench name (sv module).
tb: tb
diff --git a/hw/top_earlgrey/dv/cov/chip_assert_cover.cfg b/hw/top_earlgrey/dv/cov/chip_assert_cover.cfg
index 3aadf02..b4aa302 100644
--- a/hw/top_earlgrey/dv/cov/chip_assert_cover.cfg
+++ b/hw/top_earlgrey/dv/cov/chip_assert_cover.cfg
@@ -4,7 +4,7 @@
// Include assertions within these modules.
+module tb
-+module top_earlgrey_asic
++module chip_earlgrey_asic
+module top_earlgrey
+module rv_core_ibex
diff --git a/hw/top_earlgrey/dv/cov/chip_cover.cfg b/hw/top_earlgrey/dv/cov/chip_cover.cfg
index abef508..a576efd 100644
--- a/hw/top_earlgrey/dv/cov/chip_cover.cfg
+++ b/hw/top_earlgrey/dv/cov/chip_cover.cfg
@@ -8,7 +8,7 @@
// Include port toggles of all IOs at these hierarchies.
begin tgl(portsonly)
- +module top_earlgrey_asic
+ +module chip_earlgrey_asic
+module padring
+moduletree top_earlgrey 2
+moduletree rv_core_ibex 2
@@ -16,7 +16,7 @@
// Enable full coverage collection on these modules to cover the glue logic.
begin line+cond+fsm+branch
- +module top_earlgrey_asic
+ +module chip_earlgrey_asic
+module top_earlgrey
+module rv_core_ibex
end
diff --git a/hw/top_earlgrey/dv/tb/tb.sv b/hw/top_earlgrey/dv/tb/tb.sv
index a369458..146177a 100644
--- a/hw/top_earlgrey/dv/tb/tb.sv
+++ b/hw/top_earlgrey/dv/tb/tb.sv
@@ -87,7 +87,7 @@
// TODO: the external clk is currently not connected.
// We will need to feed this in via a muxed pin, once that function implemented.
- top_earlgrey_asic dut (
+ chip_earlgrey_asic dut (
// Clock and Reset
.POR_N(rst_n),
// Bank A (VIOA domain)
diff --git a/hw/top_earlgrey/dv/verilator_sim_cfg.hjson b/hw/top_earlgrey/dv/verilator_sim_cfg.hjson
index 44f6e80..e33e694 100644
--- a/hw/top_earlgrey/dv/verilator_sim_cfg.hjson
+++ b/hw/top_earlgrey/dv/verilator_sim_cfg.hjson
@@ -3,7 +3,7 @@
// SPDX-License-Identifier: Apache-2.0
{
// Name of the sim cfg - typically same as the name of the DUT.
- name: top_earlgrey_verilator
+ name: chip_earlgrey_verilator
// Top level dut name (sv module).
dut: "{name}"
diff --git a/hw/top_earlgrey/formal/conn_csvs/top_earlgrey_conn.csv b/hw/top_earlgrey/formal/conn_csvs/top_earlgrey_conn.csv
index 3a737d9..93f4ab6 100644
--- a/hw/top_earlgrey/formal/conn_csvs/top_earlgrey_conn.csv
+++ b/hw/top_earlgrey/formal/conn_csvs/top_earlgrey_conn.csv
@@ -2,7 +2,7 @@
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
#
-# TODO: use top_earlgrey_asic once the ast compile error fixed
+# TODO: use chip_earlgrey_asic once the ast compile error fixed
,NAME,SRC BLOCK,SRC SIGNAL,DEST BLOCK,DEST SIGNAL,,,,,,
diff --git a/hw/top_earlgrey/lint/top_earlgrey.waiver b/hw/top_earlgrey/lint/top_earlgrey.waiver
index cdb1655..6b4ab62 100644
--- a/hw/top_earlgrey/lint/top_earlgrey.waiver
+++ b/hw/top_earlgrey/lint/top_earlgrey.waiver
@@ -22,7 +22,7 @@
-comment "Divided clocks go through prim_clock_div, which use muxes for scan bypass and clock step down"
# Combo loops through uart loopback can be ignored
-waive -rules {COMBO_LOOP} -location {top_earlgrey_asic.sv} -regexp {'tx' driven in module 'uart_core' by 'rx' at uart_core.sv} \
+waive -rules {COMBO_LOOP} -location {chip_earlgrey_asic.sv} -regexp {'tx' driven in module 'uart_core' by 'rx' at uart_core.sv} \
-comment "there is technically a loopback path through uart, however RX / TX should never be configured to the same pin"
waive -rules {SAME_NAME_TYPE} -location {*} -regexp {.*} \
diff --git a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson
index ba4bb9e..4da5764 100644
--- a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson
+++ b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson
@@ -271,10 +271,10 @@
}
]
},
- { name: top_earlgrey_asic
- fusesoc_core: lowrisc:systems:top_earlgrey_asic
+ { name: chip_earlgrey_asic
+ fusesoc_core: lowrisc:systems:chip_earlgrey_asic
import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
- rel_path: "hw/top_earlgrey_asic/lint/{tool}"
+ rel_path: "hw/chip_earlgrey_asic/lint/{tool}"
overrides: [
{
name: design_level
@@ -283,15 +283,15 @@
]
},
// these two currently cause compilation issues in AscentLint
- //{ name: top_earlgrey_nexysvideo
- // fusesoc_core: lowrisc:systems:top_earlgrey_nexysvideo
+ //{ name: chip_earlgrey_nexysvideo
+ // fusesoc_core: lowrisc:systems:chip_earlgrey_nexysvideo
// import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
- // rel_path: "hw/top_earlgrey_nexysvideo/lint/{tool}"
+ // rel_path: "hw/chip_earlgrey_nexysvideo/lint/{tool}"
//},
- //{ name: top_earlgrey_verilator
- // fusesoc_core: lowrisc:systems:top_earlgrey_verilator
+ //{ name: chip_earlgrey_verilator
+ // fusesoc_core: lowrisc:systems:chip_earlgrey_verilator
// import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
- // rel_path: "hw/top_earlgrey_verilator/lint/{tool}"
+ // rel_path: "hw/chip_earlgrey_verilator/lint/{tool}"
//},
]
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_asic.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
similarity index 99%
rename from hw/top_earlgrey/rtl/autogen/top_earlgrey_asic.sv
rename to hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
index f48cebc..7f70786 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_asic.sv
+++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
@@ -9,8 +9,7 @@
// -o hw/top_earlgrey/ \
// --rnd_cnst_seed 4881560218908238235
-// TODO: change the naming to chip_earlgrey_asic
-module top_earlgrey_asic (
+module chip_earlgrey_asic (
// Dedicated Pads
inout POR_N, // Manual Pad
inout SPI_HOST_D0, // Dedicated Pad for spi_host0_sd
@@ -1188,5 +1187,4 @@
-// TODO: change the naming to chip_
-endmodule : top_earlgrey_asic
+endmodule : chip_earlgrey_asic
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_nexysvideo.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv
similarity index 99%
rename from hw/top_earlgrey/rtl/autogen/top_earlgrey_nexysvideo.sv
rename to hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv
index 7eaa514..9e5a49d 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_nexysvideo.sv
+++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv
@@ -9,8 +9,7 @@
// -o hw/top_earlgrey/ \
// --rnd_cnst_seed 4881560218908238235
-// TODO: change the naming to chip_earlgrey_nexysvideo
-module top_earlgrey_nexysvideo #(
+module chip_earlgrey_nexysvideo #(
// Path to a VMEM file containing the contents of the boot ROM, which will be
// baked into the FPGA bitstream.
parameter BootRomInitFile = "boot_rom_fpga_nexysvideo.32.vmem",
@@ -809,5 +808,4 @@
-// TODO: change the naming to chip_
-endmodule : top_earlgrey_nexysvideo
+endmodule : chip_earlgrey_nexysvideo
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv b/hw/top_earlgrey/rtl/chip_earlgrey_verilator.sv
similarity index 99%
rename from hw/top_earlgrey/rtl/top_earlgrey_verilator.sv
rename to hw/top_earlgrey/rtl/chip_earlgrey_verilator.sv
index 1f6ac0c..f40a51b 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_verilator.sv
+++ b/hw/top_earlgrey/rtl/chip_earlgrey_verilator.sv
@@ -2,7 +2,7 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-module top_earlgrey_verilator (
+module chip_earlgrey_verilator (
// Clock and Reset
input clk_i,
input rst_ni
@@ -354,4 +354,4 @@
`undef RV_CORE_IBEX
`undef SIM_SRAM_IF
-endmodule
+endmodule : chip_earlgrey_verilator
diff --git a/hw/top_earlgrey/syn/top_earlgrey_asic_syn_cfg.hjson b/hw/top_earlgrey/syn/chip_earlgrey_asic_syn_cfg.hjson
similarity index 92%
rename from hw/top_earlgrey/syn/top_earlgrey_asic_syn_cfg.hjson
rename to hw/top_earlgrey/syn/chip_earlgrey_asic_syn_cfg.hjson
index 0a93108..f3909ed 100644
--- a/hw/top_earlgrey/syn/top_earlgrey_asic_syn_cfg.hjson
+++ b/hw/top_earlgrey/syn/chip_earlgrey_asic_syn_cfg.hjson
@@ -3,10 +3,10 @@
// SPDX-License-Identifier: Apache-2.0
{
// Top level dut name (sv module).
- name: top_earlgrey_asic
+ name: chip_earlgrey_asic
// Fusesoc core file used for building the file list.
- fusesoc_core: lowrisc:systems:top_earlgrey_asic:0.1
+ fusesoc_core: lowrisc:systems:chip_earlgrey_asic:0.1
import_cfgs: [// Project wide common synthesis config file
"{proj_root}/hw/syn/tools/dvsim/common_syn_cfg.hjson"]
diff --git a/hw/top_earlgrey/util/top_earlgrey_nexysvideo_size_check.core b/hw/top_earlgrey/util/chip_earlgrey_nexysvideo_size_check.core
similarity index 61%
rename from hw/top_earlgrey/util/top_earlgrey_nexysvideo_size_check.core
rename to hw/top_earlgrey/util/chip_earlgrey_nexysvideo_size_check.core
index 48ddab7..6f0bbff 100644
--- a/hw/top_earlgrey/util/top_earlgrey_nexysvideo_size_check.core
+++ b/hw/top_earlgrey/util/chip_earlgrey_nexysvideo_size_check.core
@@ -2,30 +2,30 @@
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:tool:top_earlgrey_nexysvideo_size_check"
+name: "lowrisc:tool:chip_earlgrey_nexysvideo_size_check"
description: "Check if design size has been reduced for nexysvideo target"
filesets:
- files_top_earlgrey_size_check:
+ files_chip_earlgrey_size_check:
files:
- - ./top_earlgrey_size_check.py : { copyto: util/top_earlgrey_size_check.py }
+ - ./chip_earlgrey_size_check.py : { copyto: util/chip_earlgrey_size_check.py }
scripts:
- top_earlgrey_size_check:
+ chip_earlgrey_size_check:
cmd:
- python3
- - util/top_earlgrey_size_check.py
+ - util/chip_earlgrey_size_check.py
- --target=nexysvideo
# TODO: Use this syntax once https://github.com/olofk/fusesoc/issues/353 is
# fixed. Remove the filesets from the default target, and also remove the
# copyto.
#filesets:
- # - top_earlgrey_size_check
+ # - chip_earlgrey_size_check
targets:
default:
filesets:
- - files_top_earlgrey_size_check
+ - files_chip_earlgrey_size_check
hooks:
pre_build:
- - top_earlgrey_size_check
+ - chip_earlgrey_size_check
diff --git a/hw/top_earlgrey/util/top_earlgrey_size_check.py b/hw/top_earlgrey/util/chip_earlgrey_size_check.py
similarity index 100%
rename from hw/top_earlgrey/util/top_earlgrey_size_check.py
rename to hw/top_earlgrey/util/chip_earlgrey_size_check.py
diff --git a/hw/top_earlgrey/util/opentitan_earlgrey_usbdev_pin_config_sim.sh b/hw/top_earlgrey/util/opentitan_earlgrey_usbdev_pin_config_sim.sh
index 5622e1f..b5a3232 100755
--- a/hw/top_earlgrey/util/opentitan_earlgrey_usbdev_pin_config_sim.sh
+++ b/hw/top_earlgrey/util/opentitan_earlgrey_usbdev_pin_config_sim.sh
@@ -4,7 +4,7 @@
# SPDX-License-Identifier: Apache-2.0
# Simulator executable
-VERILATOR=build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator
+VERILATOR=build/lowrisc_systems_chip_earlgrey_verilator_0.1/sim-verilator/Vchip_earlgrey_verilator
# Code to load
ROMCODE=build-bin/sw/device/boot_rom/boot_rom_sim_verilator.elf
diff --git a/hw/top_englishbreakfast/top_englishbreakfast_cw305.core b/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core
similarity index 94%
rename from hw/top_englishbreakfast/top_englishbreakfast_cw305.core
rename to hw/top_englishbreakfast/chip_englishbreakfast_cw305.core
index 3ce1f54..df59461 100644
--- a/hw/top_englishbreakfast/top_englishbreakfast_cw305.core
+++ b/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core
@@ -2,7 +2,7 @@
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:systems:top_englishbreakfast_cw305:0.1"
+name: "lowrisc:systems:chip_englishbreakfast_cw305:0.1"
description: "English Breakfast toplevel for the ChipWhisperer CW305 board"
filesets:
@@ -49,7 +49,7 @@
default: &default_target
filesets:
- files_rtl_cw305
- toplevel: top_englishbreakfast_cw305
+ toplevel: chip_englishbreakfast_cw305
synth:
default_tool: vivado
@@ -57,7 +57,7 @@
- files_rtl_cw305
- files_constraints
- files_tcl
- toplevel: top_englishbreakfast_cw305
+ toplevel: chip_englishbreakfast_cw305
parameters:
- BootRomInitFile
- PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx
diff --git a/hw/top_englishbreakfast/top_englishbreakfast_verilator.cc b/hw/top_englishbreakfast/chip_englishbreakfast_verilator.cc
similarity index 91%
rename from hw/top_englishbreakfast/top_englishbreakfast_verilator.cc
rename to hw/top_englishbreakfast/chip_englishbreakfast_verilator.cc
index 2cc99f2..c919a57 100644
--- a/hw/top_englishbreakfast/top_englishbreakfast_verilator.cc
+++ b/hw/top_englishbreakfast/chip_englishbreakfast_verilator.cc
@@ -9,14 +9,14 @@
#include "verilator_sim_ctrl.h"
int main(int argc, char **argv) {
- top_englishbreakfast_verilator top;
+ chip_englishbreakfast_verilator top;
VerilatorMemUtil memutil;
VerilatorSimCtrl &simctrl = VerilatorSimCtrl::GetInstance();
simctrl.SetTop(&top, &top.clk_i, &top.rst_ni,
VerilatorSimCtrlFlags::ResetPolarityNegative);
std::string top_scope(
- "TOP.top_englishbreakfast_verilator."
+ "TOP.chip_englishbreakfast_verilator."
"top_englishbreakfast");
std::string ram1p_adv_scope(
"u_prim_ram_1p_adv.u_mem."
@@ -37,7 +37,7 @@
memutil.RegisterMemoryArea("flash", 0x20000000u, &flash);
simctrl.RegisterExtension(&memutil);
- // see top_earlgrey_verilator.cc for justification and explanation
+ // see chip_earlgrey_verilator.cc for justification and explanation
simctrl.SetInitialResetDelay(500);
simctrl.SetResetDuration(10);
diff --git a/hw/top_englishbreakfast/top_englishbreakfast_verilator.core b/hw/top_englishbreakfast/chip_englishbreakfast_verilator.core
similarity index 91%
rename from hw/top_englishbreakfast/top_englishbreakfast_verilator.core
rename to hw/top_englishbreakfast/chip_englishbreakfast_verilator.core
index 53508a7..1ded494 100644
--- a/hw/top_englishbreakfast/top_englishbreakfast_verilator.core
+++ b/hw/top_englishbreakfast/chip_englishbreakfast_verilator.core
@@ -2,7 +2,7 @@
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:systems:top_englishbreakfast_verilator:0.1"
+name: "lowrisc:systems:chip_englishbreakfast_verilator:0.1"
description: "English Breakfast toplevel for simulation with Verilator"
filesets:
files_sim_verilator:
@@ -24,8 +24,8 @@
- lowrisc:prim:clock_div
files:
- - rtl/top_englishbreakfast_verilator.sv: { file_type: systemVerilogSource }
- - top_englishbreakfast_verilator.cc: { file_type: cppSource }
+ - rtl/chip_englishbreakfast_verilator.sv: { file_type: systemVerilogSource }
+ - chip_englishbreakfast_verilator.cc: { file_type: cppSource }
parameters:
# For value definition, please see ip/prim/rtl/prim_pkg.sv
@@ -71,7 +71,7 @@
default: &default_target
filesets:
- files_sim_verilator
- toplevel: top_englishbreakfast_verilator
+ toplevel: chip_englishbreakfast_verilator
sim:
parameters:
@@ -86,7 +86,7 @@
default_tool: verilator
filesets:
- files_sim_verilator
- toplevel: top_englishbreakfast_verilator
+ toplevel: chip_englishbreakfast_verilator
tools:
verilator:
mode: cc
@@ -100,7 +100,7 @@
- '--trace-params'
- '--trace-max-array 1024'
- '--unroll-count 512'
- - '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DVL_USER_STOP -DTOPLEVEL_NAME=top_englishbreakfast_verilator -g"'
+ - '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DVL_USER_STOP -DTOPLEVEL_NAME=chip_englishbreakfast_verilator -g"'
- '-LDFLAGS "-pthread -lutil -lelf"'
- '-Wall'
# Execute simulation with four threads by default, which works best
diff --git a/hw/top_englishbreakfast/rtl/top_englishbreakfast_verilator.sv b/hw/top_englishbreakfast/rtl/chip_englishbreakfast_verilator.sv
similarity index 99%
rename from hw/top_englishbreakfast/rtl/top_englishbreakfast_verilator.sv
rename to hw/top_englishbreakfast/rtl/chip_englishbreakfast_verilator.sv
index 30b8343..64893c7 100644
--- a/hw/top_englishbreakfast/rtl/top_englishbreakfast_verilator.sv
+++ b/hw/top_englishbreakfast/rtl/chip_englishbreakfast_verilator.sv
@@ -2,7 +2,7 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-module top_englishbreakfast_verilator (
+module chip_englishbreakfast_verilator (
// Clock and Reset
input clk_i,
input rst_ni
@@ -351,4 +351,4 @@
`undef RV_CORE_IBEX
`undef SIM_SRAM_IF
-endmodule
+endmodule : chip_englishbreakfast_verilator
diff --git a/sw/device/lib/arch/device_sim_verilator.c b/sw/device/lib/arch/device_sim_verilator.c
index cfd4ef0..7cab9ce 100644
--- a/sw/device/lib/arch/device_sim_verilator.c
+++ b/sw/device/lib/arch/device_sim_verilator.c
@@ -12,7 +12,7 @@
const device_type_t kDeviceType = kDeviceSimVerilator;
// Changes to the clock frequency or UART baud rate must also be reflected at
-// `hw/top_earlgrey/rtl/top_earlgrey_verilator.sv` and
+// `hw/top_earlgrey/rtl/chip_earlgrey_verilator.sv` and
// `test/systemtest/earlgrey/test_sim_verilator.py`.
const uint64_t kClockFreqCpuHz = 500 * 1000; // 500kHz
@@ -22,7 +22,7 @@
const uint64_t kUartBaudrate = 7200;
-// Defined in `hw/top_earlgrey/top_earlgrey_verilator.core`
+// Defined in `hw/top_earlgrey/chip_earlgrey_verilator.core`
const uintptr_t kDeviceTestStatusAddress = 0x30000000;
const uintptr_t kDeviceLogBypassUartAddress = 0;
diff --git a/sw/device/tests/dif/dif_gpio_smoketest.c b/sw/device/tests/dif/dif_gpio_smoketest.c
index 7f9adb5..6f35acc 100644
--- a/sw/device/tests/dif/dif_gpio_smoketest.c
+++ b/sw/device/tests/dif/dif_gpio_smoketest.c
@@ -30,9 +30,9 @@
* Pins to be tested.
*
* This test only uses pins 0-15 to be compatible with both FPGA and DV:
- * - On the nexys video board (top_earlgrey_nexysvideo.sv), pins 20-23 are
+ * - On the nexys video board (chip_earlgrey_nexysvideo.sv), pins 20-23 are
* grounded and pins 16-19 are reserved for JTAG, while
- * - On the OpenTitan ASIC (top_earlgrey_asic.sv), pins 20-31 are grounded and
+ * - On the OpenTitan ASIC (chip_earlgrey_asic.sv), pins 20-31 are grounded and
* pins 16-19 are reserved for JTAG.
*/
static const uint32_t kGpioMask = 0x0000FFFF;
diff --git a/sw/vendor/patches/riscv_compliance/0001-Add-configurable-trap-alignment-and-entry-point-to-p.patch b/sw/vendor/patches/riscv_compliance/0001-Add-configurable-trap-alignment-and-entry-point-to-p.patch
index e963d16..f454667 100644
--- a/sw/vendor/patches/riscv_compliance/0001-Add-configurable-trap-alignment-and-entry-point-to-p.patch
+++ b/sw/vendor/patches/riscv_compliance/0001-Add-configurable-trap-alignment-and-entry-point-to-p.patch
@@ -1,7 +1,7 @@
From e8b82ff045fca264917a7c5539bfcbe8ed22b7a0 Mon Sep 17 00:00:00 2001
From: Greg Chadwick <gac@lowrisc.org>
Date: Wed, 15 Apr 2020 15:45:31 +0100
-Subject: [PATCH 1/4] Add configurable trap alignment and entry point to p
+Subject: [PATCH 1/5] Add configurable trap alignment and entry point to p
test-env
diff --git a/sw/vendor/patches/riscv_compliance/0002-Add-OpenTitan-target.patch b/sw/vendor/patches/riscv_compliance/0002-Add-OpenTitan-target.patch
index 14f2e3e..5a2e2ed 100644
--- a/sw/vendor/patches/riscv_compliance/0002-Add-OpenTitan-target.patch
+++ b/sw/vendor/patches/riscv_compliance/0002-Add-OpenTitan-target.patch
@@ -1,7 +1,7 @@
From 12485c998481c4414e157a7b6d475c2c118fce77 Mon Sep 17 00:00:00 2001
From: Greg Chadwick <gac@lowrisc.org>
Date: Wed, 15 Apr 2020 15:44:54 +0100
-Subject: [PATCH 2/4] Add OpenTitan target
+Subject: [PATCH 2/5] Add OpenTitan target
diff --git a/Makefile b/Makefile
diff --git a/sw/vendor/patches/riscv_compliance/0003-Remove-tests-that-do-not-pass-on-OpenTitan.patch b/sw/vendor/patches/riscv_compliance/0003-Remove-tests-that-do-not-pass-on-OpenTitan.patch
index 2bc9391..dbcdb3a 100644
--- a/sw/vendor/patches/riscv_compliance/0003-Remove-tests-that-do-not-pass-on-OpenTitan.patch
+++ b/sw/vendor/patches/riscv_compliance/0003-Remove-tests-that-do-not-pass-on-OpenTitan.patch
@@ -1,7 +1,7 @@
From 238c8583aa41156429c890e9761979007fae8be0 Mon Sep 17 00:00:00 2001
From: Greg Chadwick <gac@lowrisc.org>
Date: Wed, 15 Apr 2020 18:39:08 +0100
-Subject: [PATCH 3/4] Remove tests that do not pass on OpenTitan
+Subject: [PATCH 3/5] Remove tests that do not pass on OpenTitan
diff --git a/riscv-test-suite/rv32i/Makefrag b/riscv-test-suite/rv32i/Makefrag
diff --git a/sw/vendor/patches/riscv_compliance/0004-otp-img-Add-OTP-image-preload-switch-to-RUN_TARGET.patch b/sw/vendor/patches/riscv_compliance/0004-otp-img-Add-OTP-image-preload-switch-to-RUN_TARGET.patch
index 532554f..969b225 100644
--- a/sw/vendor/patches/riscv_compliance/0004-otp-img-Add-OTP-image-preload-switch-to-RUN_TARGET.patch
+++ b/sw/vendor/patches/riscv_compliance/0004-otp-img-Add-OTP-image-preload-switch-to-RUN_TARGET.patch
@@ -1,7 +1,7 @@
From 74393f086a0d36070152f828a07f015ede7198aa Mon Sep 17 00:00:00 2001
From: Michael Schaffner <msf@google.com>
Date: Tue, 23 Feb 2021 18:30:20 -0800
-Subject: [PATCH 4/4] [otp-img] Add OTP image preload switch to RUN_TARGET
+Subject: [PATCH 4/5] [otp-img] Add OTP image preload switch to RUN_TARGET
Signed-off-by: Michael Schaffner <msf@google.com>
diff --git a/sw/vendor/patches/riscv_compliance/0005-verilator-Rename-top_-chip_.patch b/sw/vendor/patches/riscv_compliance/0005-verilator-Rename-top_-chip_.patch
new file mode 100644
index 0000000..f782cdc
--- /dev/null
+++ b/sw/vendor/patches/riscv_compliance/0005-verilator-Rename-top_-chip_.patch
@@ -0,0 +1,33 @@
+From c595f9723c1196f54ad04d9ee91ced7ca3c7acae Mon Sep 17 00:00:00 2001
+From: Michael Schaffner <msf@google.com>
+Date: Wed, 31 Mar 2021 16:23:34 -0700
+Subject: [PATCH 5/5] [verilator] Rename top_ -> chip_
+
+Signed-off-by: Michael Schaffner <msf@google.com>
+
+diff --git a/riscv-target/opentitan/README.md b/riscv-target/opentitan/README.md
+index 353a9b3..a942788 100644
+--- a/riscv-target/opentitan/README.md
++++ b/riscv-target/opentitan/README.md
+@@ -24,7 +24,7 @@ $ export OT_FPGA_UART=/dev/tty*
+ ```
+
+ By default, the test assumes there exists a valid Verilator build at
+-`${REPO_TOP}/build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator`.
++`${REPO_TOP}/build/lowrisc_systems_chip_earlgrey_verilator_0.1/sim-verilator/Vchip_earlgrey_verilator`.
+ If your Verilator build is at a different location, please set that as well when
+ running with Verilator.
+
+diff --git a/riscv-target/opentitan/device/rv32imc/Makefile.include b/riscv-target/opentitan/device/rv32imc/Makefile.include
+index ca47ee0..570e0be 100644
+--- a/riscv-target/opentitan/device/rv32imc/Makefile.include
++++ b/riscv-target/opentitan/device/rv32imc/Makefile.include
+@@ -11,7 +11,7 @@ OT_FPGA_UART ?=
+ OT_TARGET ?= fpga_nexysvideo
+ LDSCRIPT = $(OT_ROOT)/sw/device/exts/common/flash_link.ld
+ DEFINES = $(CARG) -DPRIV_MISA_S=0 -DPRIV_MISA_U=0 -DRVTEST_ENTRY=_rvc_start -DTRAPALIGN=8
+-TARGET_SIM ?= $(OT_ROOT)/build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator
++TARGET_SIM ?= $(OT_ROOT)/build/lowrisc_systems_chip_earlgrey_verilator_0.1/sim-verilator/Vchip_earlgrey_verilator
+
+ COMPLIANCE_LIB_EXPORT = sw/device/riscv_compliance_support/riscv_compliance_support_export_$(OT_TARGET)
+ COMPLIANCE_LIB = ot_riscv_compliance_support_$(OT_TARGET)
diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/README.md b/sw/vendor/riscv_compliance/riscv-target/opentitan/README.md
index 353a9b3..a942788 100644
--- a/sw/vendor/riscv_compliance/riscv-target/opentitan/README.md
+++ b/sw/vendor/riscv_compliance/riscv-target/opentitan/README.md
@@ -24,7 +24,7 @@
```
By default, the test assumes there exists a valid Verilator build at
-`${REPO_TOP}/build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator`.
+`${REPO_TOP}/build/lowrisc_systems_chip_earlgrey_verilator_0.1/sim-verilator/Vchip_earlgrey_verilator`.
If your Verilator build is at a different location, please set that as well when
running with Verilator.
diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include b/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include
index ca47ee0..570e0be 100644
--- a/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include
+++ b/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include
@@ -11,7 +11,7 @@
OT_TARGET ?= fpga_nexysvideo
LDSCRIPT = $(OT_ROOT)/sw/device/exts/common/flash_link.ld
DEFINES = $(CARG) -DPRIV_MISA_S=0 -DPRIV_MISA_U=0 -DRVTEST_ENTRY=_rvc_start -DTRAPALIGN=8
-TARGET_SIM ?= $(OT_ROOT)/build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator
+TARGET_SIM ?= $(OT_ROOT)/build/lowrisc_systems_chip_earlgrey_verilator_0.1/sim-verilator/Vchip_earlgrey_verilator
COMPLIANCE_LIB_EXPORT = sw/device/riscv_compliance_support/riscv_compliance_support_export_$(OT_TARGET)
COMPLIANCE_LIB = ot_riscv_compliance_support_$(OT_TARGET)
diff --git a/test/systemtest/earlgrey/test_fpga_nexysvideo.py b/test/systemtest/earlgrey/test_fpga_nexysvideo.py
index 77f6374..52e8582 100644
--- a/test/systemtest/earlgrey/test_fpga_nexysvideo.py
+++ b/test/systemtest/earlgrey/test_fpga_nexysvideo.py
@@ -71,7 +71,7 @@
localconf_nexysvideo):
""" A Nexys Video board flashed with an Earl Grey bitstream """
- bitstream = bin_dir / "hw/top_earlgrey/lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit"
+ bitstream = bin_dir / "hw/top_earlgrey/lowrisc_systems_chip_earlgrey_nexysvideo_0.1.bit"
assert bitstream.is_file(), ("Bitstream not found at %s." % str(bitstream))
cmd_pgm = [
diff --git a/test/systemtest/earlgrey/test_sim_verilator.py b/test/systemtest/earlgrey/test_sim_verilator.py
index 01e2370..00a69db 100644
--- a/test/systemtest/earlgrey/test_sim_verilator.py
+++ b/test/systemtest/earlgrey/test_sim_verilator.py
@@ -279,7 +279,7 @@
Self-checking applications are expected to return PASS or FAIL in the end.
"""
- sim_path = bin_dir / "hw/top_earlgrey/Vtop_earlgrey_verilator"
+ sim_path = bin_dir / "hw/top_earlgrey/Vchip_earlgrey_verilator"
rom_elf_path = bin_dir / "sw/device/boot_rom/boot_rom_sim_verilator.elf"
otp_img_path = bin_dir / "sw/device/otp_img/otp_img_sim_verilator.vmem"
@@ -303,7 +303,7 @@
Self-checking applications are expected to return PASS or FAIL in the end.
"""
- sim_path = bin_dir / "hw/top_earlgrey/Vtop_earlgrey_verilator"
+ sim_path = bin_dir / "hw/top_earlgrey/Vchip_earlgrey_verilator"
rom_elf_path = bin_dir / "sw/device/silicon_creator/mask_rom/mask_rom_sim_verilator.elf"
otp_img_path = bin_dir / "sw/device/otp_img/otp_img_sim_verilator.vmem"
@@ -322,7 +322,7 @@
def test_spiflash(tmp_path, bin_dir):
""" Load a single application to the Verilator simulation using spiflash """
- sim_path = bin_dir / "hw/top_earlgrey/Vtop_earlgrey_verilator"
+ sim_path = bin_dir / "hw/top_earlgrey/Vchip_earlgrey_verilator"
rom_elf_path = bin_dir / "sw/device/boot_rom/boot_rom_sim_verilator.elf"
otp_img_path = bin_dir / "sw/device/otp_img/otp_img_sim_verilator.vmem"
@@ -352,7 +352,7 @@
with the core or the system (bus) is performed.
"""
# Run a simulation (bootrom only, no app beyond that)
- sim_path = bin_dir / "hw/top_earlgrey/Vtop_earlgrey_verilator"
+ sim_path = bin_dir / "hw/top_earlgrey/Vchip_earlgrey_verilator"
rom_elf_path = bin_dir / "sw/device/boot_rom/boot_rom_sim_verilator.elf"
otp_img_path = bin_dir / "sw/device/otp_img/otp_img_sim_verilator.vmem"
diff --git a/test/systemtest/utils.py b/test/systemtest/utils.py
index 250392d..bf10036 100644
--- a/test/systemtest/utils.py
+++ b/test/systemtest/utils.py
@@ -511,7 +511,7 @@
"""
# Example of a full prefix to be matched:
- # 1629002: (../src/lowrisc_dv_sw_test_status_0/sw_test_status_if.sv:42) [TOP.top_earlgrey_verilator.u_sw_test_status_if]
+ # 1629002: (../src/lowrisc_dv_sw_test_status_0/sw_test_status_if.sv:42) [TOP.chip_earlgrey_verilator.u_sw_test_status_if]
pattern = r'\d+: \(.+/sw_test_status_if\.sv:\d+\) \[TOP\..+\] '
if isinstance(line, bytes):
return re.sub(bytes(pattern, encoding='utf-8'), b'', line)
diff --git a/util/fpga/README.md b/util/fpga/README.md
index dab4314..29af287 100644
--- a/util/fpga/README.md
+++ b/util/fpga/README.md
@@ -16,7 +16,7 @@
```
Updated output bitfile located : at the same place as raw vivado bitfile @
-`build/lowrisc_systems_top_earlgrey_nexysvideo_0.1/synth-vivado/lowrisc_systems_top_earlgrey_nexysvideo_0.1.splice.bit`
+`build/lowrisc_systems_chip_earlgrey_nexysvideo_0.1/synth-vivado/lowrisc_systems_chip_earlgrey_nexysvideo_0.1.splice.bit`
This directory contains following files:
diff --git a/util/fpga/splice_nexysvideo.sh b/util/fpga/splice_nexysvideo.sh
index 98d9990..2b4975a 100755
--- a/util/fpga/splice_nexysvideo.sh
+++ b/util/fpga/splice_nexysvideo.sh
@@ -10,11 +10,11 @@
# ./util/fpga/splice_nexysvideo.sh
# Updated bitfile located at the same place as raw vivado bitfile at
-# $REPO_TOP/build/lowrisc_systems_top_earlgrey_nexysvideo_0.1/synth-vivado/
-# lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
+# $REPO_TOP/build/lowrisc_systems_chip_earlgrey_nexysvideo_0.1/synth-vivado/
+# lowrisc_systems_chip_earlgrey_nexysvideo_0.1.bit
# A copy of the original bitfile is created at
-# $REPO_TOP/build/lowrisc_systems_top_earlgrey_nexysvideo_0.1/synth-vivado/
-# lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit.orig
+# $REPO_TOP/build/lowrisc_systems_chip_earlgrey_nexysvideo_0.1/synth-vivado/
+# lowrisc_systems_chip_earlgrey_nexysvideo_0.1.bit.orig
set -e
. util/build_consts.sh
@@ -23,8 +23,8 @@
TARGET_EXPORT="${TARGET_PREFIX}/boot_rom_export_fpga_nexysvideo"
TARGET="${BIN_DIR}/${TARGET_PREFIX}/boot_rom_fpga_nexysvideo"
-FPGA_BUILD_DIR=build/lowrisc_systems_top_earlgrey_nexysvideo_0.1/synth-vivado/
-FPGA_BIT_NAME=lowrisc_systems_top_earlgrey_nexysvideo_0.1
+FPGA_BUILD_DIR=build/lowrisc_systems_chip_earlgrey_nexysvideo_0.1/synth-vivado/
+FPGA_BIT_NAME=lowrisc_systems_chip_earlgrey_nexysvideo_0.1
./meson_init.sh
ninja -C "${OBJ_DIR}" "${TARGET_EXPORT}"
diff --git a/util/make_distribution.sh b/util/make_distribution.sh
index 014f711..86c335b 100755
--- a/util/make_distribution.sh
+++ b/util/make_distribution.sh
@@ -26,8 +26,8 @@
'sw/device/*.vmem'
'sw/otbn/*.elf'
'sw/host/spiflash/spiflash'
- 'hw/top_earlgrey/Vtop_earlgrey_verilator'
- 'hw/top_earlgrey/lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit'
+ 'hw/top_earlgrey/Vchip_earlgrey_verilator'
+ 'hw/top_earlgrey/lowrisc_systems_chip_earlgrey_nexysvideo_0.1.bit'
)
DIST_DIR="$OBJ_DIR/$OT_VERSION"
diff --git a/util/topgen-fusesoc.py b/util/topgen-fusesoc.py
index 09f7be0..b946b33 100644
--- a/util/topgen-fusesoc.py
+++ b/util/topgen-fusesoc.py
@@ -128,6 +128,12 @@
write_core(core_filepath, generated_core)
else:
+ nameparts = topname.split('_')
+ if nameparts[0] == 'top' and len(nameparts) > 1:
+ chipname = 'chip_' + '_'.join(nameparts[1:])
+ else:
+ chipname = topname
+
core_filepath = os.path.abspath('generated-topgen.core')
generated_core = {
'name': "lowrisc:systems:generated-topgen",
@@ -172,7 +178,7 @@
# TODO: this is not ideal. we should extract
# this info from the target configuration and
# possibly generate separate core files for this.
- 'rtl/autogen/%s_cw305.sv' % topname,
+ 'rtl/autogen/%s_cw305.sv' % chipname,
],
'file_type': 'systemVerilogSource'
},
diff --git a/util/topgen.py b/util/topgen.py
index 696c75e..6870c74 100755
--- a/util/topgen.py
+++ b/util/topgen.py
@@ -1094,11 +1094,10 @@
out_path / f"rtl/autogen/top_{topname}.sv",
gencmd=gencmd)
- # TODO: chiplevel renaming
# Multiple chip-levels (ASIC, FPGA, Verilator, etc)
for target in topcfg['targets']:
render_template(TOPGEN_TEMPLATE_PATH / "chiplevel.sv.tpl",
- out_path / f"rtl/autogen/top_{topname}_{target['name']}.sv",
+ out_path / f"rtl/autogen/chip_{topname}_{target['name']}.sv",
gencmd=gencmd,
target=target)
diff --git a/util/topgen/templates/chiplevel.sv.tpl b/util/topgen/templates/chiplevel.sv.tpl
index eea403f..8ded544 100644
--- a/util/topgen/templates/chiplevel.sv.tpl
+++ b/util/topgen/templates/chiplevel.sv.tpl
@@ -73,9 +73,8 @@
unused_im_defs, undriven_im_defs = lib.get_dangling_im_def(top["inter_signal"]["definitions"])
%>\
-// TODO: change the naming to chip_${top["name"]}_${target["name"]}
% if target["name"] != "asic":
-module top_${top["name"]}_${target["name"]} #(
+module chip_${top["name"]}_${target["name"]} #(
// Path to a VMEM file containing the contents of the boot ROM, which will be
// baked into the FPGA bitstream.
parameter BootRomInitFile = "boot_rom_fpga_${target["name"]}.32.vmem",
@@ -84,7 +83,7 @@
parameter OtpCtrlMemInitFile = "otp_img_fpga_${target["name"]}.vmem"
) (
% else:
-module top_${top["name"]}_${target["name"]} (
+module chip_${top["name"]}_${target["name"]} (
% endif
<%
@@ -1186,5 +1185,4 @@
% endif
-// TODO: change the naming to chip_
-endmodule : top_${top["name"]}_${target["name"]}
+endmodule : chip_${top["name"]}_${target["name"]}
