[doc] Use relative links in IP checklists
Make IP blocks easier to relocate by using relative links where
possible. No change to rendered output.
Signed-off-by: Philipp Wagner <phw@lowrisc.org>
diff --git a/hw/ip/aes/doc/checklist.md b/hw/ip/aes/doc/checklist.md
index 9a825e9..77edfb3 100644
--- a/hw/ip/aes/doc/checklist.md
+++ b/hw/ip/aes/doc/checklist.md
@@ -2,7 +2,7 @@
title: "AES Checklist"
---
-This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [AES peripheral.]({{<relref "hw/ip/aes/doc" >}})
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [AES peripheral.]({{<relref "." >}})
All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
## Design Checklist
@@ -11,7 +11,7 @@
Type | Item | Resolution | Note/Collaterals
--------------|----------------------- |-------------|------------------
-Documentation | [SPEC_COMPLETE][] | Done | [AES Design Spec]({{<relref "hw/ip/aes/doc" >}})
+Documentation | [SPEC_COMPLETE][] | Done | [AES Design Spec]({{<relref "." >}})
Documentation | [CSR_DEFINED][] | Done |
RTL | [CLKRST_CONNECTED][] | Done |
RTL | [IP_TOP][] | Done |
@@ -110,8 +110,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [AES DV document]({{<relref "hw/ip/aes/doc/dv" >}})
-Documentation | [DV_PLAN_COMPLETED][] | Done | [AES DV plan]({{<relref "hw/ip/aes/doc/dv/index.md#dv_plan" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [AES DV document]({{<relref "dv" >}})
+Documentation | [DV_PLAN_COMPLETED][] | Done | [AES DV plan]({{<relref "dv/index.md#dv_plan" >}})
Testbench | [TB_TOP_CREATED][] | Done |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
Testbench | [SIM_TB_ENV_CREATED][] | Done |
diff --git a/hw/ip/aon_timer/doc/checklist.md b/hw/ip/aon_timer/doc/checklist.md
index ac669a5..cd5b2db 100644
--- a/hw/ip/aon_timer/doc/checklist.md
+++ b/hw/ip/aon_timer/doc/checklist.md
@@ -2,7 +2,7 @@
title: "AON Timer Checklist"
---
-This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [AON Timer peripheral.]({{< relref "hw/ip/aon_timer/doc" >}})
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [AON Timer peripheral.]({{< relref "." >}})
All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
## Design Checklist
@@ -11,7 +11,7 @@
Type | Item | Resolution | Note/Collaterals
--------------|--------------------------------|-------------|------------------
-Documentation | [SPEC_COMPLETE][] | Done | [AON Timer Design Spec]({{<relref "hw/ip/aon_timer/doc" >}})
+Documentation | [SPEC_COMPLETE][] | Done | [AON Timer Design Spec]({{<relref "." >}})
Documentation | [CSR_DEFINED][] | Done |
RTL | [CLKRST_CONNECTED][] | Done |
RTL | [IP_TOP][] | Done |
diff --git a/hw/ip/clkmgr/doc/checklist.md b/hw/ip/clkmgr/doc/checklist.md
index 3bbd292..bc13536 100644
--- a/hw/ip/clkmgr/doc/checklist.md
+++ b/hw/ip/clkmgr/doc/checklist.md
@@ -7,7 +7,7 @@
directory for a new design that transitions from L0 (Specification) to L1 (Development)
stage, and updated as needed. Once done, please remove this comment before checking it in.
-->
-This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [CLKMGR peripheral.]({{< relref "hw/ip/clkmgr/doc" >}})
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [CLKMGR peripheral.]({{< relref "." >}})
All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
## Design Checklist
@@ -16,7 +16,7 @@
Type | Item | Resolution | Note/Collaterals
--------------|--------------------------------|-------------|------------------
-Documentation | [SPEC_COMPLETE][] | Done | [CLKMGR Design Spec]({{<relref "hw/ip/clkmgr/doc" >}})
+Documentation | [SPEC_COMPLETE][] | Done | [CLKMGR Design Spec]({{<relref "." >}})
Documentation | [CSR_DEFINED][] | Done |
RTL | [CLKRST_CONNECTED][] | Done |
RTL | [IP_TOP][] | Done |
diff --git a/hw/ip/csrng/doc/checklist.md b/hw/ip/csrng/doc/checklist.md
index b6395a4..71e36e3 100755
--- a/hw/ip/csrng/doc/checklist.md
+++ b/hw/ip/csrng/doc/checklist.md
@@ -7,7 +7,7 @@
directory for a new design that transitions from L0 (Specification) to L1 (Development)
stage, and updated as needed. Once done, please remove this comment before checking it in.
-->
-This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [CSRNG peripheral.]({{< relref "hw/ip/csrng/doc" >}})
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [CSRNG peripheral.]({{< relref "." >}})
All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
## Design Checklist
@@ -16,7 +16,7 @@
Type | Item | Resolution | Note/Collaterals
--------------|--------------------------------|-------------|------------------
-Documentation | [SPEC_COMPLETE][] | Done | [CSRNG Design Spec]({{<relref "hw/ip/csrng/doc" >}})
+Documentation | [SPEC_COMPLETE][] | Done | [CSRNG Design Spec]({{<relref "." >}})
Documentation | [CSR_DEFINED][] | Done |
RTL | [CLKRST_CONNECTED][] | Done |
RTL | [IP_TOP][] | Done |
@@ -115,8 +115,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [CSRNG DV document]({{<relref "hw/ip/csrng/doc/dv" >}})
-Documentation | [DV_PLAN_COMPLETED][] | Done | [CSRNG DV plan]({{<relref "hw/ip/csrng/doc/dv/index.md#dv_plan" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [CSRNG DV document]({{<relref "dv" >}})
+Documentation | [DV_PLAN_COMPLETED][] | Done | [CSRNG DV plan]({{<relref "dv/index.md#dv_plan" >}})
Testbench | [TB_TOP_CREATED][] | Done |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
Testbench | [SIM_TB_ENV_CREATED][] | Done |
diff --git a/hw/ip/dcd/doc/checklist.md b/hw/ip/dcd/doc/checklist.md
index c6c62bc..1d97314 100644
--- a/hw/ip/dcd/doc/checklist.md
+++ b/hw/ip/dcd/doc/checklist.md
@@ -16,7 +16,7 @@
Type | Item | Resolution | Note/Collaterals
--------------|--------------------------------|-------------|------------------
-Documentation | [SPEC_COMPLETE][] | Not Started | [DCD Design Spec]({{<relref "hw/ip/dcd/doc" >}})
+Documentation | [SPEC_COMPLETE][] | Not Started | [DCD Design Spec]({{<relref "." >}})
Documentation | [CSR_DEFINED][] | Not Started |
RTL | [CLKRST_CONNECTED][] | Not Started |
RTL | [IP_TOP][] | Not Started |
@@ -115,8 +115,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [DCD DV document]({{<relref "hw/ip/dcd/doc/dv/index.md" >}})
-Documentation | [DV_PLAN_COMPLETED][] | Not Started | [DCD DV Plan]({{<relref "hw/ip/dcd/doc/dv/index.md#dv_plan" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [DCD DV document]({{<relref "dv/index.md" >}})
+Documentation | [DV_PLAN_COMPLETED][] | Not Started | [DCD DV Plan]({{<relref "dv/index.md#dv_plan" >}})
Testbench | [TB_TOP_CREATED][] | Not Started |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Not Started |
Testbench | [SIM_TB_ENV_CREATED][] | Not Started |
diff --git a/hw/ip/edn/doc/checklist.md b/hw/ip/edn/doc/checklist.md
index ea486ef..cdb770b 100755
--- a/hw/ip/edn/doc/checklist.md
+++ b/hw/ip/edn/doc/checklist.md
@@ -7,7 +7,7 @@
directory for a new design that transitions from L0 (Specification) to L1 (Development)
stage, and updated as needed. Once done, please remove this comment before checking it in.
-->
-This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [EDN peripheral.]({{< relref "hw/ip/edn/doc" >}})
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [EDN peripheral.]({{< relref "." >}})
All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
## Design Checklist
@@ -16,7 +16,7 @@
Type | Item | Resolution | Note/Collaterals
--------------|--------------------------------|-------------|------------------
-Documentation | [SPEC_COMPLETE][] | Done | [EDN Design Spec]({{<relref "hw/ip/edn/doc" >}})
+Documentation | [SPEC_COMPLETE][] | Done | [EDN Design Spec]({{<relref "." >}})
Documentation | [CSR_DEFINED][] | Done |
RTL | [CLKRST_CONNECTED][] | Done |
RTL | [IP_TOP][] | Done |
@@ -113,8 +113,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [EDN DV document]({{<relref "hw/ip/edn/doc/dv" >}})
-Documentation | [DV_PLAN_COMPLETED][] | Done | [EDN DV plan]({{<relref "hw/ip/edn/doc/dv/index.md#dv_plan" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [EDN DV document]({{<relref "dv" >}})
+Documentation | [DV_PLAN_COMPLETED][] | Done | [EDN DV plan]({{<relref "dv/index.md#dv_plan" >}})
Testbench | [TB_TOP_CREATED][] | Done |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
Testbench | [SIM_TB_ENV_CREATED][] | Done |
diff --git a/hw/ip/entropy_src/doc/checklist.md b/hw/ip/entropy_src/doc/checklist.md
index 52b036d..20c409d 100755
--- a/hw/ip/entropy_src/doc/checklist.md
+++ b/hw/ip/entropy_src/doc/checklist.md
@@ -2,7 +2,7 @@
title: "ENTROPY_SRC Checklist"
---
-This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [ENTROPY_SRC peripheral.]({{< relref "hw/ip/entropy_src/doc" >}})
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [ENTROPY_SRC peripheral.]({{< relref "." >}})
All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
## Design Checklist
@@ -11,7 +11,7 @@
Type | Item | Resolution | Note/Collaterals
--------------|--------------------------------|-------------|------------------
-Documentation | [SPEC_COMPLETE][] | Done | [ENTROPY_SRC Design Spec]({{<relref "hw/ip/entropy_src/doc" >}})
+Documentation | [SPEC_COMPLETE][] | Done | [ENTROPY_SRC Design Spec]({{<relref "." >}})
Documentation | [CSR_DEFINED][] | Done |
RTL | [CLKRST_CONNECTED][] | Done |
RTL | [IP_TOP][] | Done |
@@ -110,8 +110,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [ENTROPY_SRC DV document]({{<relref "hw/ip/entropy_src/doc/dv" >}})
-Documentation | [DV_PLAN_COMPLETED][] | In Progress | [ENTROPY_SRC DV plan]({{<relref "hw/ip/entropy_src/doc/dv/index.md#dv_plan" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [ENTROPY_SRC DV document]({{<relref "dv" >}})
+Documentation | [DV_PLAN_COMPLETED][] | In Progress | [ENTROPY_SRC DV plan]({{<relref "dv/index.md#dv_plan" >}})
Testbench | [TB_TOP_CREATED][] | Done |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
Testbench | [SIM_TB_ENV_CREATED][] | Done |
diff --git a/hw/ip/gpio/doc/checklist.md b/hw/ip/gpio/doc/checklist.md
index 18d95a5..e156ba8 100644
--- a/hw/ip/gpio/doc/checklist.md
+++ b/hw/ip/gpio/doc/checklist.md
@@ -137,7 +137,7 @@
Review | [STD_TEST_CATEGORIES_PLANNED][] | Done | Exception (Security, Power, Debug)
Review | [V2_CHECKLIST_SCOPED][] | Done |
-[gpio_dv_doc]: {{<relref "/hw/ip/gpio/doc/dv/index.md">}}
+[gpio_dv_doc]: {{<relref "/dv/index.md">}}
[DV_DOC_DRAFT_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_doc_draft_completed" >}}
[DV_PLAN_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_plan_completed" >}}
diff --git a/hw/ip/hmac/doc/checklist.md b/hw/ip/hmac/doc/checklist.md
index d6df2c4..8614bb8 100644
--- a/hw/ip/hmac/doc/checklist.md
+++ b/hw/ip/hmac/doc/checklist.md
@@ -21,7 +21,7 @@
RTL | [ASSERT_KNOWN_ADDED][] | Done |
Code Quality | [LINT_SETUP][] | Done |
-[HMAC Spec]: {{<relref "/hw/ip/hmac/doc">}}
+[HMAC Spec]: {{<relref "/.">}}
[SPEC_COMPLETE]: {{<relref "/doc/project/checklist.md#spec_complete" >}}
[CSR_DEFINED]: {{<relref "/doc/project/checklist.md#csr_defined" >}}
diff --git a/hw/ip/i2c/doc/checklist.md b/hw/ip/i2c/doc/checklist.md
index 4852e88..8ded987 100644
--- a/hw/ip/i2c/doc/checklist.md
+++ b/hw/ip/i2c/doc/checklist.md
@@ -2,7 +2,7 @@
title: "I2C Checklist"
---
-This checklist is for [Hardware Stage][] transitions for the [I2C peripheral.]({{<relref "hw/ip/i2c/doc" >}})
+This checklist is for [Hardware Stage][] transitions for the [I2C peripheral.]({{<relref "." >}})
All checklist items refer to the content in the [Checklist.]({{<relref "/doc/project/checklist.md">}})
[Hardware Stage]: {{<relref "/doc/project/development_stages.md" >}}
@@ -13,7 +13,7 @@
Type | Item | Resolution | Note/Collaterals
--------------|--------------------------------|-------------|------------------
-Documentation | [SPEC_COMPLETE][] | Done | [I2C Spec]({{<relref "hw/ip/i2c/doc" >}})
+Documentation | [SPEC_COMPLETE][] | Done | [I2C Spec]({{<relref "." >}})
Documentation | [CSR_DEFINED][] | Done |
RTL | [CLKRST_CONNECTED][] | Done |
RTL | [IP_TOP][] | Done |
@@ -112,8 +112,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [i2c_dv_doc]({{<relref "hw/ip/i2c/doc/dv" >}})
-Documentation | [DV_PLAN_COMPLETED][] | Done | [i2c_dv_plan]({{<relref "hw/ip/i2c/doc/dv/index.md#dv_plan" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [i2c_dv_doc]({{<relref "dv" >}})
+Documentation | [DV_PLAN_COMPLETED][] | Done | [i2c_dv_plan]({{<relref "dv/index.md#dv_plan" >}})
Testbench | [TB_TOP_CREATED][] | Done |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
Testbench | [SIM_TB_ENV_CREATED][] | Done |
diff --git a/hw/ip/keymgr/doc/checklist.md b/hw/ip/keymgr/doc/checklist.md
index 88069e3..b0d0a80 100644
--- a/hw/ip/keymgr/doc/checklist.md
+++ b/hw/ip/keymgr/doc/checklist.md
@@ -115,8 +115,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [KEYMGR DV document]({{<relref "hw/ip/keymgr/doc/dv" >}})
-Documentation | [DV_PLAN_COMPLETED][] | Done | [KEYMGR DV plan]({{<relref "hw/ip/keymgr/doc/dv/index.md#dv_plan" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [KEYMGR DV document]({{<relref "dv" >}})
+Documentation | [DV_PLAN_COMPLETED][] | Done | [KEYMGR DV plan]({{<relref "dv/index.md#dv_plan" >}})
Testbench | [TB_TOP_CREATED][] | Done |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
Testbench | [SIM_TB_ENV_CREATED][] | Done |
diff --git a/hw/ip/lc_ctrl/doc/checklist.md b/hw/ip/lc_ctrl/doc/checklist.md
index a0cc8fd..c4d1f64 100644
--- a/hw/ip/lc_ctrl/doc/checklist.md
+++ b/hw/ip/lc_ctrl/doc/checklist.md
@@ -7,7 +7,7 @@
directory for a new design that transitions from L0 (Specification) to L1 (Development)
stage, and updated as needed. Once done, please remove this comment before checking it in.
-->
-This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [LC_CTRL peripheral.]({{< relref "hw/ip/lc_ctrl/doc" >}})
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [LC_CTRL peripheral.]({{< relref "." >}})
All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
## Design Checklist
@@ -16,7 +16,7 @@
Type | Item | Resolution | Note/Collaterals
--------------|--------------------------------|-------------|------------------
-Documentation | [SPEC_COMPLETE][] | Done | [LC_CTRL Design Spec]({{<relref "hw/ip/lc_ctrl/doc" >}})
+Documentation | [SPEC_COMPLETE][] | Done | [LC_CTRL Design Spec]({{<relref "." >}})
Documentation | [CSR_DEFINED][] | Done |
RTL | [CLKRST_CONNECTED][] | Done |
RTL | [IP_TOP][] | Done |
@@ -115,8 +115,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [LC_CTRL DV document]({{<relref "hw/ip/lc_ctrl/doc/dv" >}})
-Documentation | [DV_PLAN_COMPLETED][] | Done | [LC_CTRL DV plan]({{<relref "hw/ip/lc_ctrl/doc/dv/index.md#dv_plan" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [LC_CTRL DV document]({{<relref "dv" >}})
+Documentation | [DV_PLAN_COMPLETED][] | Done | [LC_CTRL DV plan]({{<relref "dv/index.md#dv_plan" >}})
Testbench | [TB_TOP_CREATED][] | Done |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
Testbench | [SIM_TB_ENV_CREATED][] | Done |
diff --git a/hw/ip/otbn/doc/checklist.md b/hw/ip/otbn/doc/checklist.md
index dd34413..f431bd0 100644
--- a/hw/ip/otbn/doc/checklist.md
+++ b/hw/ip/otbn/doc/checklist.md
@@ -2,7 +2,7 @@
title: "OTBN Checklist"
---
-This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [OTBN peripheral.]({{< relref "hw/ip/otbn/doc" >}})
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [OTBN peripheral.]({{< relref "." >}})
All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
## Design Checklist
@@ -11,7 +11,7 @@
Type | Item | Resolution | Note/Collaterals
--------------|--------------------------------|-------------|------------------
-Documentation | [SPEC_COMPLETE][] | Done | [OTBN Design Spec]({{<relref "hw/ip/otbn/doc" >}}). The specification is feature-complete, we were able to successfully run larger chunks of crypto code with the described feature set. At the same time, the specification has (known and unknown) issues, such as incomplete or buggy descriptions of individual instructions. These issues are being worked on as they are discovered while the design is in the D1 stage.
+Documentation | [SPEC_COMPLETE][] | Done | [OTBN Design Spec]({{<relref "." >}}). The specification is feature-complete, we were able to successfully run larger chunks of crypto code with the described feature set. At the same time, the specification has (known and unknown) issues, such as incomplete or buggy descriptions of individual instructions. These issues are being worked on as they are discovered while the design is in the D1 stage.
Documentation | [CSR_DEFINED][] | Done |
RTL | [CLKRST_CONNECTED][] | Done |
RTL | [IP_TOP][] | Done |
@@ -110,8 +110,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [OTBN DV document]({{<relref "hw/ip/otbn/doc/dv" >}})
-Documentation | [DV_PLAN_COMPLETED][] | Done | [OTBN DV plan]({{<relref "hw/ip/otbn/doc/dv/index.md#dv_plan" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [OTBN DV document]({{<relref "dv" >}})
+Documentation | [DV_PLAN_COMPLETED][] | Done | [OTBN DV plan]({{<relref "dv/index.md#dv_plan" >}})
Testbench | [TB_TOP_CREATED][] | Done |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
Testbench | [SIM_TB_ENV_CREATED][] | Done |
diff --git a/hw/ip/otp_ctrl/doc/checklist.md b/hw/ip/otp_ctrl/doc/checklist.md
index 956a50b..82d5d7a 100644
--- a/hw/ip/otp_ctrl/doc/checklist.md
+++ b/hw/ip/otp_ctrl/doc/checklist.md
@@ -7,7 +7,7 @@
directory for a new design that transitions from L0 (Specification) to L1 (Development)
stage, and updated as needed. Once done, please remove this comment before checking it in.
-->
-This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [OTP_CTRL peripheral.]({{< relref "hw/ip/otp_ctrl/doc" >}})
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [OTP_CTRL peripheral.]({{< relref "." >}})
All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
## Design Checklist
@@ -16,7 +16,7 @@
Type | Item | Resolution | Note/Collaterals
--------------|--------------------------------|-------------|------------------
-Documentation | [SPEC_COMPLETE][] | Done | [OTP_CTRL Design Spec]({{<relref "hw/ip/otp_ctrl/doc" >}})
+Documentation | [SPEC_COMPLETE][] | Done | [OTP_CTRL Design Spec]({{<relref "." >}})
Documentation | [CSR_DEFINED][] | Done |
RTL | [CLKRST_CONNECTED][] | Done |
RTL | [IP_TOP][] | Done |
@@ -115,8 +115,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [OTP_CTRL DV document]({{<relref "hw/ip/otp_ctrl/doc/dv" >}})
-Documentation | [DV_PLAN_COMPLETED][] | Done | [OTP_CTRL DV plan]({{<relref "hw/ip/otp_ctrl/doc/dv/index.md#dv_plan" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [OTP_CTRL DV document]({{<relref "dv" >}})
+Documentation | [DV_PLAN_COMPLETED][] | Done | [OTP_CTRL DV plan]({{<relref "dv/index.md#dv_plan" >}})
Testbench | [TB_TOP_CREATED][] | Done |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
Testbench | [SIM_TB_ENV_CREATED][] | Done |
diff --git a/hw/ip/pattgen/doc/checklist.md b/hw/ip/pattgen/doc/checklist.md
index 8178d46..81c59c8 100644
--- a/hw/ip/pattgen/doc/checklist.md
+++ b/hw/ip/pattgen/doc/checklist.md
@@ -2,7 +2,7 @@
title: "Pattgen Checklist"
---
-This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [Pattgen peripheral.]({{<relref "hw/ip/pattgen/doc" >}})
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [Pattgen peripheral.]({{<relref "." >}})
All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
## Design Checklist
@@ -11,7 +11,7 @@
Type | Item | Resolution | Note/Collaterals
--------------|----------------------- |-------------|------------------
-Documentation | [SPEC_COMPLETE][] | Done | [Pattgen Design Spec]({{<relref "hw/ip/pattgen/doc" >}})
+Documentation | [SPEC_COMPLETE][] | Done | [Pattgen Design Spec]({{<relref "." >}})
Documentation | [CSR_DEFINED][] | Done |
RTL | [CLKRST_CONNECTED][] | Done |
RTL | [IP_TOP][] | Done |
@@ -112,8 +112,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [pattgen_dv_doc]({{<relref "hw/ip/pattgen/doc/dv" >}})
-Documentation | [DV_PLAN_COMPLETED][] | Done | [pattgen_dv_plan]({{<relref "hw/ip/pattgen/doc/dv/index.md#dv_plan" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [pattgen_dv_doc]({{<relref "dv" >}})
+Documentation | [DV_PLAN_COMPLETED][] | Done | [pattgen_dv_plan]({{<relref "dv/index.md#dv_plan" >}})
Testbench | [TB_TOP_CREATED][] | Done |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
Testbench | [SIM_TB_ENV_CREATED][] | Done |
diff --git a/hw/ip/pwrmgr/doc/checklist.md b/hw/ip/pwrmgr/doc/checklist.md
index 2b6660b..1f79e4c 100644
--- a/hw/ip/pwrmgr/doc/checklist.md
+++ b/hw/ip/pwrmgr/doc/checklist.md
@@ -2,7 +2,7 @@
title: "PWRMGR Checklist"
---
-This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [PWRMGR peripheral.]({{< relref "hw/ip/pwrmgr/doc" >}})
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [PWRMGR peripheral.]({{< relref "." >}})
All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
## Design Checklist
@@ -11,7 +11,7 @@
Type | Item | Resolution | Note/Collaterals
--------------|--------------------------------|-------------|------------------
-Documentation | [SPEC_COMPLETE][] | Done |[PWRMGR Design Spec]({{<relref "hw/ip/pwrmgr/doc" >}})
+Documentation | [SPEC_COMPLETE][] | Done |[PWRMGR Design Spec]({{<relref "." >}})
Documentation | [CSR_DEFINED][] | Done |
RTL | [CLKRST_CONNECTED][] | Done |
RTL | [IP_TOP][] | Done |
diff --git a/hw/ip/rstmgr/doc/checklist.md b/hw/ip/rstmgr/doc/checklist.md
index 5c17a8b..e8d3888 100644
--- a/hw/ip/rstmgr/doc/checklist.md
+++ b/hw/ip/rstmgr/doc/checklist.md
@@ -2,7 +2,7 @@
title: "RSTMGR Checklist"
---
-This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [RSTMGR peripheral.]({{< relref "hw/ip/rstmgr/doc" >}})
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [RSTMGR peripheral.]({{< relref "." >}})
All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
## Design Checklist
@@ -11,7 +11,7 @@
Type | Item | Resolution | Note/Collaterals
--------------|--------------------------------|-------------|------------------
-Documentation | [SPEC_COMPLETE][] | Done | [RSTMGR Design Spec]({{<relref "hw/ip/rstmgr/doc" >}})
+Documentation | [SPEC_COMPLETE][] | Done | [RSTMGR Design Spec]({{<relref "." >}})
Documentation | [CSR_DEFINED][] | Done |
RTL | [CLKRST_CONNECTED][] | Done |
RTL | [IP_TOP][] | Done |
diff --git a/hw/ip/rv_timer/doc/checklist.md b/hw/ip/rv_timer/doc/checklist.md
index cb183a4..c81160d 100644
--- a/hw/ip/rv_timer/doc/checklist.md
+++ b/hw/ip/rv_timer/doc/checklist.md
@@ -22,7 +22,7 @@
RTL | [ASSERT_KNOWN_ADDED][] | Done |
Code Quality | [LINT_SETUP][] | Done |
-[RV_TIMER Spec]: {{<relref "/hw/ip/rv_timer/doc/_index.md">}}
+[RV_TIMER Spec]: {{<relref "/_index.md">}}
[SPEC_COMPLETE]: {{<relref "/doc/project/checklist.md#spec_complete" >}}
[CSR_DEFINED]: {{<relref "/doc/project/checklist.md#csr_defined" >}}
diff --git a/hw/ip/sram_ctrl/doc/checklist.md b/hw/ip/sram_ctrl/doc/checklist.md
index 4359054..1303e3b 100644
--- a/hw/ip/sram_ctrl/doc/checklist.md
+++ b/hw/ip/sram_ctrl/doc/checklist.md
@@ -2,7 +2,7 @@
title: "SRAM_CTRL Checklist"
---
-This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [SRAM_CTRL peripheral.]({{< relref "hw/ip/sram_ctrl/doc" >}})
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [SRAM_CTRL peripheral.]({{< relref "." >}})
All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
## Design Checklist
@@ -11,7 +11,7 @@
Type | Item | Resolution | Note/Collaterals
--------------|-----------------------|-------------|------------------
-Documentation | [SPEC_COMPLETE][] | Done | [SRAM_CTRL Design Spec]({{<relref "hw/ip/sram_ctrl/doc" >}})
+Documentation | [SPEC_COMPLETE][] | Done | [SRAM_CTRL Design Spec]({{<relref "." >}})
Documentation | [CSR_DEFINED][] | Done |
RTL | [CLKRST_CONNECTED][] | Done |
RTL | [IP_TOP][] | Done |
diff --git a/hw/ip/usbdev/doc/checklist.md b/hw/ip/usbdev/doc/checklist.md
index 018be7b..0b792f1 100644
--- a/hw/ip/usbdev/doc/checklist.md
+++ b/hw/ip/usbdev/doc/checklist.md
@@ -2,7 +2,7 @@
title: "USB Device Checklist"
---
-This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [USB Device peripheral.]({{< relref "hw/ip/usbdev/doc" >}})
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [USB Device peripheral.]({{< relref "." >}})
All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
## Design Checklist
@@ -11,7 +11,7 @@
Type | Item | Resolution | Note/Collaterals
--------------|--------------------------------|-------------|------------------
-Documentation | [SPEC_COMPLETE][] | Done | [USB Device Design Spec]({{<relref "hw/ip/usbdev/doc" >}})
+Documentation | [SPEC_COMPLETE][] | Done | [USB Device Design Spec]({{<relref "." >}})
Documentation | [CSR_DEFINED][] | Done |
RTL | [CLKRST_CONNECTED][] | Done |
RTL | [IP_TOP][] | Done |
@@ -110,8 +110,8 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | In Progress | [USB Device DV document]({{<relref "hw/ip/usbdev/doc/dv" >}})
-Documentation | [DV_PLAN_COMPLETED][] | In Progress | [USB Device DV plan]({{<relref "hw/ip/usbdev/doc/dv/index.md#dv_plan" >}})
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | In Progress | [USB Device DV document]({{<relref "dv" >}})
+Documentation | [DV_PLAN_COMPLETED][] | In Progress | [USB Device DV plan]({{<relref "dv/index.md#dv_plan" >}})
Testbench | [TB_TOP_CREATED][] | Done |
Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
Testbench | [SIM_TB_ENV_CREATED][] | Done |
