[top] Auto generate files Signed-off-by: Timothy Chen <timothytim@google.com> [top] Auto-generate files Signed-off-by: Timothy Chen <timothytim@google.com> [top] Auto generate files Signed-off-by: Timothy Chen <timothytim@google.com> [top] auto generate files Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson b/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson index c4acd3f..7b7b57f 100644 --- a/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson +++ b/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson
@@ -207,80 +207,55 @@ # Templated registers for software control - { name: "SPI_DEVICE_REGEN", - desc: ''' - Register write enable for spi_device reset. - ''', - swaccess: "rw1c", - hwaccess: "none", - fields: [ - { - bits: "0", - desc: ''' When 1, rst_spi_device_n is software programmable. - ''' - resval: 1, - }, - ] - tags: [// Don't reset other IPs as it will affect CSR access on these IPs - "excl:CsrAllTests:CsrExclWrite"] - }, + { multireg: { + cname: "RSTMGR_SW_RST", + name: "SW_RST_REGEN", + desc: ''' + Register write enable for software controllabe resets. + When a particular bit value is 0, the corresponding value in !SW_RST_CTRL can no longer be changed. + When a particular bit value is 1, the corresponding value in !SW_RST_CTRL can be changed. + ''', + count: 2, + swaccess: "rw0c", + hwaccess: "hro", + fields: [ + { + bits: "0", + name: "EN", + desc: "Register write enable for software controllable resets", + resval: "1", + tags: [// Don't reset other IPs as it will affect CSR access on these IPs + "excl:CsrAllTests:CsrExclCheck"] + }, + ], + } + } - { name: "RST_SPI_DEVICE_N", - regwen: "SPI_DEVICE_REGEN", - desc: ''' - Software reset control for spi_device - ''', - swaccess: "rw", - hwaccess: "hro", - fields: [ - { - bits: "0", - desc: ''' When set to 0, spi_device is held in reset. This bit can only be - programmed when spi_device_regen is 1. - ''' - resval: 1, - }, - ] - tags: [// Don't reset other IPs as it will affect CSR access on these IPs - "excl:CsrAllTests:CsrExclWrite"] - }, - { name: "USB_REGEN", - desc: ''' - Register write enable for usb reset. - ''', - swaccess: "rw1c", - hwaccess: "none", - fields: [ - { - bits: "0", - desc: ''' When 1, rst_usb_n is software programmable. - ''' - resval: 1, - }, - ] - tags: [// Don't reset other IPs as it will affect CSR access on these IPs - "excl:CsrAllTests:CsrExclWrite"] - }, - - { name: "RST_USB_N", - regwen: "USB_REGEN", - desc: ''' - Software reset control for usb - ''', - swaccess: "rw", - hwaccess: "hro", - fields: [ - { - bits: "0", - desc: ''' When set to 0, usb is held in reset. This bit can only be - programmed when usb_regen is 1. - ''' - resval: 1, - }, - ] - tags: [// Don't reset other IPs as it will affect CSR access on these IPs - "excl:CsrAllTests:CsrExclWrite"] - }, + { multireg: { + cname: "RSTMGR_SW_RST", + name: "SW_RST_CTRL_N", + desc: ''' + Software controllabe resets. + When a particular bit value is 0, the corresponding module is held in reset. + When a particular bit value is 1, the corresponding module is not held in reset. + ''', + count: 2, + swaccess: "rw", + hwaccess: "hro", + hwext: "true", + hwqe: "true", + fields: [ + { + bits: "0", + name: "VAL", + desc: "Software reset value", + resval: "1", + tags: [// Don't reset other IPs as it will affect CSR access on these IPs + "excl:CsrAllTests:CsrExclCheck"] + }, + ], + } + } ]
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv index ec6ebb9..0117b0b 100644 --- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv +++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
@@ -153,6 +153,30 @@ assign pwr_o.rst_lc_src_n = rst_lc_src_n; assign pwr_o.rst_sys_src_n = rst_sys_src_n; + + //////////////////////////////////////////////////// + // Software reset controls external reg // + //////////////////////////////////////////////////// + logic [2-1:0] sw_rst_ctrl_n; + + for (genvar i=0; i < 2; i++) begin : gen_sw_rst_ext_regs + prim_subreg #( + .DW(1), + .SWACCESS("RW"), + .RESVAL(1) + ) u_rst_sw_ctrl_reg ( + .clk_i, + .rst_ni(local_rst_n), + .we(reg2hw.sw_rst_ctrl_n[i].qe & reg2hw.sw_rst_regen[i]), + .wd(reg2hw.sw_rst_ctrl_n[i].q), + .de('0), + .d('0), + .qe(), + .q(sw_rst_ctrl_n[i]), + .qs(hw2reg.sw_rst_ctrl_n[i].d) + ); + end + //////////////////////////////////////////////////// // leaf reset in the system // // These should all be generated // @@ -375,7 +399,7 @@ ) u_spi_device ( .clk_i(clk_io_div2_i), .rst_ni(rst_sys_src_n[0]), - .d_i(reg2hw.rst_spi_device_n.q), + .d_i(sw_rst_ctrl_n[SPI_DEVICE]), .q_o(rst_spi_device_n) ); @@ -394,7 +418,7 @@ ) u_usb ( .clk_i(clk_usb_i), .rst_ni(rst_sys_src_n[0]), - .d_i(reg2hw.rst_usb_n.q), + .d_i(sw_rst_ctrl_n[USB]), .q_o(rst_usb_n) );
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv index 0efbd77..1228a8c 100644 --- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv +++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv
@@ -24,8 +24,9 @@ // calculated domains parameter int OffDomains = PowerDomains-1; - // low power exit + ndm_reset_req + external reasons - //parameter int ResetReasons = 1 + 1 + HwResetReqs; + // positions of software controllable reset bits + parameter int SPI_DEVICE = 0; + parameter int USB = 1; // ast interface typedef struct packed {
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_pkg.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_pkg.sv index 66998c7..3599a78 100644 --- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_pkg.sv +++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_pkg.sv
@@ -9,6 +9,8 @@ // Param list parameter int RdWidth = 32; parameter int IdxWidth = 4; + parameter int SW_RST_REGEN = 2; + parameter int SW_RST_CTRL_N = 2; //////////////////////////// // Typedefs for registers // @@ -30,11 +32,12 @@ typedef struct packed { logic q; - } rstmgr_reg2hw_rst_spi_device_n_reg_t; + } rstmgr_reg2hw_sw_rst_regen_mreg_t; typedef struct packed { logic q; - } rstmgr_reg2hw_rst_usb_n_reg_t; + logic qe; + } rstmgr_reg2hw_sw_rst_ctrl_n_mreg_t; typedef struct packed { @@ -67,25 +70,30 @@ logic [31:0] d; } rstmgr_hw2reg_alert_info_reg_t; + typedef struct packed { + logic d; + } rstmgr_hw2reg_sw_rst_ctrl_n_mreg_t; + /////////////////////////////////////// // Register to internal design logic // /////////////////////////////////////// typedef struct packed { - rstmgr_reg2hw_reset_info_reg_t reset_info; // [7:7] - rstmgr_reg2hw_alert_info_ctrl_reg_t alert_info_ctrl; // [6:2] - rstmgr_reg2hw_rst_spi_device_n_reg_t rst_spi_device_n; // [1:1] - rstmgr_reg2hw_rst_usb_n_reg_t rst_usb_n; // [0:0] + rstmgr_reg2hw_reset_info_reg_t reset_info; // [11:11] + rstmgr_reg2hw_alert_info_ctrl_reg_t alert_info_ctrl; // [10:6] + rstmgr_reg2hw_sw_rst_regen_mreg_t [1:0] sw_rst_regen; // [5:4] + rstmgr_reg2hw_sw_rst_ctrl_n_mreg_t [1:0] sw_rst_ctrl_n; // [3:0] } rstmgr_reg2hw_t; /////////////////////////////////////// // Internal design logic to register // /////////////////////////////////////// typedef struct packed { - rstmgr_hw2reg_reset_info_reg_t reset_info; // [43:43] - rstmgr_hw2reg_alert_info_ctrl_reg_t alert_info_ctrl; // [42:38] - rstmgr_hw2reg_alert_info_attr_reg_t alert_info_attr; // [37:38] - rstmgr_hw2reg_alert_info_reg_t alert_info; // [37:38] + rstmgr_hw2reg_reset_info_reg_t reset_info; // [45:45] + rstmgr_hw2reg_alert_info_ctrl_reg_t alert_info_ctrl; // [44:40] + rstmgr_hw2reg_alert_info_attr_reg_t alert_info_attr; // [39:40] + rstmgr_hw2reg_alert_info_reg_t alert_info; // [39:40] + rstmgr_hw2reg_sw_rst_ctrl_n_mreg_t [1:0] sw_rst_ctrl_n; // [39:38] } rstmgr_hw2reg_t; // Register Address @@ -93,10 +101,8 @@ parameter logic [4:0] RSTMGR_ALERT_INFO_CTRL_OFFSET = 5'h 4; parameter logic [4:0] RSTMGR_ALERT_INFO_ATTR_OFFSET = 5'h 8; parameter logic [4:0] RSTMGR_ALERT_INFO_OFFSET = 5'h c; - parameter logic [4:0] RSTMGR_SPI_DEVICE_REGEN_OFFSET = 5'h 10; - parameter logic [4:0] RSTMGR_RST_SPI_DEVICE_N_OFFSET = 5'h 14; - parameter logic [4:0] RSTMGR_USB_REGEN_OFFSET = 5'h 18; - parameter logic [4:0] RSTMGR_RST_USB_N_OFFSET = 5'h 1c; + parameter logic [4:0] RSTMGR_SW_RST_REGEN_OFFSET = 5'h 10; + parameter logic [4:0] RSTMGR_SW_RST_CTRL_N_OFFSET = 5'h 14; // Register Index @@ -105,22 +111,18 @@ RSTMGR_ALERT_INFO_CTRL, RSTMGR_ALERT_INFO_ATTR, RSTMGR_ALERT_INFO, - RSTMGR_SPI_DEVICE_REGEN, - RSTMGR_RST_SPI_DEVICE_N, - RSTMGR_USB_REGEN, - RSTMGR_RST_USB_N + RSTMGR_SW_RST_REGEN, + RSTMGR_SW_RST_CTRL_N } rstmgr_id_e; // Register width information to check illegal writes - parameter logic [3:0] RSTMGR_PERMIT [8] = '{ + parameter logic [3:0] RSTMGR_PERMIT [6] = '{ 4'b 0001, // index[0] RSTMGR_RESET_INFO 4'b 0001, // index[1] RSTMGR_ALERT_INFO_CTRL 4'b 0001, // index[2] RSTMGR_ALERT_INFO_ATTR 4'b 1111, // index[3] RSTMGR_ALERT_INFO - 4'b 0001, // index[4] RSTMGR_SPI_DEVICE_REGEN - 4'b 0001, // index[5] RSTMGR_RST_SPI_DEVICE_N - 4'b 0001, // index[6] RSTMGR_USB_REGEN - 4'b 0001 // index[7] RSTMGR_RST_USB_N + 4'b 0001, // index[4] RSTMGR_SW_RST_REGEN + 4'b 0001 // index[5] RSTMGR_SW_RST_CTRL_N }; endpackage
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv index 53a67ea..c867410 100644 --- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv +++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv
@@ -93,18 +93,20 @@ logic alert_info_attr_re; logic [31:0] alert_info_qs; logic alert_info_re; - logic spi_device_regen_qs; - logic spi_device_regen_wd; - logic spi_device_regen_we; - logic rst_spi_device_n_qs; - logic rst_spi_device_n_wd; - logic rst_spi_device_n_we; - logic usb_regen_qs; - logic usb_regen_wd; - logic usb_regen_we; - logic rst_usb_n_qs; - logic rst_usb_n_wd; - logic rst_usb_n_we; + logic sw_rst_regen_en_0_qs; + logic sw_rst_regen_en_0_wd; + logic sw_rst_regen_en_0_we; + logic sw_rst_regen_en_1_qs; + logic sw_rst_regen_en_1_wd; + logic sw_rst_regen_en_1_we; + logic sw_rst_ctrl_n_val_0_qs; + logic sw_rst_ctrl_n_val_0_wd; + logic sw_rst_ctrl_n_val_0_we; + logic sw_rst_ctrl_n_val_0_re; + logic sw_rst_ctrl_n_val_1_qs; + logic sw_rst_ctrl_n_val_1_wd; + logic sw_rst_ctrl_n_val_1_we; + logic sw_rst_ctrl_n_val_1_re; // Register instances // R[reset_info]: V(False) @@ -299,19 +301,22 @@ ); - // R[spi_device_regen]: V(False) + // Subregister 0 of Multireg sw_rst_regen + // R[sw_rst_regen]: V(False) + + // F[en_0]: 0:0 prim_subreg #( .DW (1), - .SWACCESS("W1C"), + .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_spi_device_regen ( + ) u_sw_rst_regen_en_0 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (spi_device_regen_we), - .wd (spi_device_regen_wd), + .we (sw_rst_regen_en_0_we), + .wd (sw_rst_regen_en_0_wd), // from internal hardware .de (1'b0), @@ -319,53 +324,25 @@ // to internal hardware .qe (), - .q (), + .q (reg2hw.sw_rst_regen[0].q ), // to register interface (read) - .qs (spi_device_regen_qs) + .qs (sw_rst_regen_en_0_qs) ); - // R[rst_spi_device_n]: V(False) - + // F[en_1]: 1:1 prim_subreg #( .DW (1), - .SWACCESS("RW"), + .SWACCESS("W0C"), .RESVAL (1'h1) - ) u_rst_spi_device_n ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (rst_spi_device_n_we & spi_device_regen_qs), - .wd (rst_spi_device_n_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rst_spi_device_n.q ), - - // to register interface (read) - .qs (rst_spi_device_n_qs) - ); - - - // R[usb_regen]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("W1C"), - .RESVAL (1'h1) - ) u_usb_regen ( + ) u_sw_rst_regen_en_1 ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (usb_regen_we), - .wd (usb_regen_wd), + .we (sw_rst_regen_en_1_we), + .wd (sw_rst_regen_en_1_wd), // from internal hardware .de (1'b0), @@ -373,53 +350,60 @@ // to internal hardware .qe (), - .q (), + .q (reg2hw.sw_rst_regen[1].q ), // to register interface (read) - .qs (usb_regen_qs) - ); - - - // R[rst_usb_n]: V(False) - - prim_subreg #( - .DW (1), - .SWACCESS("RW"), - .RESVAL (1'h1) - ) u_rst_usb_n ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - - // from register interface (qualified with register enable) - .we (rst_usb_n_we & usb_regen_qs), - .wd (rst_usb_n_wd), - - // from internal hardware - .de (1'b0), - .d ('0 ), - - // to internal hardware - .qe (), - .q (reg2hw.rst_usb_n.q ), - - // to register interface (read) - .qs (rst_usb_n_qs) + .qs (sw_rst_regen_en_1_qs) ); - logic [7:0] addr_hit; + // Subregister 0 of Multireg sw_rst_ctrl_n + // R[sw_rst_ctrl_n]: V(True) + + // F[val_0]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_sw_rst_ctrl_n_val_0 ( + .re (sw_rst_ctrl_n_val_0_re), + .we (sw_rst_ctrl_n_val_0_we), + .wd (sw_rst_ctrl_n_val_0_wd), + .d (hw2reg.sw_rst_ctrl_n[0].d), + .qre (), + .qe (reg2hw.sw_rst_ctrl_n[0].qe), + .q (reg2hw.sw_rst_ctrl_n[0].q ), + .qs (sw_rst_ctrl_n_val_0_qs) + ); + + + // F[val_1]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_sw_rst_ctrl_n_val_1 ( + .re (sw_rst_ctrl_n_val_1_re), + .we (sw_rst_ctrl_n_val_1_we), + .wd (sw_rst_ctrl_n_val_1_wd), + .d (hw2reg.sw_rst_ctrl_n[1].d), + .qre (), + .qe (reg2hw.sw_rst_ctrl_n[1].qe), + .q (reg2hw.sw_rst_ctrl_n[1].q ), + .qs (sw_rst_ctrl_n_val_1_qs) + ); + + + + + + logic [5:0] addr_hit; always_comb begin addr_hit = '0; addr_hit[0] = (reg_addr == RSTMGR_RESET_INFO_OFFSET); addr_hit[1] = (reg_addr == RSTMGR_ALERT_INFO_CTRL_OFFSET); addr_hit[2] = (reg_addr == RSTMGR_ALERT_INFO_ATTR_OFFSET); addr_hit[3] = (reg_addr == RSTMGR_ALERT_INFO_OFFSET); - addr_hit[4] = (reg_addr == RSTMGR_SPI_DEVICE_REGEN_OFFSET); - addr_hit[5] = (reg_addr == RSTMGR_RST_SPI_DEVICE_N_OFFSET); - addr_hit[6] = (reg_addr == RSTMGR_USB_REGEN_OFFSET); - addr_hit[7] = (reg_addr == RSTMGR_RST_USB_N_OFFSET); + addr_hit[4] = (reg_addr == RSTMGR_SW_RST_REGEN_OFFSET); + addr_hit[5] = (reg_addr == RSTMGR_SW_RST_CTRL_N_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -433,8 +417,6 @@ if (addr_hit[3] && reg_we && (RSTMGR_PERMIT[3] != (RSTMGR_PERMIT[3] & reg_be))) wr_err = 1'b1 ; if (addr_hit[4] && reg_we && (RSTMGR_PERMIT[4] != (RSTMGR_PERMIT[4] & reg_be))) wr_err = 1'b1 ; if (addr_hit[5] && reg_we && (RSTMGR_PERMIT[5] != (RSTMGR_PERMIT[5] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[6] && reg_we && (RSTMGR_PERMIT[6] != (RSTMGR_PERMIT[6] & reg_be))) wr_err = 1'b1 ; - if (addr_hit[7] && reg_we && (RSTMGR_PERMIT[7] != (RSTMGR_PERMIT[7] & reg_be))) wr_err = 1'b1 ; end assign reset_info_por_we = addr_hit[0] & reg_we & ~wr_err; @@ -459,17 +441,19 @@ assign alert_info_re = addr_hit[3] && reg_re; - assign spi_device_regen_we = addr_hit[4] & reg_we & ~wr_err; - assign spi_device_regen_wd = reg_wdata[0]; + assign sw_rst_regen_en_0_we = addr_hit[4] & reg_we & ~wr_err; + assign sw_rst_regen_en_0_wd = reg_wdata[0]; - assign rst_spi_device_n_we = addr_hit[5] & reg_we & ~wr_err; - assign rst_spi_device_n_wd = reg_wdata[0]; + assign sw_rst_regen_en_1_we = addr_hit[4] & reg_we & ~wr_err; + assign sw_rst_regen_en_1_wd = reg_wdata[1]; - assign usb_regen_we = addr_hit[6] & reg_we & ~wr_err; - assign usb_regen_wd = reg_wdata[0]; + assign sw_rst_ctrl_n_val_0_we = addr_hit[5] & reg_we & ~wr_err; + assign sw_rst_ctrl_n_val_0_wd = reg_wdata[0]; + assign sw_rst_ctrl_n_val_0_re = addr_hit[5] && reg_re; - assign rst_usb_n_we = addr_hit[7] & reg_we & ~wr_err; - assign rst_usb_n_wd = reg_wdata[0]; + assign sw_rst_ctrl_n_val_1_we = addr_hit[5] & reg_we & ~wr_err; + assign sw_rst_ctrl_n_val_1_wd = reg_wdata[1]; + assign sw_rst_ctrl_n_val_1_re = addr_hit[5] && reg_re; // Read data return always_comb begin @@ -496,19 +480,13 @@ end addr_hit[4]: begin - reg_rdata_next[0] = spi_device_regen_qs; + reg_rdata_next[0] = sw_rst_regen_en_0_qs; + reg_rdata_next[1] = sw_rst_regen_en_1_qs; end addr_hit[5]: begin - reg_rdata_next[0] = rst_spi_device_n_qs; - end - - addr_hit[6]: begin - reg_rdata_next[0] = usb_regen_qs; - end - - addr_hit[7]: begin - reg_rdata_next[0] = rst_usb_n_qs; + reg_rdata_next[0] = sw_rst_ctrl_n_val_0_qs; + reg_rdata_next[1] = sw_rst_ctrl_n_val_1_qs; end default: begin
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h index 81759bb..c325486 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -772,6 +772,15 @@ kTopEarlgreyPowerManagerWakeUpsLast = 0, /**< \internal Last valid pwrmgr wakeup signal */ } top_earlgrey_power_manager_wake_ups_t; +/** + * Reset Manager Software Controlled Resets + */ +typedef enum top_earlgrey_reset_manager_sw_resets { + kTopEarlgreyResetManagerSwResetsSpiDevice = 0, /**< */ + kTopEarlgreyResetManagerSwResetsUsb = 1, /**< */ + kTopEarlgreyResetManagerSwResetsLast = 1, /**< \internal Last valid rstmgr software reset request */ +} top_earlgrey_reset_manager_sw_resets_t; + // Header Extern Guard #ifdef __cplusplus } // extern "C"