commit 92b526ea2f076a0a94484a5b20ff5a8c6b6e8c91
author Timothy Chen <timothytim@google.com> Mon Feb 01 21:23:42 2021 -0800
committer tjaychen <timothytim@google.com> Wed Feb 03 15:29:38 2021 -0800
tree 32c037b591151bd555b011d98226390a8d8c08aa
parent 469a303d48130a8c680934b87cc8e02c67be846b

[top] Re-arrange always on modules

- move usbdev out of always on
- move pinmux / padctrl to peri clock domain
- move sensor_ctrl / ast to always on and peri clock domain
- add validation check to make sure there is only 1 pwr/clk/rstmgr per top
- remove instance name hardcoding in merge.py

Signed-off-by: Timothy Chen <timothytim@google.com>

[util] tweak based on review comments

Signed-off-by: Timothy Chen <timothytim@google.com>

hw/top_earlgrey/data/top_earlgrey.sv.tpl

diff --git a/hw/top_earlgrey/data/top_earlgrey.sv.tpl b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
index 0f4cf43..39ea30f 100644
--- a/hw/top_earlgrey/data/top_earlgrey.sv.tpl
+++ b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
@@ -249,7 +249,7 @@
     .crash_dump_o         (rv_core_ibex_crashdump),
     // CPU control signals
     .fetch_enable_i       (1'b1),
-    .core_sleep_o         (pwrmgr_pwr_cpu.core_sleeping)
+    .core_sleep_o         (pwrmgr_aon_pwr_cpu.core_sleeping)
   );
 
   // Debug Module (RISC-V Debug Spec 0.13)
@@ -293,8 +293,8 @@
     .jtag_rsp_o    (jtag_rsp)
   );
 
-  assign rstmgr_cpu.ndmreset_req = ndmreset_req;
-  assign rstmgr_cpu.rst_cpu_n = ${top["reset_paths"]["sys"]}[rstmgr_pkg::Domain0Sel];
+  assign rstmgr_aon_cpu.ndmreset_req = ndmreset_req;
+  assign rstmgr_aon_cpu.rst_cpu_n = ${top["reset_paths"]["sys"]}[rstmgr_pkg::Domain0Sel];
 
 ## Memory Instantiation
 % for m in top["memory"]: