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opensecura / 3p / lowrisc / opentitan / c71e12d84629e784ced1029714965b0d76fa6ec4
commitc71e12d84629e784ced1029714965b0d76fa6ec4[log] [tgz]
authorSrikrishna Iyer <sriyer@google.com>Tue Feb 15 09:56:36 2022 -0800
committerSrikrishna Iyer <46467186+sriyerg@users.noreply.github.com>Wed Feb 16 14:03:42 2022 -0800
tree72e8dbda6d803786899561e1d5deceb6d80fce5a
parent00d77e5dc7ea3a985a717470acfba75f8f2bcdd4 [diff]
[rv_dm dv] Add Hjson spec for debug memory

The comportable rv_dm wrapper only exposes the debug memory as a window.
Our reggen tool infers that as a read-only memory and creates a RAL
model reflecting the same.

In reality, behind the window is a whole slew of CSRs, ROM and SRAM
(program buffer) that are implemented in the vendored-in PULP codebase.

To better aid rv_dm DV, we hand-write that address space with the spec
as reference:
https://github.com/lowRISC/opentitan/blob/master/hw/vendor/pulp_riscv_dbg/doc/debug-system.md#debug-memory

In the subsequent PR, this Hjson will be used for generating a proper
RAL model reflecting the full address map of the debug memory, rather
than just a ROM space inferred from the window.

Signed-off-by: Srikrishna Iyer <sriyer@google.com>
2 files changed
tree: 72e8dbda6d803786899561e1d5deceb6d80fce5a
  1. .github/
  2. ci/
  3. doc/
  4. hw/
  5. rules/
  6. site/
  7. sw/
  8. test/
  9. third_party/
  10. util/
  11. .bazelignore
  12. .bazelrc
  13. .bazelversion
  14. .clang-format
  15. .dockerignore
  16. .flake8
  17. .gitignore
  18. .style.yapf
  19. .svlint.toml
  20. .svls.toml
  21. _index.md
  22. apt-requirements.txt
  23. azure-pipelines.yml
  24. BUILD
  25. check_tool_requirements.core
  26. CLA
  27. COMMITTERS
  28. CONTRIBUTING.md
  29. LICENSE
  30. meson-config.txt
  31. meson.build
  32. meson_init.sh
  33. meson_options.txt
  34. python-requirements.txt
  35. README.md
  36. tool_requirements.py
  37. toolchain.txt
  38. topgen-reg-only.core
  39. topgen.core
  40. WORKSPACE
  41. yum-requirements.txt
README.md

OpenTitan

OpenTitan logo

About the project

OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.

About this repository

This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository. It exists to enable collaboration across partners participating in the OpenTitan project.

Documentation

The project contains comprehensive documentation of all IPs and tools. You can access it online at docs.opentitan.org.

How to contribute

Have a look at CONTRIBUTING and our documentation on project organization and processes for guidelines on how to contribute code to this repository.

Licensing

Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).