| commit | 915a624a796cc7f05472a581ccdb17298eaf384f | [log] [tgz] |
|---|---|---|
| author | Srikrishna Iyer <sriyer@google.com> | Sat Aug 20 09:51:19 2022 -0700 |
| committer | Srikrishna Iyer <46467186+sriyerg@users.noreply.github.com> | Fri Aug 26 11:50:07 2022 -0700 |
| tree | f60cfbee10a87bc3526535dbfceb5f25f343b740 | |
| parent | edc3accc977ff4c57703f36460bb60c0e4cd02bd [diff] |
[rtl] Randomize srate value in AST RNG
This commit randomizes the dv_srate_value in
AST RNG model so that the randomness fetched from
AST is different for different simulation seeds.
It provides `rng_stage_value_min` and rng_srate_value_max`
variables that can be set via plusargs - these are the
bounds within which the `dv_srate_value` is randomized
within. By default, the bound is {[32:128]}. These bounds
must stay within {[5:500]} range.
The chip_sim_cfg.hjson is also updated to set these
plusargs correctly.
Signed-off-by: Srikrishna Iyer <sriyer@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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