commit 8ebb832de6aed6b20a87cf4f63a33db057200210
author Weicai Yang <weicai@google.com> Thu Jun 03 16:17:57 2021 -0700
committer weicaiyang <49293026+weicaiyang@users.noreply.github.com> Thu Jun 03 20:56:40 2021 -0700
tree 7fc3a1cb005dc6a3cb9818ad46e2b0dc2271c12e
parent 22bdcfcc2ede3e148414b92042a8905a227a8c4e

[dv] fix a typo in tl_device_access_types_testplan

Signed-off-by: Weicai Yang <weicai@google.com>

hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson

diff --git a/hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson b/hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson
index 708ba6b..2eae33e 100644
--- a/hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson
+++ b/hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson
@@ -26,7 +26,7 @@
               - access unmapped address, expect `d_error = 1` when `devmode_i == 1`
               - write a CSR with unaligned address, e.g. `a_address[1:0] != 0`
               - write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
-              - write a memory with `a_mask = '1` when it doesn't support partial accesses
+              - write a memory with `a_mask != '1` when it doesn't support partial accesses
               - read a WO (write-only) memory'''
       milestone: V2
       tests: ["{name}_tl_errors"]