commit 8eb2bc0879d85d0cd25aa3f6bbfb85f0bef69fb9
author Guillermo Maturana <maturana@google.com> Tue Mar 01 14:29:09 2022 -0800
committer Matute <maturana@google.com> Wed Mar 02 15:04:46 2022 -0800
tree 646e8dba6039070a094b7a7786df13c770035d25
parent ae0940f17cb0b0e301137a868388ab0629cf2de9

[full_chip,clkmgr] Bind clkmgr SVA in full chip

Signed-off-by: Guillermo Maturana <maturana@google.com>

hw/top_earlgrey/dv/chip_sim.core

diff --git a/hw/top_earlgrey/dv/chip_sim.core b/hw/top_earlgrey/dv/chip_sim.core
index 6ff59fe..b359896 100644
--- a/hw/top_earlgrey/dv/chip_sim.core
+++ b/hw/top_earlgrey/dv/chip_sim.core
@@ -15,6 +15,7 @@
     depend:
       - lowrisc:ip:tlul
       - lowrisc:dv:chip_test
+      - lowrisc:dv:clkmgr_sva
       - lowrisc:dv:pwrmgr_sva
       - lowrisc:dv:rstmgr_sva
       - lowrisc:dv:xbar_main_bind

hw/top_earlgrey/dv/chip_sim_cfg.hjson

diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
index d890774..258f583 100644
--- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson
+++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
@@ -24,7 +24,8 @@
   ral_spec: "{proj_root}/hw/top_earlgrey/data/top_earlgrey.hjson"
 
   // Add additional tops for simulation.
-  sim_tops: ["pwrmgr_bind",
+  sim_tops: ["clkmgr_bind",
+             "pwrmgr_bind",
              "rstmgr_bind",
              "xbar_main_bind",
              "xbar_peri_bind"]