[dv/kmac] add stress tests
Signed-off-by: Udi Jonnalagadda <udij@google.com>
diff --git a/hw/ip/kmac/data/kmac_base_testplan.hjson b/hw/ip/kmac/data/kmac_base_testplan.hjson
index 9ef9975..7f9c9da 100644
--- a/hw/ip/kmac/data/kmac_base_testplan.hjson
+++ b/hw/ip/kmac/data/kmac_base_testplan.hjson
@@ -6,8 +6,7 @@
import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
"hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
"hw/dv/tools/dvsim/testplans/mem_testplan.hjson",
- // Uncomment stress tests once ready to prevent seeing failures every night.
- //"hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
+ "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
"hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson"]
testpoints: [
{
diff --git a/hw/ip/kmac/dv/env/kmac_env.core b/hw/ip/kmac/dv/env/kmac_env.core
index 9a64f9d..2371124 100644
--- a/hw/ip/kmac/dv/env/kmac_env.core
+++ b/hw/ip/kmac/dv/env/kmac_env.core
@@ -36,6 +36,7 @@
- seq_lib/kmac_test_vectors_kmac_xof_vseq.sv: {is_include_file: true}
- seq_lib/kmac_burst_write_vseq.sv: {is_include_file: true}
- seq_lib/kmac_app_vseq.sv: {is_include_file: true}
+ - seq_lib/kmac_stress_all_vseq.sv: {is_include_file: true}
file_type: systemVerilogSource
generate:
diff --git a/hw/ip/kmac/dv/env/seq_lib/kmac_stress_all_vseq.sv b/hw/ip/kmac/dv/env/seq_lib/kmac_stress_all_vseq.sv
new file mode 100644
index 0000000..c9ad68e
--- /dev/null
+++ b/hw/ip/kmac/dv/env/seq_lib/kmac_stress_all_vseq.sv
@@ -0,0 +1,48 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class kmac_stress_all_vseq extends kmac_base_vseq;
+
+ `uvm_object_utils(kmac_stress_all_vseq)
+ `uvm_object_new
+
+ string vseq_names[$] = {
+ "kmac_smoke_vseq",
+ "kmac_long_msg_and_output_vseq",
+ "kmac_burst_write_vseq",
+ "kmac_sideload_vseq",
+ // Do not include sha3 or shake test vectors as they require a specific value for a shared
+ // plusarg - excluding them does not detract much from the stress_all test
+ "kmac_test_vectors_kmac_vseq",
+ "kmac_test_vectors_kmac_xof_vseq",
+ "kmac_app_vseq"
+ };
+
+ virtual task pre_start();
+ do_kmac_init = 0;
+ super.pre_start();
+ endtask
+
+ task body();
+ `uvm_info(`gfn, $sformatf("Running %0d random sequences", num_trans), UVM_LOW)
+ for (int i = 0; i < num_trans; i++) begin
+ uvm_sequence seq;
+ kmac_base_vseq kmac_vseq;
+ uint seq_idx = $urandom_range(0, vseq_names.size() - 1);
+ string cur_vseq_name = vseq_names[seq_idx];
+
+ seq = create_seq_by_name(cur_vseq_name);
+ `downcast(kmac_vseq, seq)
+
+ kmac_vseq.do_apply_reset = (do_apply_reset) ? $urandom_range(0, 1) : 0;
+
+ kmac_vseq.set_sequencer(p_sequencer);
+ // Limit the number of hashes performed by each subsequence as this can easily timeout
+ `DV_CHECK_RANDOMIZE_WITH_FATAL(kmac_vseq, kmac_vseq.num_trans inside {[0 : 50]};)
+ `uvm_info(`gfn, $sformatf("iteration[%0d]: starting %0s", i, cur_vseq_name), UVM_LOW)
+ kmac_vseq.start(p_sequencer);
+ end
+ endtask
+
+endclass
diff --git a/hw/ip/kmac/dv/env/seq_lib/kmac_vseq_list.sv b/hw/ip/kmac/dv/env/seq_lib/kmac_vseq_list.sv
index 871f063..7a161d8 100644
--- a/hw/ip/kmac/dv/env/seq_lib/kmac_vseq_list.sv
+++ b/hw/ip/kmac/dv/env/seq_lib/kmac_vseq_list.sv
@@ -14,3 +14,4 @@
`include "kmac_test_vectors_kmac_xof_vseq.sv"
`include "kmac_burst_write_vseq.sv"
`include "kmac_app_vseq.sv"
+`include "kmac_stress_all_vseq.sv"
diff --git a/hw/ip/kmac/dv/kmac_base_sim_cfg.hjson b/hw/ip/kmac/dv/kmac_base_sim_cfg.hjson
index 201f202..c17c142 100644
--- a/hw/ip/kmac/dv/kmac_base_sim_cfg.hjson
+++ b/hw/ip/kmac/dv/kmac_base_sim_cfg.hjson
@@ -30,9 +30,8 @@
"{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
"{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
"{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
- "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson"]
- // TODO uncomment when ready to implement
- //"{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"]
+ "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson",
+ "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"]
// Add additional tops for simulation.
sim_tops: ["kmac_bind"]
@@ -40,7 +39,7 @@
// Default iterations for all tests - each test entry can override this.
reseed: 50
- run_opts: ["+test_timeout_ns=4000000000"]
+ run_opts: ["+test_timeout_ns=4_000_000_000"]
// Need to override the default output directory
overrides: [
@@ -80,7 +79,7 @@
{
name: "{variant}_long_msg_and_output"
uvm_test_seq: kmac_long_msg_and_output_vseq
- run_opts: ["+test_timeout_ns=10000000000"]
+ run_opts: ["+test_timeout_ns=10_000_000_000"]
}
{
name: "{variant}_sideload"
@@ -140,6 +139,15 @@
name: "{variant}_app"
uvm_test_seq: kmac_app_vseq
}
+ {
+ name: kmac_stress_all
+ run_opts: ["+test_timeout_ns=10_000_000_000",
+ "+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0"]
+ }
+ {
+ name: kmac_stress_all_with_rand_reset
+ run_opts: ["+test_vectors_dir={build_dir}/src/lowrisc_dv_test_vectors_0"]
+ }
]
// List of regressions.
