fix(spi_device): Delay CMDFIFO Event

Issue #11871

This commit revises upload module to generate the command FIFO not empty
event after the SPI transaction.

This logic does not follow the FIFO notempty signal from
prim_fifo_async_sram_adapter module. It rather implements custom logic
to:

- Set interrupt when CMDFIFO is not empty AND the SPI transaction is
  completed.

To achieve the criteria above, the logic keeps the notempty signal until
the transaction is completed. The logic in SYS_CLK detects the end of
the transaction (sys_csb_deasserted_pulse_i) and if  the value is one,
creates a pulse.

Signed-off-by: Eunchan Kim <eunchan@opentitan.org>