Adding I2C FSM functionality and interrupt support
-Created RX and FMT Fifos
-Renamed 1 register for common nomenclature with i2c spec
-Changed register descriptions
-Added skeleton for I2C FSM
diff --git a/hw/ip/i2c/doc/i2c.hjson b/hw/ip/i2c/doc/i2c.hjson
index 7fc713d..4003c69 100644
--- a/hw/ip/i2c/doc/i2c.hjson
+++ b/hw/ip/i2c/doc/i2c.hjson
@@ -105,6 +105,7 @@
{ name: "RDATA"
desc: "I2C read data"
swaccess: "ro"
+ hwaccess: "hrw"
hwext: "true"
hwre: "true"
fields: [
@@ -279,11 +280,11 @@
fields: [
{ bits: "15:0"
name: "THIGH"
- desc: "The minimum time to hold SCL high in a given pulse"
+ desc: "The actual time to hold SCL high in a given pulse"
}
{ bits: "31:16"
name: "TLOW"
- desc: "The minimum time to hold SCL low between any two SCL pulses"
+ desc: "The actual time to hold SCL low between any two SCL pulses"
}
]
}
@@ -315,11 +316,11 @@
fields: [
{ bits: "15:0"
name: "TSU_STA"
- desc: "Minimum setup time for repeated start signals"
+ desc: "Actual setup time for repeated start signals"
}
{ bits: "31:16"
- name: "THD_ST"
- desc: "Minimum hold time for start signals"
+ name: "THD_STA"
+ desc: "Actual hold time for start signals"
}
]
}
@@ -333,12 +334,12 @@
fields: [
{ bits: "15:0"
name: "TSU_DAT"
- desc: "Minimum setup time for data (or ack) bits"
+ desc: "Actual setup time for data (or ack) bits"
}
{ bits: "31:16"
name: "THD_DAT"
desc: '''
- Minimum hold time for data (or ack) bits
+ Actual hold time for data (or ack) bits
(Note, where required, the parameters TVD_DAT is taken to be THD_DAT+T_F)
'''
}
@@ -354,11 +355,11 @@
fields: [
{ bits: "15:0"
name: "TSU_STO"
- desc: "Minimum setup time for stop signals"
+ desc: "Actual setup time for stop signals"
}
{ bits: "31:16"
name: "T_BUF"
- desc: "Minimum time between each STOP signal and the following START signal"
+ desc: "Actual time between each STOP signal and the following START signal"
}
]
}
diff --git a/hw/ip/i2c/i2c.core b/hw/ip/i2c/i2c.core
index 8c6d05c..7ab92dd 100644
--- a/hw/ip/i2c/i2c.core
+++ b/hw/ip/i2c/i2c.core
@@ -14,6 +14,7 @@
- rtl/i2c_reg_pkg.sv
- rtl/i2c_reg_top.sv
- rtl/i2c_core.sv
+ - rtl/i2c_fsm.sv
- rtl/i2c.sv
file_type: systemVerilogSource
diff --git a/hw/ip/i2c/rtl/i2c.sv b/hw/ip/i2c/rtl/i2c.sv
index 4dca14c..74a20c0 100644
--- a/hw/ip/i2c/rtl/i2c.sv
+++ b/hw/ip/i2c/rtl/i2c.sv
@@ -38,6 +38,9 @@
i2c_hw2reg_t hw2reg;
logic devmode;
+ logic scanmode_i;
+
+ assign scanmode_i = 1'b0;
i2c_reg_top u_reg (
.clk_i,
@@ -55,6 +58,7 @@
i2c_core i2c_core (
.clk_i,
.rst_ni,
+ .scanmode_i,
.reg2hw,
.hw2reg,
@@ -84,4 +88,6 @@
assign cio_scl_en_o = ~scl_int;
assign cio_sda_en_o = ~sda_int;
+ `ASSERT_KNOWN(scanmodeKnown, scanmode_i, clk_i, 0)
+
endmodule
diff --git a/hw/ip/i2c/rtl/i2c_core.sv b/hw/ip/i2c/rtl/i2c_core.sv
index b7dad63..8f99521 100644
--- a/hw/ip/i2c/rtl/i2c_core.sv
+++ b/hw/ip/i2c/rtl/i2c_core.sv
@@ -2,11 +2,12 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
-// Description: UART core module
+// Description: I2C core module
module i2c_core (
input clk_i,
input rst_ni,
+ input scanmode_i,
input i2c_reg_pkg::i2c_reg2hw_t reg2hw,
output i2c_reg_pkg::i2c_hw2reg_t hw2reg,
@@ -31,12 +32,14 @@
logic [15:0] tlow;
logic [15:0] t_r;
logic [15:0] t_f;
+ logic [15:0] thd_sta;
logic [15:0] tsu_sta;
logic [15:0] tsu_sto;
- logic [15:0] thd_st;
logic [15:0] tsu_dat;
logic [15:0] thd_dat;
logic [15:0] t_buf;
+ logic [30:0] stretch_timeout;
+ logic timeout_enable;
logic scl_out_fsm;
logic sda_out_fsm;
@@ -56,23 +59,53 @@
logic override;
+ logic fmt_fifo_rst_n;
+ logic fmt_fifo_wvalid;
+ logic fmt_fifo_wready;
+ logic [12:0] fmt_fifo_wdata;
+ logic [5:0] fmt_fifo_depth;
+ logic fmt_fifo_rvalid;
+ logic fmt_fifo_rready;
+ logic [12:0] fmt_fifo_rdata;
+ logic [7:0] fmt_byte;
+ logic fmt_flag_start_before;
+ logic fmt_flag_stop_after;
+ logic fmt_flag_read_bytes;
+ logic fmt_flag_read_continue;
+ logic fmt_flag_nak_ok;
+
+ logic [1:0] i2c_fifo_fmtilvl;
+ logic [2:0] i2c_fifo_rxilvl;
+
+ logic rx_fifo_rst_n;
+ logic rx_fifo_wvalid;
+ logic rx_fifo_wready;
+ logic [7:0] rx_fifo_wdata;
+ logic [5:0] rx_fifo_depth;
+ logic rx_fifo_rvalid;
+ logic rx_fifo_rready;
+ logic [7:0] rx_fifo_rdata;
+
+ logic host_idle;
+ logic target_idle;
+
+ // placeholder: no target functionality yet;
+ assign target_idle = 1'b1;
+
+ assign hw2reg.status.fmtfull.d = ~fmt_fifo_wready;
+ assign hw2reg.status.rxfull.d = ~rx_fifo_wready;
+ assign hw2reg.status.fmtempty.d = ~fmt_fifo_rvalid;
+ assign hw2reg.status.hostidle.d = host_idle;
+ assign hw2reg.status.targetidle.d = target_idle;
+ assign hw2reg.status.rxempty.d = ~rx_fifo_rvalid;
+ assign hw2reg.rdata.d = rx_fifo_rdata;
+ assign hw2reg.fifo_status.fmtlvl.d = fmt_fifo_depth;
+ assign hw2reg.fifo_status.rxlvl.d = rx_fifo_depth;
+ assign hw2reg.val.scl_rx.d = scl_rx_val;
+ assign hw2reg.val.sda_rx.d = sda_rx_val;
+
assign override = reg2hw.ovrd.txovrden;
- // placeholder until FSM in place
- assign sclout_fsm = 1'b0;
- assign sdaout_fsm = 1'b0;
-
- // placeholders for unused output registers
- assign hw2reg.status.fmtfull.d = 1'b0;
- assign hw2reg.status.rxfull.d = 1'b0;
- assign hw2reg.status.fmtempty.d = 1'b0;
- assign hw2reg.status.hostidle.d = 1'b1;
- assign hw2reg.status.targetidle.d = 1'b1;
- assign hw2reg.status.rxempty.d = 1'b0;
- assign hw2reg.fifo_status.fmtlvl.d = 5'b0;
- assign hw2reg.fifo_status.rxlvl.d = 5'b0;
-
-
assign scl_o = override ? reg2hw.ovrd.sclval : scl_out_fsm;
assign sda_o = override ? reg2hw.ovrd.sdaval : sda_out_fsm;
@@ -87,29 +120,146 @@
end
end
- assign hw2reg.val.scl_rx.d = scl_rx_val;
- assign hw2reg.val.sda_rx.d = sda_rx_val;
+ assign thigh = reg2hw.timing0.thigh.q;
+ assign tlow = reg2hw.timing0.tlow.q;
+ assign t_r = reg2hw.timing1.t_r.q;
+ assign t_f = reg2hw.timing1.t_f.q;
+ assign tsu_sta = reg2hw.timing2.tsu_sta.q;
+ assign thd_sta = reg2hw.timing2.thd_sta.q;
+ assign tsu_dat = reg2hw.timing3.tsu_dat.q;
+ assign thd_dat = reg2hw.timing3.thd_dat.q;
+ assign tsu_sto = reg2hw.timing4.tsu_sto.q;
+ assign t_buf = reg2hw.timing4.t_buf.q;
+ assign stretch_timeout = reg2hw.timeout_ctrl.val.q;
+ assign timeout_enable = reg2hw.timeout_ctrl.en.q;
- assign thigh = reg2hw.timing0.thigh.q;
- assign tlow = reg2hw.timing0.tlow.q;
- assign t_r = reg2hw.timing1.t_r.q;
- assign t_f = reg2hw.timing1.t_f.q;
- assign tsu_sta = reg2hw.timing2.tsu_sta.q;
- assign thd_st = reg2hw.timing2.thd_st.q;
- assign tsu_dat = reg2hw.timing3.tsu_dat.q;
- assign thd_dat = reg2hw.timing3.thd_dat.q;
- assign tsu_sto = reg2hw.timing4.tsu_sto.q;
- assign t_buf = reg2hw.timing4.t_buf.q;
+ assign i2c_fifo_fmtilvl = reg2hw.fifo_ctrl.fmtilvl.q;
+ assign i2c_fifo_rxilvl = reg2hw.fifo_ctrl.rxilvl.q;
- assign event_fmt_watermark = 1'b0;
- assign event_rx_watermark = 1'b0;
- assign event_fmt_overflow = 1'b0;
- assign event_rx_overflow = 1'b0;
- assign event_nak = 1'b0;
- assign event_scl_interference = 1'b0;
- assign event_sda_interference = 1'b0;
- assign event_stretch_timeout = 1'b0;
- assign event_sda_unstable = 1'b0;
+ always_comb begin
+ unique case(i2c_fifo_fmtilvl)
+ 2'h0: event_fmt_watermark = (fmt_fifo_depth <= 6'd1);
+ 2'h1: event_fmt_watermark = (fmt_fifo_depth <= 6'd4);
+ 2'h2: event_fmt_watermark = (fmt_fifo_depth <= 6'd8);
+ default: event_fmt_watermark = (fmt_fifo_depth <= 6'd16);
+ endcase
+ end
+
+ always_comb begin
+ unique case(i2c_fifo_rxilvl)
+ 3'h0: event_rx_watermark = (rx_fifo_depth >= 6'd1);
+ 3'h1: event_rx_watermark = (rx_fifo_depth >= 6'd4);
+ 3'h2: event_rx_watermark = (rx_fifo_depth >= 6'd8);
+ 3'h3: event_rx_watermark = (rx_fifo_depth >= 6'd16);
+ 3'h4: event_rx_watermark = (rx_fifo_depth >= 6'd30);
+ default: event_rx_watermark = 1'b0;
+ endcase
+ end
+
+ assign event_fmt_overflow = fmt_fifo_wvalid & ~fmt_fifo_wready;
+ assign event_rx_overflow = rx_fifo_wvalid & ~rx_fifo_wready;
+
+
+
+ // The fifo write enable is controlled entirely
+ // by the fbyte field qe bit.
+ // When all fbyte.qe is asserted the fbyte, and all forma flags
+ // are injected into the fifo. (i.e. the qe bits for the flags have no effect).
+ assign fmt_fifo_wvalid = reg2hw.fdata.fbyte.qe;
+ assign fmt_fifo_wdata[7:0] = reg2hw.fdata.fbyte.q;
+ assign fmt_fifo_wdata[8] = reg2hw.fdata.start.q;
+ assign fmt_fifo_wdata[9] = reg2hw.fdata.stop.q;
+ assign fmt_fifo_wdata[10] = reg2hw.fdata.read.q;
+ assign fmt_fifo_wdata[11] = reg2hw.fdata.rcont.q;
+ assign fmt_fifo_wdata[12] = reg2hw.fdata.nakok.q;
+
+ assign fmt_byte = fmt_fifo_rdata[7:0];
+ assign fmt_flag_start_before = fmt_fifo_rdata[8];
+ assign fmt_flag_stop_after = fmt_fifo_rdata[9];
+ assign fmt_flag_read_continue = fmt_fifo_rdata[10];
+ assign fmt_flag_read_bytes = fmt_fifo_rdata[11];
+ assign fmt_flag_nak_ok = fmt_fifo_rdata[12];
+
+ assign fmt_fifo_rst_n = scanmode_i ? rst_ni : (rst_ni & ~reg2hw.fifo_ctrl.fmtrst.q);
+
+ prim_fifo_sync #(
+ .Width(13),
+ .Pass(1'b1),
+ .Depth(32)
+ ) u_i2c_fmtfifo (
+ .clk_i,
+ .rst_ni(fmt_fifo_rst_n),
+ .wvalid(fmt_fifo_wen),
+ .wready(fmt_fifo_wready),
+ .wdata(fmt_fifo_wdata),
+ .depth(fmt_fifo_depth),
+ .rvalid(fmt_fifo_rvalid),
+ .rready(fmt_fifo_rready),
+ .rdata(fmt_fifo_rdata)
+ );
+
+ assign rx_fifo_rready = reg2hw.rdata.re;
+ assign rx_fifo_rst_n = scanmode_i ? rst_ni : (rst_ni & ~reg2hw.fifo_ctrl.rxrst.q);
+
+ prim_fifo_sync #(
+ .Width(8),
+ .Pass(1'b0),
+ .Depth(32)
+ ) u_i2c_rxfifo (
+ .clk_i,
+ .rst_ni(rx_fifo_rst_n),
+ .wvalid(rx_fifo_wvalid),
+ .wready(rx_fifo_wready),
+ .wdata(rx_fifo_wdata),
+ .depth(rx_fifo_depth),
+ .rvalid(rx_fifo_rvalid),
+ .rready(rx_fifo_rready),
+ .rdata(rx_fifo_rdata)
+ );
+
+ i2c_fsm u_i2c_fsm (
+ .clk_i,
+ .rst_ni,
+
+ .scl_i,
+ .scl_o(scl_out_fsm),
+ .sda_i,
+ .sda_o(sda_out_fsm),
+
+ .fmt_fifo_rvalid,
+ .fmt_fifo_rready,
+
+ .fmt_byte,
+ .fmt_flag_start_before,
+ .fmt_flag_stop_after,
+ .fmt_flag_read_bytes,
+ .fmt_flag_read_continue,
+ .fmt_flag_nak_ok,
+
+ .rx_fifo_wvalid,
+ .rx_fifo_wdata,
+
+ .host_idle,
+
+ .thigh,
+ .tlow,
+ .t_r,
+ .t_f,
+ .thd_sta,
+ .tsu_sta,
+ .tsu_sto,
+ .tsu_dat,
+ .thd_dat,
+ .t_buf,
+ .stretch_timeout,
+ .timeout_enable,
+
+ .event_nak,
+ .event_scl_interference,
+ .event_sda_interference,
+ .event_stretch_timeout,
+ .event_sda_unstable
+ );
prim_intr_hw #(.Width(1)) intr_hw_fmt_watermark (
.event_intr_i (event_fmt_watermark),
diff --git a/hw/ip/i2c/rtl/i2c_fsm.sv b/hw/ip/i2c/rtl/i2c_fsm.sv
new file mode 100644
index 0000000..ca0f438
--- /dev/null
+++ b/hw/ip/i2c/rtl/i2c_fsm.sv
@@ -0,0 +1,63 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Description: I2C finite state machine
+
+module i2c_fsm (
+ input clk_i,
+ input rst_ni,
+
+ input scl_i,
+ output scl_o,
+ input sda_i,
+ output sda_o,
+
+ input fmt_fifo_rvalid,
+ output fmt_fifo_rready,
+ input [7:0] fmt_byte,
+ input fmt_flag_start_before,
+ input fmt_flag_stop_after,
+ input fmt_flag_read_bytes,
+ input fmt_flag_read_continue,
+ input fmt_flag_nak_ok,
+
+ output rx_fifo_wvalid,
+ output [7:0] rx_fifo_wdata,
+
+ output host_idle,
+
+ input [15:0] thigh,
+ input [15:0] tlow,
+ input [15:0] t_r,
+ input [15:0] t_f,
+ input [15:0] thd_sta,
+ input [15:0] tsu_sta,
+ input [15:0] tsu_sto,
+ input [15:0] tsu_dat,
+ input [15:0] thd_dat,
+ input [15:0] t_buf,
+ input [30:0] stretch_timeout,
+ input timeout_enable,
+
+ output event_nak,
+ output event_scl_interference,
+ output event_sda_interference,
+ output event_stretch_timeout,
+ output event_sda_unstable
+);
+
+ // PLACEHOLDER IO
+ assign scl_o = 1'b0;
+ assign sda_o = 1'b0;
+ assign fmt_fifo_rready = 1'b0;
+ assign rx_fifo_wvalid = 1'b0;
+ assign rx_fifo_wdata = 8'h00;
+
+ assign event_nak = 1'b0;
+ assign event_scl_interference = 1'b0;
+ assign event_sda_interference = 1'b0;
+ assign event_stretch_timeout = 1'b0;
+ assign event_sda_unstable = 1'b0;
+
+endmodule;
diff --git a/hw/ip/i2c/rtl/i2c_reg_pkg.sv b/hw/ip/i2c/rtl/i2c_reg_pkg.sv
index bb0a305..02eb1a7 100644
--- a/hw/ip/i2c/rtl/i2c_reg_pkg.sv
+++ b/hw/ip/i2c/rtl/i2c_reg_pkg.sv
@@ -215,7 +215,7 @@
} tsu_sta;
struct packed {
logic [15:0] q; // [111:96]
- } thd_st;
+ } thd_sta;
} timing2;
struct packed {
struct packed {
@@ -248,63 +248,66 @@
struct packed {
struct packed {
+ logic d; // [75]
+ logic de; // [74]
+ } fmt_watermark;
+ struct packed {
+ logic d; // [73]
+ logic de; // [72]
+ } rx_watermark;
+ struct packed {
+ logic d; // [71]
+ logic de; // [70]
+ } fmt_overflow;
+ struct packed {
+ logic d; // [69]
+ logic de; // [68]
+ } rx_overflow;
+ struct packed {
logic d; // [67]
logic de; // [66]
- } fmt_watermark;
+ } nak;
struct packed {
logic d; // [65]
logic de; // [64]
- } rx_watermark;
+ } scl_interference;
struct packed {
logic d; // [63]
logic de; // [62]
- } fmt_overflow;
+ } sda_interference;
struct packed {
logic d; // [61]
logic de; // [60]
- } rx_overflow;
+ } stretch_timeout;
struct packed {
logic d; // [59]
logic de; // [58]
- } nak;
- struct packed {
- logic d; // [57]
- logic de; // [56]
- } scl_interference;
- struct packed {
- logic d; // [55]
- logic de; // [54]
- } sda_interference;
- struct packed {
- logic d; // [53]
- logic de; // [52]
- } stretch_timeout;
- struct packed {
- logic d; // [51]
- logic de; // [50]
} sda_unstable;
} intr_state;
struct packed {
struct packed {
- logic d; // [49]
+ logic d; // [57]
} fmtfull;
struct packed {
- logic d; // [48]
+ logic d; // [56]
} rxfull;
struct packed {
- logic d; // [47]
+ logic d; // [55]
} fmtempty;
struct packed {
- logic d; // [46]
+ logic d; // [54]
} hostidle;
struct packed {
- logic d; // [45]
+ logic d; // [53]
} targetidle;
struct packed {
- logic d; // [44]
+ logic d; // [52]
} rxempty;
} status;
struct packed {
+ logic [7:0] d; // [51:44]
+ } rdata;
+ struct packed {
struct packed {
logic [5:0] d; // [43:38]
} fmtlvl;
diff --git a/hw/ip/i2c/rtl/i2c_reg_top.sv b/hw/ip/i2c/rtl/i2c_reg_top.sv
index e53f879..86e99d9 100644
--- a/hw/ip/i2c/rtl/i2c_reg_top.sv
+++ b/hw/ip/i2c/rtl/i2c_reg_top.sv
@@ -5,9 +5,7 @@
// Register Top module auto-generated by `reggen`
-module i2c_reg_top #(
- parameter logic LifeCycle = 1'b0 // If 0b, assume devmode 1b always
-) (
+module i2c_reg_top (
input clk_i,
input rst_ni,
@@ -67,30 +65,7 @@
);
assign reg_rdata = reg_rdata_next ;
-
- // Ignore devmode_i if this register module isn't used in LifeCycle managed IP
- // And mandate to return error for address miss
-
- logic devmode ;
- assign devmode = LifeCycle ? devmode_i : 1'b1;
-
- assign reg_error = (devmode & addrmiss) | wr_err ;
-
- // TODO(eunchan): Revise Register Interface logic after REG INTF finalized
- // TODO(eunchan): Make concrete scenario
- // 1. Write: No response, so that it can guarantee a request completes a clock after we
- // It means, bus_reg_ready doesn't have to be lowered.
- // 2. Read: response. So bus_reg_ready should assert after reg_bus_valid & reg_bus_ready
- // _____ _____
- // a_valid _____/ \_______/ \______
- // ___________ _____
- // a_ready \_______/ \______ <- ERR though no logic malfunction
- // _____________
- // d_valid ___________/ \______
- // _____
- // d_ready ___________________/ \______
- //
- // Above example is fine but if r.b.r doesn't assert within two cycle, then it can be wrong.
+ assign reg_error = (devmode_i & addrmiss) | wr_err ;
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
@@ -238,9 +213,9 @@
logic [15:0] timing2_tsu_sta_qs;
logic [15:0] timing2_tsu_sta_wd;
logic timing2_tsu_sta_we;
- logic [15:0] timing2_thd_st_qs;
- logic [15:0] timing2_thd_st_wd;
- logic timing2_thd_st_we;
+ logic [15:0] timing2_thd_sta_qs;
+ logic [15:0] timing2_thd_sta_wd;
+ logic timing2_thd_sta_we;
logic [15:0] timing3_tsu_dat_qs;
logic [15:0] timing3_tsu_dat_wd;
logic timing3_tsu_dat_we;
@@ -997,7 +972,7 @@
.re (rdata_re),
.we (1'b0),
.wd ('0),
- .d ('0),
+ .d (hw2reg.rdata.d),
.qre (reg2hw.rdata.re),
.qe (),
.q (reg2hw.rdata.q ),
@@ -1541,18 +1516,18 @@
);
- // F[thd_st]: 31:16
+ // F[thd_sta]: 31:16
prim_subreg #(
.DW (16),
.SWACCESS("RW"),
.RESVAL (16'h0)
- ) u_timing2_thd_st (
+ ) u_timing2_thd_sta (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
- .we (timing2_thd_st_we),
- .wd (timing2_thd_st_wd),
+ .we (timing2_thd_sta_we),
+ .wd (timing2_thd_sta_wd),
// from internal hardware
.de (1'b0),
@@ -1560,10 +1535,10 @@
// to internal hardware
.qe (),
- .q (reg2hw.timing2.thd_st.q ),
+ .q (reg2hw.timing2.thd_sta.q ),
// to register interface (read)
- .qs (timing2_thd_st_qs)
+ .qs (timing2_thd_sta_qs)
);
@@ -1936,8 +1911,8 @@
assign timing2_tsu_sta_we = addr_hit[13] & reg_we & ~wr_err;
assign timing2_tsu_sta_wd = reg_wdata[15:0];
- assign timing2_thd_st_we = addr_hit[13] & reg_we & ~wr_err;
- assign timing2_thd_st_wd = reg_wdata[31:16];
+ assign timing2_thd_sta_we = addr_hit[13] & reg_we & ~wr_err;
+ assign timing2_thd_sta_wd = reg_wdata[31:16];
assign timing3_tsu_dat_we = addr_hit[14] & reg_we & ~wr_err;
assign timing3_tsu_dat_wd = reg_wdata[15:0];
@@ -2058,7 +2033,7 @@
addr_hit[13]: begin
reg_rdata_next[15:0] = timing2_tsu_sta_qs;
- reg_rdata_next[31:16] = timing2_thd_st_qs;
+ reg_rdata_next[31:16] = timing2_thd_sta_qs;
end
addr_hit[14]: begin
