[csrng/dv] parameter move, dv plan, checklist, checklist
Signed-off-by: Steve Nelson <steve.nelson@wdc.com>
diff --git a/hw/ip/csrng/data/csrng_testplan.hjson b/hw/ip/csrng/data/csrng_testplan.hjson
index 732edf5..07ee385 100644
--- a/hw/ip/csrng/data/csrng_testplan.hjson
+++ b/hw/ip/csrng/data/csrng_testplan.hjson
@@ -24,7 +24,7 @@
Verify regen bit enables/disables write access to control registers
'''
milestone: V2
- tests: ["csrng_firmware"]
+ tests: []
}
{
name: interrupts
@@ -32,7 +32,7 @@
Verify all csrng interrupts assert/clear when expected.
'''
milestone: V2
- tests: ["csrng_interrupts"]
+ tests: []
}
{
name: cmds
@@ -43,7 +43,7 @@
Verify for multiple hw app interfaces running in parallel.
'''
milestone: V2
- tests: ["csrng_cmds"]
+ tests: []
}
{
name: genbits
@@ -53,7 +53,7 @@
Verify for multiple hw app interfaces running in parallel.
'''
milestone: V2
- tests: ["csrng_genbits"]
+ tests: []
}
{
name: stress_all
diff --git a/hw/ip/csrng/doc/checklist.md b/hw/ip/csrng/doc/checklist.md
index 8d1fee4..921352c 100644
--- a/hw/ip/csrng/doc/checklist.md
+++ b/hw/ip/csrng/doc/checklist.md
@@ -115,24 +115,24 @@
Type | Item | Resolution | Note/Collaterals
--------------|---------------------------------------|-------------|------------------
-Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [CSRNG DV document]({{<relref "hw/ip/csrng/doc/dv" >}})
-Documentation | [DV_PLAN_COMPLETED][] | Not Started | [CSRNG DV plan]({{<relref "hw/ip/csrng/doc/dv/index.md#dv_plan" >}})
-Testbench | [TB_TOP_CREATED][] | Not Started |
-Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Not Started |
-Testbench | [SIM_TB_ENV_CREATED][] | Not Started |
-Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Not Started |
-Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Not Started |
-Testbench | [TB_GEN_AUTOMATED][] | Not Started |
-Tests | [SIM_SMOKE_TEST_PASSING][] | Not Started |
-Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Not Started |
-Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | Not Started |
-Tool Setup | [SIM_ALT_TOOL_SETUP][] | Not Started |
-Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Not Started |
-Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Not Started |
-Regression | [FPV_REGRESSION_SETUP][] | Not Started |
-Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Not Started |
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Done | [CSRNG DV document]({{<relref "hw/ip/csrng/doc/dv" >}})
+Documentation | [DV_PLAN_COMPLETED][] | Done | [CSRNG DV plan]({{<relref "hw/ip/csrng/doc/dv/index.md#dv_plan" >}})
+Testbench | [TB_TOP_CREATED][] | Done |
+Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Done |
+Testbench | [SIM_TB_ENV_CREATED][] | Done |
+Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Done |
+Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Done |
+Testbench | [TB_GEN_AUTOMATED][] | Done |
+Tests | [SIM_SMOKE_TEST_PASSING][] | Done |
+Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Done |
+Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | N/A |
+Tool Setup | [SIM_ALT_TOOL_SETUP][] | Done | Xcelium (signoff), VCS (alt)
+Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Done |
+Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Done |
+Regression | [FPV_REGRESSION_SETUP][] | N/A |
+Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Done |
Code Quality | [TB_LINT_SETUP][] | Done |
-Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Not Started |
+Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | N/A |
Review | [DESIGN_SPEC_REVIEWED][] | Not Started |
Review | [DV_PLAN_REVIEWED][] | Not Started |
Review | [STD_TEST_CATEGORIES_PLANNED][] | Not Started | Exception (?)
diff --git a/hw/ip/csrng/doc/dv/index.md b/hw/ip/csrng/doc/dv/index.md
index 85ee264..ad3169e 100644
--- a/hw/ip/csrng/doc/dv/index.md
+++ b/hw/ip/csrng/doc/dv/index.md
@@ -11,7 +11,7 @@
## Current status
* [Design & verification stage]({{< relref "hw" >}})
- * [HW development stages]({{< relref "doc/project/development_stages" >}})
+* [HW development stages]({{< relref "doc/project/development_stages" >}})
* [Simulation results](https://reports.opentitan.org/hw/ip/csrng/dv/latest/results.html)
## Design features
@@ -21,7 +21,7 @@
CSRNG testbench has been constructed based on the [CIP testbench architecture]({{< relref "hw/dv/sv/cip_lib/doc" >}}).
### Block diagram
-
+
### Top level testbench
Top level testbench is located at `hw/ip/csrng/dv/tb/tb.sv`. It instantiates the CSRNG DUT module `hw/ip/csrng/rtl/csrng.sv`.
@@ -39,15 +39,17 @@
* [dv_utils_pkg]({{< relref "hw/dv/sv/dv_utils/README.md" >}})
* [csr_utils_pkg]({{< relref "hw/dv/sv/csr_utils/README.md" >}})
-### Compile-time configurations
+<!--### Compile-time configurations
[list compile time configurations, if any and what are they used for]
+TODO-->
### Global types & methods
All common types and methods defined at the package level can be found in
`csrng_env_pkg`. Some of them in use are:
```systemverilog
-[list a few parameters, types & methods; no need to mention all]
```
+<!--TODO [list a few parameters, types & methods; no need to mention all]-->
+
### TL_agent
CSRNG testbench instantiates (already handled in CIP base env) [tl_agent]({{< relref "hw/dv/sv/tl_agent/README.md" >}})
which provides the ability to drive and independently monitor random traffic via
@@ -96,5 +98,4 @@
```
## DV plan
-<!-- TODO: uncomment the line below after adding the DV plan -->
-{{</* testplan "hw/ip/csrng/data/csrng_testplan.hjson" */>}}
+{{< testplan "hw/ip/csrng/data/csrng_testplan.hjson" >}}
diff --git a/hw/ip/csrng/dv/env/csrng_env.core b/hw/ip/csrng/dv/env/csrng_env.core
index 278e396..7907717 100644
--- a/hw/ip/csrng/dv/env/csrng_env.core
+++ b/hw/ip/csrng/dv/env/csrng_env.core
@@ -10,6 +10,7 @@
- lowrisc:dv:ralgen
- lowrisc:dv:cip_lib
- lowrisc:dv:push_pull_agent
+ - lowrisc:dv:entropy_src_env
files:
- csrng_env_pkg.sv
- csrng_env_cfg.sv: {is_include_file: true}
diff --git a/hw/ip/csrng/dv/env/csrng_env.sv b/hw/ip/csrng/dv/env/csrng_env.sv
index 2f76695..b8052cc 100644
--- a/hw/ip/csrng/dv/env/csrng_env.sv
+++ b/hw/ip/csrng/dv/env/csrng_env.sv
@@ -10,18 +10,17 @@
);
`uvm_component_utils(csrng_env)
- push_pull_agent#(.HostDataWidth(entropy_src_pkg::FIPS_CSRNG_BUS_WIDTH)) m_entropy_src_agent;
+ push_pull_agent#(.HostDataWidth(entropy_src_env_pkg::FIPS_CSRNG_BUS_WIDTH)) m_entropy_src_agent;
`uvm_component_new
function void build_phase(uvm_phase phase);
super.build_phase(phase);
// create components
- m_entropy_src_agent = push_pull_agent#(.HostDataWidth(entropy_src_pkg::FIPS_CSRNG_BUS_WIDTH))::
- type_id::create("m_entropy_src_agent", this);
- uvm_config_db#(push_pull_agent_cfg#(.HostDataWidth(entropy_src_pkg::FIPS_CSRNG_BUS_WIDTH)))::
- set(this, "m_entropy_src_agent*", "cfg",
- cfg.m_entropy_src_agent_cfg);
+ m_entropy_src_agent = push_pull_agent#(.HostDataWidth(entropy_src_env_pkg::FIPS_CSRNG_BUS_WIDTH))
+ ::type_id::create("m_entropy_src_agent", this);
+ uvm_config_db#(push_pull_agent_cfg#(.HostDataWidth(entropy_src_env_pkg::FIPS_CSRNG_BUS_WIDTH)))
+ ::set(this, "m_entropy_src_agent*", "cfg", cfg.m_entropy_src_agent_cfg);
cfg.m_entropy_src_agent_cfg.agent_type = push_pull_agent_pkg::PullAgent;
cfg.m_entropy_src_agent_cfg.if_mode = dv_utils_pkg::Device;
@@ -34,7 +33,7 @@
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
if (cfg.en_scb) begin
- m_entropy_src_agent.monitor.analysis_port.connect(scoreboard.push_pull_fifo.analysis_export);
+ m_entropy_src_agent.monitor.analysis_port.connect(scoreboard.entropy_src_fifo.analysis_export);
end
if (cfg.is_active && cfg.m_entropy_src_agent_cfg.is_active) begin
virtual_sequencer.entropy_src_sequencer_h = m_entropy_src_agent.sequencer;
diff --git a/hw/ip/csrng/dv/env/csrng_env_cfg.sv b/hw/ip/csrng/dv/env/csrng_env_cfg.sv
index 6173cab..340ac51 100644
--- a/hw/ip/csrng/dv/env/csrng_env_cfg.sv
+++ b/hw/ip/csrng/dv/env/csrng_env_cfg.sv
@@ -5,7 +5,7 @@
class csrng_env_cfg extends cip_base_env_cfg #(.RAL_T(csrng_reg_block));
// ext component cfgs
- rand push_pull_agent_cfg#(.HostDataWidth(entropy_src_pkg::FIPS_CSRNG_BUS_WIDTH))
+ rand push_pull_agent_cfg#(.HostDataWidth(entropy_src_env_pkg::FIPS_CSRNG_BUS_WIDTH))
m_entropy_src_agent_cfg;
virtual pins_if efuse_sw_app_enable_vif;
@@ -19,9 +19,8 @@
virtual function void initialize(bit [31:0] csr_base_addr = '1);
super.initialize(csr_base_addr);
// create push_pull agent config obj
- m_entropy_src_agent_cfg = push_pull_agent_cfg#(.HostDataWidth(entropy_src_pkg::
- FIPS_CSRNG_BUS_WIDTH))::type_id::create
- ("m_entropy_src_agent_cfg");
+ m_entropy_src_agent_cfg = push_pull_agent_cfg#(.HostDataWidth(entropy_src_env_pkg::
+ FIPS_CSRNG_BUS_WIDTH))::type_id::create("m_entropy_src_agent_cfg");
// set num_interrupts & num_alerts
begin
diff --git a/hw/ip/csrng/dv/env/csrng_env_pkg.sv b/hw/ip/csrng/dv/env/csrng_env_pkg.sv
index feaedf0..ab9b9be 100644
--- a/hw/ip/csrng/dv/env/csrng_env_pkg.sv
+++ b/hw/ip/csrng/dv/env/csrng_env_pkg.sv
@@ -19,7 +19,7 @@
`include "dv_macros.svh"
// parameters
- parameter uint NUMHWAPPS = 2;
+ parameter uint NUM_HW_APPS = 1;
parameter bit [TL_DW-1:0] [3:0] ZERO_SEED_GENBITS = {32'h0,
32'h0,
32'h0,
diff --git a/hw/ip/csrng/dv/env/csrng_scoreboard.sv b/hw/ip/csrng/dv/env/csrng_scoreboard.sv
index 2b9033f..8dd49f6 100644
--- a/hw/ip/csrng/dv/env/csrng_scoreboard.sv
+++ b/hw/ip/csrng/dv/env/csrng_scoreboard.sv
@@ -12,18 +12,18 @@
// local variables
// TLM agent fifos
- uvm_tlm_analysis_fifo#(push_pull_item#(.HostDataWidth(entropy_src_pkg::FIPS_CSRNG_BUS_WIDTH)))
- push_pull_fifo;
+ uvm_tlm_analysis_fifo#(push_pull_item#(.HostDataWidth(entropy_src_env_pkg::FIPS_CSRNG_BUS_WIDTH)))
+ entropy_src_fifo;
// local queues to hold incoming packets pending comparison
- push_pull_item#(.HostDataWidth(entropy_src_pkg::FIPS_CSRNG_BUS_WIDTH))
- push_pull_q[$];
+ push_pull_item#(.HostDataWidth(entropy_src_env_pkg::FIPS_CSRNG_BUS_WIDTH))
+ entropy_src_q[$];
`uvm_component_new
function void build_phase(uvm_phase phase);
super.build_phase(phase);
- push_pull_fifo = new("push_pull_fifo", this);
+ entropy_src_fifo = new("entropy_src_fifo", this);
endfunction
function void connect_phase(uvm_phase phase);
@@ -38,10 +38,10 @@
endtask
virtual task process_push_pull_fifo();
- push_pull_item#(.HostDataWidth(entropy_src_pkg::FIPS_CSRNG_BUS_WIDTH)) item;
+ push_pull_item#(.HostDataWidth(entropy_src_env_pkg::FIPS_CSRNG_BUS_WIDTH)) item;
forever begin
- push_pull_fifo.get(item);
- `uvm_info(`gfn, $sformatf("received push_pull item:\n%0s", item.sprint()), UVM_HIGH)
+ entropy_src_fifo.get(item);
+ `uvm_info(`gfn, $sformatf("received item:\n%0s", item.sprint()), UVM_HIGH)
end
endtask
diff --git a/hw/ip/csrng/dv/env/csrng_virtual_sequencer.sv b/hw/ip/csrng/dv/env/csrng_virtual_sequencer.sv
index 58f855d..671f3c1 100644
--- a/hw/ip/csrng/dv/env/csrng_virtual_sequencer.sv
+++ b/hw/ip/csrng/dv/env/csrng_virtual_sequencer.sv
@@ -8,7 +8,7 @@
);
`uvm_component_utils(csrng_virtual_sequencer)
- push_pull_sequencer#(.HostDataWidth(entropy_src_pkg::FIPS_CSRNG_BUS_WIDTH))
+ push_pull_sequencer#(.HostDataWidth(entropy_src_env_pkg::FIPS_CSRNG_BUS_WIDTH))
entropy_src_sequencer_h;
`uvm_component_new
diff --git a/hw/ip/csrng/dv/tb.sv b/hw/ip/csrng/dv/tb.sv
index f95385f..f848abf 100644
--- a/hw/ip/csrng/dv/tb.sv
+++ b/hw/ip/csrng/dv/tb.sv
@@ -27,10 +27,10 @@
pins_if#(1) devmode_if(devmode);
pins_if#(1) efuse_sw_app_enable_if(efuse_sw_app_enable);
tl_if tl_if(.clk(clk), .rst_n(rst_n));
- push_pull_if#(.HostDataWidth(entropy_src_pkg::FIPS_CSRNG_BUS_WIDTH)) entropy_src_if();
+ push_pull_if#(.HostDataWidth(entropy_src_env_pkg::FIPS_CSRNG_BUS_WIDTH)) entropy_src_if();
// dut
- csrng#(.NumHwApps(NUMHWAPPS)) dut (
+ csrng#(.NHwApps(NUM_HW_APPS)) dut (
.clk_i (clk ),
.rst_ni (rst_n ),
@@ -40,7 +40,7 @@
.efuse_sw_app_enable_i (efuse_sw_app_enable),
// TODO: Use parameter?
- .lc_dft_en_i (4'b1010),
+ .lc_hw_debug_en_i (4'b1010),
.entropy_src_hw_if_o (entropy_src_if.req),
.entropy_src_hw_if_i ({entropy_src_if.ack, entropy_src_if.h_data[entropy_src_pkg::
@@ -70,7 +70,7 @@
uvm_config_db#(virtual pins_if)::set(null, "*.env", "efuse_sw_app_enable_vif",
efuse_sw_app_enable_if);
uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_if);
- uvm_config_db#(virtual push_pull_if#(.HostDataWidth(entropy_src_pkg::FIPS_CSRNG_BUS_WIDTH)))::set
+ uvm_config_db#(virtual push_pull_if#(.HostDataWidth(entropy_src_env_pkg::FIPS_CSRNG_BUS_WIDTH)))::set
(null, "*.env.m_entropy_src_agent*", "vif", entropy_src_if);
$timeformat(-12, 0, " ps", 12);
run_test();
diff --git a/hw/ip/entropy_src/dv/tb/tb.sv b/hw/ip/entropy_src/dv/tb/tb.sv
index 6a067c2..36d06d2 100755
--- a/hw/ip/entropy_src/dv/tb/tb.sv
+++ b/hw/ip/entropy_src/dv/tb/tb.sv
@@ -25,9 +25,9 @@
pins_if#(1) efuse_es_sw_reg_en_if(efuse_es_sw_reg_en);
tl_if tl_if(.clk(clk), .rst_n(rst_n));
push_pull_if#(.HostDataWidth(entropy_src_pkg::RNG_BUS_WIDTH))
- rng_if(.clk(clk), .rst_n(rst_n));
+ rng_if(.clk(clk), .rst_n(rst_n));
push_pull_if#(.HostDataWidth(FIPS_CSRNG_BUS_WIDTH))
- csrng_if(.clk(clk), .rst_n(rst_n));
+ csrng_if(.clk(clk), .rst_n(rst_n));
`DV_ALERT_IF_CONNECT
diff --git a/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson b/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson
index a40d37c..3ff15c5 100644
--- a/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson
+++ b/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson
@@ -14,6 +14,7 @@
use_cfgs: ["{proj_root}/hw/ip/aes/dv/aes_sim_cfg.hjson",
"{proj_root}/hw/ip/entropy_src/dv/entropy_src_sim_cfg.hjson",
+ "{proj_root}/hw/ip/csrng/dv/csrng_sim_cfg.hjson",
"{proj_root}/hw/ip/flash_ctrl/dv/flash_ctrl_sim_cfg.hjson",
"{proj_root}/hw/ip/gpio/dv/gpio_sim_cfg.hjson",
"{proj_root}/hw/ip/hmac/dv/hmac_sim_cfg.hjson",
diff --git a/util/build_docs.py b/util/build_docs.py
index 9f4244f..99a851e 100755
--- a/util/build_docs.py
+++ b/util/build_docs.py
@@ -95,6 +95,7 @@
"hw/ip/aes/data/aes_testplan.hjson",
"hw/ip/alert_handler/data/alert_handler_testplan.hjson",
"hw/ip/entropy_src/data/entropy_src_testplan.hjson",
+ "hw/ip/csrng/data/csrng_testplan.hjson",
"hw/ip/flash_ctrl/data/flash_ctrl_testplan.hjson",
"hw/ip/gpio/data/gpio_testplan.hjson",
"hw/ip/hmac/data/hmac_testplan.hjson",
