[prim] More refactoring to remove UNR generation
- the old design had the term `dst_update_i & dst_latch_d`.
- the UNR tool determined the case where dst_update_i = 0 and dst_latch_d = 1 does not exist.
- this is true, because the conditions that would `dst_latch_d` to become 1 would also always lead
to dst_update_i to be true. However, writing the terms as the above makes the intent clearer.
- re-write the code a bit to indicate the actual scenario that occurs, and also add a couple of
assertiosn to ensure the original spirit of the design is always met.
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/prim/rtl/prim_reg_cdc_arb.sv b/hw/ip/prim/rtl/prim_reg_cdc_arb.sv
index 311e750..d804df8 100644
--- a/hw/ip/prim/rtl/prim_reg_cdc_arb.sv
+++ b/hw/ip/prim/rtl/prim_reg_cdc_arb.sv
@@ -152,13 +152,24 @@
id_q <= SelSwReq;
end else if (dst_req && dst_lat_d) begin
id_q <= SelSwReq;
- end else if (dst_update_i && dst_lat_d) begin
+ end else if (!dst_req && dst_lat_d) begin
id_q <= SelHwReq;
end else if (dst_lat_q) begin
id_q <= SelHwReq;
end
end
+ // if a destination update is received when the system is idle and there is no
+ // software side request, hw update must be selected.
+ `ASSERT(DstUpdateReqCheck_A, ##1 dst_update_i & !dst_req & !busy |=> id_q == SelHwReq,
+ clk_dst_i, !rst_dst_ni)
+
+ // if hw select was chosen, then it must be the case there was a destination update
+ // indication
+ `ASSERT(HwIdSelCheck_A, $rose(id_q == SelHwReq) |-> $past(dst_update_i, 1),
+ clk_dst_i, !rst_dst_ni)
+
+
// send out prim_subreg request only when proceeding
// with software request
assign dst_req_o = ~busy & dst_req;
@@ -224,11 +235,9 @@
assign src_ack_o = src_req & (id_q == SelSwReq);
assign src_update_o = src_req & (id_q == SelHwReq);
- `ifdef INC_ASSERT
- // once hardware makes an update request, we must eventually see an update pulse
- `ASSERT(ReqTimeout_A, $rose(id_q == SelHwReq) |-> s_eventually src_update_o,
- clk_src_i, !rst_src_ni)
- `endif
+ // once hardware makes an update request, we must eventually see an update pulse
+ `ASSERT(ReqTimeout_A, $rose(id_q == SelHwReq) |-> s_eventually src_update_o,
+ clk_src_i, !rst_src_ni)
`ifdef INC_ASSERT
logic async_flag;
