| commit | 8c925edc495202874632fbc138b6bff3b343dcfd | [log] [tgz] |
|---|---|---|
| author | Cindy Chen <chencindy@google.com> | Tue Jun 16 12:15:59 2020 -0700 |
| committer | cindychip <cindy.chen0316@gmail.com> | Tue Jun 16 14:53:06 2020 -0700 |
| tree | 40b4bd0fc70260ca6af89e927434994269f24279 | |
| parent | 0e15a661577b51daf2c0ee4e7ee70253fbc6acf6 [diff] |
[alert/dv] fix priority when ping_ok and timeout triggered same cycle In RTL, when ping_ok and timeout happened at the same clk cycle, design will still trigger the timeout alert. Testbench follows this rule but did not count for corner case: where ping_ok is triggered by real esc_p/n happened during ping. This PR fixed this corner case. Signed-off-by: Cindy Chen <chencindy@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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