[ip/spi_device] Remove redundant interrupts
- Removed Async TX Empty, Full, Async RX Not Empty interrupts
- Revised the description of Async FIFO Pop
This is related to #5
diff --git a/hw/ip/spi_device/doc/spi_device.hjson b/hw/ip/spi_device/doc/spi_device.hjson
index 3c11b8a..d464511 100644
--- a/hw/ip/spi_device/doc/spi_device.hjson
+++ b/hw/ip/spi_device/doc/spi_device.hjson
@@ -13,13 +13,12 @@
{ name: "miso", desc: "SPI Output" },
],
interrupt_list: [
- { name: "rxne", desc: "RX SRAM FIFO is not empty" },
+ { name: "rxf", desc: "RX SRAM FIFO Full" },
{ name: "rxlvl", desc: "RX SRAM FIFO is above the level" },
- { name: "txe", desc: "TX SRAM FIFO is empty" },
- { name: "txf", desc: "TX SRAM FIFO is full" },
{ name: "txlvl", desc: "TX SRAM FIFO is under the level" },
{ name: "rxerr", desc: "MOSI in FwMode has error" },
],
+ scan: "true", // Enable `scanmode_i` port
regwidth: "32",
registers: [
{ name: "CONTROL",
diff --git a/hw/ip/spi_device/dv/env/spi_device_env_pkg.sv b/hw/ip/spi_device/dv/env/spi_device_env_pkg.sv
index 0af1175..5e79386 100644
--- a/hw/ip/spi_device/dv/env/spi_device_env_pkg.sv
+++ b/hw/ip/spi_device/dv/env/spi_device_env_pkg.sv
@@ -20,10 +20,8 @@
// local parameters and types
typedef enum {
- RxFifoNotEmpty,
+ RxFifoFull,
RxFifoGtLevel,
- TxFifoEmpty,
- TxFifoFull,
TxFifoLtLevel,
RxFwModeErr
} spi_device_intr_e;
diff --git a/hw/ip/spi_device/dv/env/spi_device_reg_block.sv b/hw/ip/spi_device/dv/env/spi_device_reg_block.sv
index 50d473b..37a3078 100644
--- a/hw/ip/spi_device/dv/env/spi_device_reg_block.sv
+++ b/hw/ip/spi_device/dv/env/spi_device_reg_block.sv
@@ -25,10 +25,8 @@
// Class: spi_device_reg_intr_state
class spi_device_reg_intr_state extends dv_base_reg;
// fields
- rand dv_base_reg_field rxne;
+ rand dv_base_reg_field rxf;
rand dv_base_reg_field rxlvl;
- rand dv_base_reg_field txe;
- rand dv_base_reg_field txf;
rand dv_base_reg_field txlvl;
rand dv_base_reg_field rxerr;
@@ -42,8 +40,8 @@
virtual function void build();
// create fields
- rxne = dv_base_reg_field::type_id::create("rxne");
- rxne.configure(
+ rxf = dv_base_reg_field::type_id::create("rxf");
+ rxf.configure(
.parent(this),
.size(1),
.lsb_pos(0),
@@ -64,33 +62,11 @@
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
- txe = dv_base_reg_field::type_id::create("txe");
- txe.configure(
- .parent(this),
- .size(1),
- .lsb_pos(2),
- .access("W1C"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- txf = dv_base_reg_field::type_id::create("txf");
- txf.configure(
- .parent(this),
- .size(1),
- .lsb_pos(3),
- .access("W1C"),
- .volatile(1),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
txlvl = dv_base_reg_field::type_id::create("txlvl");
txlvl.configure(
.parent(this),
.size(1),
- .lsb_pos(4),
+ .lsb_pos(2),
.access("W1C"),
.volatile(1),
.reset(0),
@@ -101,7 +77,7 @@
rxerr.configure(
.parent(this),
.size(1),
- .lsb_pos(5),
+ .lsb_pos(3),
.access("W1C"),
.volatile(1),
.reset(0),
@@ -115,10 +91,8 @@
// Class: spi_device_reg_intr_enable
class spi_device_reg_intr_enable extends dv_base_reg;
// fields
- rand dv_base_reg_field rxne;
+ rand dv_base_reg_field rxf;
rand dv_base_reg_field rxlvl;
- rand dv_base_reg_field txe;
- rand dv_base_reg_field txf;
rand dv_base_reg_field txlvl;
rand dv_base_reg_field rxerr;
@@ -132,8 +106,8 @@
virtual function void build();
// create fields
- rxne = dv_base_reg_field::type_id::create("rxne");
- rxne.configure(
+ rxf = dv_base_reg_field::type_id::create("rxf");
+ rxf.configure(
.parent(this),
.size(1),
.lsb_pos(0),
@@ -154,33 +128,11 @@
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
- txe = dv_base_reg_field::type_id::create("txe");
- txe.configure(
- .parent(this),
- .size(1),
- .lsb_pos(2),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- txf = dv_base_reg_field::type_id::create("txf");
- txf.configure(
- .parent(this),
- .size(1),
- .lsb_pos(3),
- .access("RW"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
txlvl = dv_base_reg_field::type_id::create("txlvl");
txlvl.configure(
.parent(this),
.size(1),
- .lsb_pos(4),
+ .lsb_pos(2),
.access("RW"),
.volatile(0),
.reset(0),
@@ -191,7 +143,7 @@
rxerr.configure(
.parent(this),
.size(1),
- .lsb_pos(5),
+ .lsb_pos(3),
.access("RW"),
.volatile(0),
.reset(0),
@@ -205,10 +157,8 @@
// Class: spi_device_reg_intr_test
class spi_device_reg_intr_test extends dv_base_reg;
// fields
- rand dv_base_reg_field rxne;
+ rand dv_base_reg_field rxf;
rand dv_base_reg_field rxlvl;
- rand dv_base_reg_field txe;
- rand dv_base_reg_field txf;
rand dv_base_reg_field txlvl;
rand dv_base_reg_field rxerr;
@@ -222,8 +172,8 @@
virtual function void build();
// create fields
- rxne = dv_base_reg_field::type_id::create("rxne");
- rxne.configure(
+ rxf = dv_base_reg_field::type_id::create("rxf");
+ rxf.configure(
.parent(this),
.size(1),
.lsb_pos(0),
@@ -244,33 +194,11 @@
.has_reset(1),
.is_rand(1),
.individually_accessible(1));
- txe = dv_base_reg_field::type_id::create("txe");
- txe.configure(
- .parent(this),
- .size(1),
- .lsb_pos(2),
- .access("WO"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
- txf = dv_base_reg_field::type_id::create("txf");
- txf.configure(
- .parent(this),
- .size(1),
- .lsb_pos(3),
- .access("WO"),
- .volatile(0),
- .reset(0),
- .has_reset(1),
- .is_rand(1),
- .individually_accessible(1));
txlvl = dv_base_reg_field::type_id::create("txlvl");
txlvl.configure(
.parent(this),
.size(1),
- .lsb_pos(4),
+ .lsb_pos(2),
.access("WO"),
.volatile(0),
.reset(0),
@@ -281,7 +209,7 @@
rxerr.configure(
.parent(this),
.size(1),
- .lsb_pos(5),
+ .lsb_pos(3),
.access("WO"),
.volatile(0),
.reset(0),
diff --git a/hw/ip/spi_device/dv/tb/tb.sv b/hw/ip/spi_device/dv/tb/tb.sv
index 399e53b..728b527 100644
--- a/hw/ip/spi_device/dv/tb/tb.sv
+++ b/hw/ip/spi_device/dv/tb/tb.sv
@@ -23,10 +23,8 @@
wire miso_en;
wire mosi_i;
- wire intr_rxne;
+ wire intr_rxf;
wire intr_rxlvl;
- wire intr_txe;
- wire intr_txf;
wire intr_txlvl;
wire intr_rxerr;
@@ -51,10 +49,8 @@
.cio_miso_en_o (miso_en ),
.cio_mosi_i (mosi_i ),
- .intr_rxne_o (intr_rxne ),
+ .intr_rxf_o (intr_rxf ),
.intr_rxlvl_o (intr_rxlvl),
- .intr_txe_o (intr_txe ),
- .intr_txf_o (intr_txf ),
.intr_txlvl_o (intr_txlvl),
.intr_rxerr_o (intr_rxerr)
);
@@ -64,10 +60,8 @@
assign mosi_i = spi_if.mosi;
assign spi_if.miso = miso_en ? miso_o : 1'bz;
- assign interrupts[RxFifoNotEmpty] = intr_rxne ;
+ assign interrupts[RxFifoFull] = intr_rxf ;
assign interrupts[RxFifoGtLevel] = intr_rxlvl;
- assign interrupts[TxFifoEmpty] = intr_txe ;
- assign interrupts[TxFifoFull] = intr_txf ;
assign interrupts[TxFifoLtLevel] = intr_txlvl;
assign interrupts[RxFwModeErr] = intr_rxerr;
diff --git a/hw/ip/spi_device/rtl/spi_device.sv b/hw/ip/spi_device/rtl/spi_device.sv
index 335f019..732afb8 100644
--- a/hw/ip/spi_device/rtl/spi_device.sv
+++ b/hw/ip/spi_device/rtl/spi_device.sv
@@ -25,10 +25,8 @@
input cio_mosi_i,
// Interrupts
- output logic intr_rxne_o, // RX FIFO Not Empty
+ output logic intr_rxf_o, // RX FIFO Full
output logic intr_rxlvl_o, // RX FIFO above level
- output logic intr_txe_o, // TX FIFO Empty
- output logic intr_txf_o, // TX FIFO Full
output logic intr_txlvl_o, // TX FIFO below level
output logic intr_rxerr_o // RX Frame error
);
@@ -91,7 +89,7 @@
spi_mode_e spi_mode;
//spi_byte_t fw_dummy_byte;
- logic intr_fwm_rxne, intr_fwm_txe, intr_fwm_txf, intr_fwm_rxerr;
+ logic intr_sram_rxf_full, intr_fwm_rxerr;
logic intr_fwm_rxlvl, rxlvl, rxlvl_d, intr_fwm_txlvl, txlvl, txlvl_d;
// RX FIFO Signals
@@ -198,33 +196,25 @@
// Interrupt
// Edge
- logic fwm_txf_q, fwm_txe_q, fwm_rxne_q, fwm_rxerr_q;
- logic fwm_txf , fwm_txe , fwm_rxne , fwm_rxerr ;
+ logic sram_rxf_full_q, fwm_rxerr_q;
+ logic sram_rxf_full , fwm_rxerr ;
- assign fwm_txf = ~txf_wready;
- assign fwm_txe = txf_empty_syncd;
- assign fwm_rxne = rxf_rvalid;
- assign fwm_rxerr = 1'b0; // TODO: Check if CE# deasserted in the middle of bit transfer
+ // TODO: Check if CE# deasserted in the middle of bit transfer
+ assign fwm_rxerr = 1'b0;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
- fwm_txf_q <= 1'b0;
- fwm_txe_q <= 1'b1;
- fwm_rxne_q <= 1'b0;
- fwm_rxerr_q <= 1'b0;
+ sram_rxf_full_q <= 1'b0;
+ fwm_rxerr_q <= 1'b0;
end else begin
- fwm_txf_q <= fwm_txf;
- fwm_txe_q <= fwm_txe;
- fwm_rxne_q <= fwm_rxne;
- fwm_rxerr_q <= fwm_rxerr;
+ sram_rxf_full_q <= sram_rxf_full;
+ fwm_rxerr_q <= fwm_rxerr;
end
end
// Interrupt
- assign intr_fwm_txf = ~fwm_txf_q & fwm_txf;
- assign intr_fwm_txe = ~fwm_txe_q & fwm_txe;
- assign intr_fwm_rxne = ~fwm_rxne_q & fwm_rxne;
- assign intr_fwm_rxerr = ~fwm_rxerr_q & fwm_rxerr;
+ assign intr_sram_rxf_full = ~sram_rxf_full_q & sram_rxf_full;
+ assign intr_fwm_rxerr = ~fwm_rxerr_q & fwm_rxerr;
assign rxlvl_d = (sram_rxf_depth >= reg2hw.fifo_level.rxlvl.q[PtrW-1:0]) ;
assign txlvl_d = (sram_txf_depth < reg2hw.fifo_level.txlvl.q[PtrW-1:0]) ;
@@ -243,20 +233,12 @@
assign intr_rxlvl_o = reg2hw.intr_enable.rxlvl.q & reg2hw.intr_state.rxlvl.q;
assign intr_txlvl_o = reg2hw.intr_enable.txlvl.q & reg2hw.intr_state.txlvl.q;
- assign intr_rxne_o = reg2hw.intr_enable.rxne.q & reg2hw.intr_state.rxne.q;
- assign intr_txe_o = reg2hw.intr_enable.txe.q & reg2hw.intr_state.txe.q;
- assign intr_txf_o = reg2hw.intr_enable.txf.q & reg2hw.intr_state.txf.q;
+ assign intr_rxf_o = reg2hw.intr_enable.rxf.q & reg2hw.intr_state.rxf.q;
assign intr_rxerr_o = reg2hw.intr_enable.rxerr.q & reg2hw.intr_state.rxerr.q;
- assign hw2reg.intr_state.rxne.d = 1'b1;
- assign hw2reg.intr_state.rxne.de = intr_fwm_rxne |
- (reg2hw.intr_test.rxne.qe & reg2hw.intr_test.rxne.q);
- assign hw2reg.intr_state.txe.d = 1'b1;
- assign hw2reg.intr_state.txe.de = intr_fwm_txe |
- (reg2hw.intr_test.txe.qe & reg2hw.intr_test.txe.q);
- assign hw2reg.intr_state.txf.d = 1'b1;
- assign hw2reg.intr_state.txf.de = intr_fwm_txf |
- (reg2hw.intr_test.txf.qe & reg2hw.intr_test.txf.q);
+ assign hw2reg.intr_state.rxf.d = 1'b1;
+ assign hw2reg.intr_state.rxf.de = intr_sram_rxf_full |
+ (reg2hw.intr_test.rxf.qe & reg2hw.intr_test.rxf.q);
assign hw2reg.intr_state.rxerr.d = 1'b1;
assign hw2reg.intr_state.rxerr.de = intr_fwm_rxerr |
(reg2hw.intr_test.rxerr.qe & reg2hw.intr_test.rxerr.q);
@@ -372,6 +354,7 @@
.rptr (sram_rxf_rptr), // Given by FW
.wptr (sram_rxf_wptr), // to Register interface
.depth (sram_rxf_depth),
+ .full (sram_rxf_full),
.fifo_valid (rxf_rvalid),
.fifo_ready (rxf_rready),
diff --git a/hw/ip/spi_device/rtl/spi_device_reg_pkg.sv b/hw/ip/spi_device/rtl/spi_device_reg_pkg.sv
index bd95db4..727ef6b 100644
--- a/hw/ip/spi_device/rtl/spi_device_reg_pkg.sv
+++ b/hw/ip/spi_device/rtl/spi_device_reg_pkg.sv
@@ -11,61 +11,41 @@
struct packed {
struct packed {
- logic q; // [168]
- } rxne;
- struct packed {
- logic q; // [167]
- } rxlvl;
- struct packed {
- logic q; // [166]
- } txe;
- struct packed {
- logic q; // [165]
- } txf;
- struct packed {
- logic q; // [164]
- } txlvl;
- struct packed {
- logic q; // [163]
- } rxerr;
- } intr_state;
- struct packed {
- struct packed {
- logic q; // [162]
- } rxne;
- struct packed {
- logic q; // [161]
- } rxlvl;
- struct packed {
logic q; // [160]
- } txe;
+ } rxf;
struct packed {
logic q; // [159]
- } txf;
+ } rxlvl;
struct packed {
logic q; // [158]
} txlvl;
struct packed {
logic q; // [157]
} rxerr;
- } intr_enable;
+ } intr_state;
struct packed {
struct packed {
logic q; // [156]
- logic qe; // [155]
- } rxne;
+ } rxf;
+ struct packed {
+ logic q; // [155]
+ } rxlvl;
struct packed {
logic q; // [154]
- logic qe; // [153]
- } rxlvl;
+ } txlvl;
+ struct packed {
+ logic q; // [153]
+ } rxerr;
+ } intr_enable;
+ struct packed {
struct packed {
logic q; // [152]
logic qe; // [151]
- } txe;
+ } rxf;
struct packed {
logic q; // [150]
logic qe; // [149]
- } txf;
+ } rxlvl;
struct packed {
logic q; // [148]
logic qe; // [147]
@@ -147,21 +127,13 @@
struct packed {
struct packed {
- logic d; // [66]
- logic de; // [65]
- } rxne;
- struct packed {
- logic d; // [64]
- logic de; // [63]
- } rxlvl;
- struct packed {
logic d; // [62]
logic de; // [61]
- } txe;
+ } rxf;
struct packed {
logic d; // [60]
logic de; // [59]
- } txf;
+ } rxlvl;
struct packed {
logic d; // [58]
logic de; // [57]
diff --git a/hw/ip/spi_device/rtl/spi_device_reg_top.sv b/hw/ip/spi_device/rtl/spi_device_reg_top.sv
index 18a2b07..c53da41 100644
--- a/hw/ip/spi_device/rtl/spi_device_reg_top.sv
+++ b/hw/ip/spi_device/rtl/spi_device_reg_top.sv
@@ -174,50 +174,34 @@
// Define SW related signals
// Format: <reg>_<field>_{wd|we|qs}
// or <reg>_{wd|we|qs} if field == 1 or 0
- logic intr_state_rxne_qs;
- logic intr_state_rxne_wd;
- logic intr_state_rxne_we;
+ logic intr_state_rxf_qs;
+ logic intr_state_rxf_wd;
+ logic intr_state_rxf_we;
logic intr_state_rxlvl_qs;
logic intr_state_rxlvl_wd;
logic intr_state_rxlvl_we;
- logic intr_state_txe_qs;
- logic intr_state_txe_wd;
- logic intr_state_txe_we;
- logic intr_state_txf_qs;
- logic intr_state_txf_wd;
- logic intr_state_txf_we;
logic intr_state_txlvl_qs;
logic intr_state_txlvl_wd;
logic intr_state_txlvl_we;
logic intr_state_rxerr_qs;
logic intr_state_rxerr_wd;
logic intr_state_rxerr_we;
- logic intr_enable_rxne_qs;
- logic intr_enable_rxne_wd;
- logic intr_enable_rxne_we;
+ logic intr_enable_rxf_qs;
+ logic intr_enable_rxf_wd;
+ logic intr_enable_rxf_we;
logic intr_enable_rxlvl_qs;
logic intr_enable_rxlvl_wd;
logic intr_enable_rxlvl_we;
- logic intr_enable_txe_qs;
- logic intr_enable_txe_wd;
- logic intr_enable_txe_we;
- logic intr_enable_txf_qs;
- logic intr_enable_txf_wd;
- logic intr_enable_txf_we;
logic intr_enable_txlvl_qs;
logic intr_enable_txlvl_wd;
logic intr_enable_txlvl_we;
logic intr_enable_rxerr_qs;
logic intr_enable_rxerr_wd;
logic intr_enable_rxerr_we;
- logic intr_test_rxne_wd;
- logic intr_test_rxne_we;
+ logic intr_test_rxf_wd;
+ logic intr_test_rxf_we;
logic intr_test_rxlvl_wd;
logic intr_test_rxlvl_we;
- logic intr_test_txe_wd;
- logic intr_test_txe_we;
- logic intr_test_txf_wd;
- logic intr_test_txf_we;
logic intr_test_txlvl_wd;
logic intr_test_txlvl_we;
logic intr_test_rxerr_wd;
@@ -293,29 +277,29 @@
// Register instances
// R[intr_state]: V(False)
- // F[rxne]: 0:0
+ // F[rxf]: 0:0
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
.RESVAL (1'h0)
- ) u_intr_state_rxne (
+ ) u_intr_state_rxf (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
- .we (intr_state_rxne_we),
- .wd (intr_state_rxne_wd),
+ .we (intr_state_rxf_we),
+ .wd (intr_state_rxf_wd),
// from internal hardware
- .de (hw2reg.intr_state.rxne.de),
- .d (hw2reg.intr_state.rxne.d ),
+ .de (hw2reg.intr_state.rxf.de),
+ .d (hw2reg.intr_state.rxf.d ),
// to internal hardware
.qe (),
- .q (reg2hw.intr_state.rxne.q ),
+ .q (reg2hw.intr_state.rxf.q ),
// to register interface (read)
- .qs (intr_state_rxne_qs)
+ .qs (intr_state_rxf_qs)
);
@@ -345,59 +329,7 @@
);
- // F[txe]: 2:2
- prim_subreg #(
- .DW (1),
- .SWACCESS("W1C"),
- .RESVAL (1'h0)
- ) u_intr_state_txe (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
-
- // from register interface
- .we (intr_state_txe_we),
- .wd (intr_state_txe_wd),
-
- // from internal hardware
- .de (hw2reg.intr_state.txe.de),
- .d (hw2reg.intr_state.txe.d ),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.intr_state.txe.q ),
-
- // to register interface (read)
- .qs (intr_state_txe_qs)
- );
-
-
- // F[txf]: 3:3
- prim_subreg #(
- .DW (1),
- .SWACCESS("W1C"),
- .RESVAL (1'h0)
- ) u_intr_state_txf (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
-
- // from register interface
- .we (intr_state_txf_we),
- .wd (intr_state_txf_wd),
-
- // from internal hardware
- .de (hw2reg.intr_state.txf.de),
- .d (hw2reg.intr_state.txf.d ),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.intr_state.txf.q ),
-
- // to register interface (read)
- .qs (intr_state_txf_qs)
- );
-
-
- // F[txlvl]: 4:4
+ // F[txlvl]: 2:2
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
@@ -423,7 +355,7 @@
);
- // F[rxerr]: 5:5
+ // F[rxerr]: 3:3
prim_subreg #(
.DW (1),
.SWACCESS("W1C"),
@@ -451,18 +383,18 @@
// R[intr_enable]: V(False)
- // F[rxne]: 0:0
+ // F[rxf]: 0:0
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
- ) u_intr_enable_rxne (
+ ) u_intr_enable_rxf (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
- .we (intr_enable_rxne_we),
- .wd (intr_enable_rxne_wd),
+ .we (intr_enable_rxf_we),
+ .wd (intr_enable_rxf_wd),
// from internal hardware
.de (1'b0),
@@ -470,10 +402,10 @@
// to internal hardware
.qe (),
- .q (reg2hw.intr_enable.rxne.q ),
+ .q (reg2hw.intr_enable.rxf.q ),
// to register interface (read)
- .qs (intr_enable_rxne_qs)
+ .qs (intr_enable_rxf_qs)
);
@@ -503,59 +435,7 @@
);
- // F[txe]: 2:2
- prim_subreg #(
- .DW (1),
- .SWACCESS("RW"),
- .RESVAL (1'h0)
- ) u_intr_enable_txe (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
-
- // from register interface
- .we (intr_enable_txe_we),
- .wd (intr_enable_txe_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0 ),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.intr_enable.txe.q ),
-
- // to register interface (read)
- .qs (intr_enable_txe_qs)
- );
-
-
- // F[txf]: 3:3
- prim_subreg #(
- .DW (1),
- .SWACCESS("RW"),
- .RESVAL (1'h0)
- ) u_intr_enable_txf (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
-
- // from register interface
- .we (intr_enable_txf_we),
- .wd (intr_enable_txf_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0 ),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.intr_enable.txf.q ),
-
- // to register interface (read)
- .qs (intr_enable_txf_qs)
- );
-
-
- // F[txlvl]: 4:4
+ // F[txlvl]: 2:2
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
@@ -581,7 +461,7 @@
);
- // F[rxerr]: 5:5
+ // F[rxerr]: 3:3
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
@@ -609,17 +489,17 @@
// R[intr_test]: V(True)
- // F[rxne]: 0:0
+ // F[rxf]: 0:0
prim_subreg_ext #(
.DW (1)
- ) u_intr_test_rxne (
+ ) u_intr_test_rxf (
.re (1'b0),
- .we (intr_test_rxne_we),
- .wd (intr_test_rxne_wd),
+ .we (intr_test_rxf_we),
+ .wd (intr_test_rxf_wd),
.d ('0),
.qre (),
- .qe (reg2hw.intr_test.rxne.qe),
- .q (reg2hw.intr_test.rxne.q ),
+ .qe (reg2hw.intr_test.rxf.qe),
+ .q (reg2hw.intr_test.rxf.q ),
.qs ()
);
@@ -639,37 +519,7 @@
);
- // F[txe]: 2:2
- prim_subreg_ext #(
- .DW (1)
- ) u_intr_test_txe (
- .re (1'b0),
- .we (intr_test_txe_we),
- .wd (intr_test_txe_wd),
- .d ('0),
- .qre (),
- .qe (reg2hw.intr_test.txe.qe),
- .q (reg2hw.intr_test.txe.q ),
- .qs ()
- );
-
-
- // F[txf]: 3:3
- prim_subreg_ext #(
- .DW (1)
- ) u_intr_test_txf (
- .re (1'b0),
- .we (intr_test_txf_we),
- .wd (intr_test_txf_wd),
- .d ('0),
- .qre (),
- .qe (reg2hw.intr_test.txf.qe),
- .q (reg2hw.intr_test.txf.q ),
- .qs ()
- );
-
-
- // F[txlvl]: 4:4
+ // F[txlvl]: 2:2
prim_subreg_ext #(
.DW (1)
) u_intr_test_txlvl (
@@ -684,7 +534,7 @@
);
- // F[rxerr]: 5:5
+ // F[rxerr]: 3:3
prim_subreg_ext #(
.DW (1)
) u_intr_test_rxerr (
@@ -1342,59 +1192,41 @@
// Write Enable signal
- assign intr_state_rxne_we = addr_hit[0] && reg_we;
- assign intr_state_rxne_wd = reg_wdata[0];
+ assign intr_state_rxf_we = addr_hit[0] && reg_we;
+ assign intr_state_rxf_wd = reg_wdata[0];
assign intr_state_rxlvl_we = addr_hit[0] && reg_we;
assign intr_state_rxlvl_wd = reg_wdata[1];
- assign intr_state_txe_we = addr_hit[0] && reg_we;
- assign intr_state_txe_wd = reg_wdata[2];
-
- assign intr_state_txf_we = addr_hit[0] && reg_we;
- assign intr_state_txf_wd = reg_wdata[3];
-
assign intr_state_txlvl_we = addr_hit[0] && reg_we;
- assign intr_state_txlvl_wd = reg_wdata[4];
+ assign intr_state_txlvl_wd = reg_wdata[2];
assign intr_state_rxerr_we = addr_hit[0] && reg_we;
- assign intr_state_rxerr_wd = reg_wdata[5];
+ assign intr_state_rxerr_wd = reg_wdata[3];
- assign intr_enable_rxne_we = addr_hit[1] && reg_we;
- assign intr_enable_rxne_wd = reg_wdata[0];
+ assign intr_enable_rxf_we = addr_hit[1] && reg_we;
+ assign intr_enable_rxf_wd = reg_wdata[0];
assign intr_enable_rxlvl_we = addr_hit[1] && reg_we;
assign intr_enable_rxlvl_wd = reg_wdata[1];
- assign intr_enable_txe_we = addr_hit[1] && reg_we;
- assign intr_enable_txe_wd = reg_wdata[2];
-
- assign intr_enable_txf_we = addr_hit[1] && reg_we;
- assign intr_enable_txf_wd = reg_wdata[3];
-
assign intr_enable_txlvl_we = addr_hit[1] && reg_we;
- assign intr_enable_txlvl_wd = reg_wdata[4];
+ assign intr_enable_txlvl_wd = reg_wdata[2];
assign intr_enable_rxerr_we = addr_hit[1] && reg_we;
- assign intr_enable_rxerr_wd = reg_wdata[5];
+ assign intr_enable_rxerr_wd = reg_wdata[3];
- assign intr_test_rxne_we = addr_hit[2] && reg_we;
- assign intr_test_rxne_wd = reg_wdata[0];
+ assign intr_test_rxf_we = addr_hit[2] && reg_we;
+ assign intr_test_rxf_wd = reg_wdata[0];
assign intr_test_rxlvl_we = addr_hit[2] && reg_we;
assign intr_test_rxlvl_wd = reg_wdata[1];
- assign intr_test_txe_we = addr_hit[2] && reg_we;
- assign intr_test_txe_wd = reg_wdata[2];
-
- assign intr_test_txf_we = addr_hit[2] && reg_we;
- assign intr_test_txf_wd = reg_wdata[3];
-
assign intr_test_txlvl_we = addr_hit[2] && reg_we;
- assign intr_test_txlvl_wd = reg_wdata[4];
+ assign intr_test_txlvl_wd = reg_wdata[2];
assign intr_test_rxerr_we = addr_hit[2] && reg_we;
- assign intr_test_rxerr_wd = reg_wdata[5];
+ assign intr_test_rxerr_wd = reg_wdata[3];
assign control_abort_we = addr_hit[3] && reg_we;
assign control_abort_wd = reg_wdata[0];
@@ -1469,21 +1301,17 @@
reg_rdata_next = '0;
unique case (1'b1)
addr_hit[0]: begin
- reg_rdata_next[0] = intr_state_rxne_qs;
+ reg_rdata_next[0] = intr_state_rxf_qs;
reg_rdata_next[1] = intr_state_rxlvl_qs;
- reg_rdata_next[2] = intr_state_txe_qs;
- reg_rdata_next[3] = intr_state_txf_qs;
- reg_rdata_next[4] = intr_state_txlvl_qs;
- reg_rdata_next[5] = intr_state_rxerr_qs;
+ reg_rdata_next[2] = intr_state_txlvl_qs;
+ reg_rdata_next[3] = intr_state_rxerr_qs;
end
addr_hit[1]: begin
- reg_rdata_next[0] = intr_enable_rxne_qs;
+ reg_rdata_next[0] = intr_enable_rxf_qs;
reg_rdata_next[1] = intr_enable_rxlvl_qs;
- reg_rdata_next[2] = intr_enable_txe_qs;
- reg_rdata_next[3] = intr_enable_txf_qs;
- reg_rdata_next[4] = intr_enable_txlvl_qs;
- reg_rdata_next[5] = intr_enable_rxerr_qs;
+ reg_rdata_next[2] = intr_enable_txlvl_qs;
+ reg_rdata_next[3] = intr_enable_rxerr_qs;
end
addr_hit[2]: begin
@@ -1491,8 +1319,6 @@
reg_rdata_next[1] = '0;
reg_rdata_next[2] = '0;
reg_rdata_next[3] = '0;
- reg_rdata_next[4] = '0;
- reg_rdata_next[5] = '0;
end
addr_hit[3]: begin
diff --git a/hw/ip/spi_device/rtl/spi_fwm_rxf_ctrl.sv b/hw/ip/spi_device/rtl/spi_fwm_rxf_ctrl.sv
index 2947400..bab909d 100644
--- a/hw/ip/spi_device/rtl/spi_fwm_rxf_ctrl.sv
+++ b/hw/ip/spi_device/rtl/spi_fwm_rxf_ctrl.sv
@@ -26,6 +26,8 @@
output logic [PtrW-1:0] wptr,
output logic [PtrW-1:0] depth,
+ output logic full,
+
input fifo_valid,
output logic fifo_ready,
input [FifoDw-1:0] fifo_rdata,
@@ -86,6 +88,7 @@
assign ptr_cmp = rptr ^ wptr;
// TODO: Check partial SRAM width read condition
assign sramf_full = (ptr_cmp[PtrW-1] == 1'b1) && (ptr_cmp[PtrW-2:SDW] == '0);
+ assign full = sramf_full;
assign sramf_limit = limit_index_i - base_index_i;
diff --git a/hw/ip/spi_device/rtl/spi_fwmode.sv b/hw/ip/spi_device/rtl/spi_fwmode.sv
index 4c0df32..1241284 100644
--- a/hw/ip/spi_device/rtl/spi_fwmode.sv
+++ b/hw/ip/spi_device/rtl/spi_fwmode.sv
@@ -41,7 +41,8 @@
localparam int unsigned BITWIDTH = $clog2(BITS);
logic [BITWIDTH-1:0] rx_bitcount;
- typedef enum {
+
+ typedef enum logic {
TxIdle,
TxActive
} tx_state_e;
@@ -91,11 +92,10 @@
assign first_bit = (tx_bitcount == BITWIDTH'(BITS-1)) ? 1'b1 : 1'b0;
assign last_bit = (tx_bitcount == '0) ? 1'b1 : 1'b0;
// Pop the entry from the FIFO at bit 1.
- // This let the module pop the entry correctly when CPHA == 1
- // If CPHA is set, there is no clock posedge after bitcnt is 0.
- // So TX Async FIFO pop signal cannot be latched inside FIFO.
- // It is safe to pop between bitcnt 6 to 1. If pop signal is asserted
- // when bitcnt 7 it can pop twice if CPHA is 1.
+ // This let the module pop the entry correctly when CPHA == 1 If CPHA is set, there is no clock
+ // posedge after bitcnt is 0 right before CSb is de-asserted. So TX Async FIFO pop signal
+ // cannot be latched inside FIFO. It is safe to pop between bitcnt 6 to 1. If pop signal is
+ // asserted when bitcnt 7 it can pop twice if CPHA is 1.
assign tx_rready_o = (tx_bitcount == BITWIDTH'(1)); // Pop at second bit transfer
always_ff @(posedge clk_out_i or negedge rst_out_ni) begin
if (!rst_out_ni) begin
diff --git a/hw/ip/spi_device/sw/spi_device_regs.h b/hw/ip/spi_device/sw/spi_device_regs.h
index 8f109ae..6b340d4 100644
--- a/hw/ip/spi_device/sw/spi_device_regs.h
+++ b/hw/ip/spi_device/sw/spi_device_regs.h
@@ -12,30 +12,24 @@
// Interrupt State Register
#define SPI_DEVICE_INTR_STATE(id) (SPI_DEVICE##id##_BASE_ADDR + 0x0)
-#define SPI_DEVICE_INTR_STATE_RXNE 0
+#define SPI_DEVICE_INTR_STATE_RXF 0
#define SPI_DEVICE_INTR_STATE_RXLVL 1
-#define SPI_DEVICE_INTR_STATE_TXE 2
-#define SPI_DEVICE_INTR_STATE_TXF 3
-#define SPI_DEVICE_INTR_STATE_TXLVL 4
-#define SPI_DEVICE_INTR_STATE_RXERR 5
+#define SPI_DEVICE_INTR_STATE_TXLVL 2
+#define SPI_DEVICE_INTR_STATE_RXERR 3
// Interrupt Enable Register
#define SPI_DEVICE_INTR_ENABLE(id) (SPI_DEVICE##id##_BASE_ADDR + 0x4)
-#define SPI_DEVICE_INTR_ENABLE_RXNE 0
+#define SPI_DEVICE_INTR_ENABLE_RXF 0
#define SPI_DEVICE_INTR_ENABLE_RXLVL 1
-#define SPI_DEVICE_INTR_ENABLE_TXE 2
-#define SPI_DEVICE_INTR_ENABLE_TXF 3
-#define SPI_DEVICE_INTR_ENABLE_TXLVL 4
-#define SPI_DEVICE_INTR_ENABLE_RXERR 5
+#define SPI_DEVICE_INTR_ENABLE_TXLVL 2
+#define SPI_DEVICE_INTR_ENABLE_RXERR 3
// Interrupt Test Register
#define SPI_DEVICE_INTR_TEST(id) (SPI_DEVICE##id##_BASE_ADDR + 0x8)
-#define SPI_DEVICE_INTR_TEST_RXNE 0
+#define SPI_DEVICE_INTR_TEST_RXF 0
#define SPI_DEVICE_INTR_TEST_RXLVL 1
-#define SPI_DEVICE_INTR_TEST_TXE 2
-#define SPI_DEVICE_INTR_TEST_TXF 3
-#define SPI_DEVICE_INTR_TEST_TXLVL 4
-#define SPI_DEVICE_INTR_TEST_RXERR 5
+#define SPI_DEVICE_INTR_TEST_TXLVL 2
+#define SPI_DEVICE_INTR_TEST_RXERR 3
// Control register
#define SPI_DEVICE_CONTROL(id) (SPI_DEVICE##id##_BASE_ADDR + 0xc)
diff --git a/hw/top_earlgrey/doc/rv_plic.hjson b/hw/top_earlgrey/doc/rv_plic.hjson
index ed0e47d..4fea638 100644
--- a/hw/top_earlgrey/doc/rv_plic.hjson
+++ b/hw/top_earlgrey/doc/rv_plic.hjson
@@ -6,6 +6,10 @@
// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
// util/topgen.py -t hw/top_earlgrey/doc/top_earlgrey.hjson --plic-only -o hw/top_earlgrey/
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
# RV_PLIC register template
#
# Parameter (given by python tool)
@@ -22,7 +26,7 @@
{ multireg: {
name: "IP",
desc: "Interrupt Pending",
- count: 54,
+ count: 52,
cname: "RV_PLIC",
swaccess: "ro",
hwaccess: "hwo",
@@ -34,7 +38,7 @@
{ multireg: {
name: "LE",
desc: "Interrupt Source mode. 0: Level, 1: Edge-triggered",
- count: 54,
+ count: 52,
cname: "RV_PLIC",
swaccess: "rw",
hwaccess: "hro",
@@ -459,27 +463,11 @@
{ bits: "1:0" }
],
}
- { name: "PRIO52",
- desc: "Interrupt Source 52 Priority",
- swaccess: "rw",
- hwaccess: "hro",
- fields: [
- { bits: "1:0" }
- ],
- }
- { name: "PRIO53",
- desc: "Interrupt Source 53 Priority",
- swaccess: "rw",
- hwaccess: "hro",
- fields: [
- { bits: "1:0" }
- ],
- }
{ skipto: 256 }
{ multireg: {
name: "IE0",
desc: "Interrupt Enable for Target 0",
- count: 54,
+ count: 52,
cname: "RV_PLIC",
swaccess: "rw",
hwaccess: "hro",
diff --git a/hw/top_earlgrey/doc/top_earlgrey.gen.hjson b/hw/top_earlgrey/doc/top_earlgrey.gen.hjson
index a9dc310..3a2fb3b 100644
--- a/hw/top_earlgrey/doc/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/doc/top_earlgrey.gen.hjson
@@ -140,7 +140,7 @@
interrupt_list:
[
{
- name: rxne
+ name: rxf
width: 1
}
{
@@ -148,14 +148,6 @@
width: 1
}
{
- name: txe
- width: 1
- }
- {
- name: txf
- width: 1
- }
- {
name: txlvl
width: 1
}
@@ -493,7 +485,7 @@
width: 1
}
{
- name: spi_device_rxne
+ name: spi_device_rxf
width: 1
}
{
@@ -501,14 +493,6 @@
width: 1
}
{
- name: spi_device_txe
- width: 1
- }
- {
- name: spi_device_txf
- width: 1
- }
- {
name: spi_device_txlvl
width: 1
}
diff --git a/hw/top_earlgrey/rtl/rv_plic.sv b/hw/top_earlgrey/rtl/rv_plic.sv
index df10f6d..a2c9227 100644
--- a/hw/top_earlgrey/rtl/rv_plic.sv
+++ b/hw/top_earlgrey/rtl/rv_plic.sv
@@ -25,7 +25,7 @@
// MAX_PRIO: Maximum value of interrupt priority
module rv_plic #(
- parameter int N_SOURCE = 54,
+ parameter int N_SOURCE = 52,
parameter int N_TARGET = 1,
parameter FIND_MAX = "SEQUENTIAL", // SEQUENTIAL | MATRIX
@@ -152,8 +152,6 @@
assign prio[49] = reg2hw.prio49.q;
assign prio[50] = reg2hw.prio50.q;
assign prio[51] = reg2hw.prio51.q;
- assign prio[52] = reg2hw.prio52.q;
- assign prio[53] = reg2hw.prio53.q;
//----------------------------------------------------------------------------
//////////////////////////////////////////////////////////////////////////////
@@ -210,8 +208,6 @@
assign ie[0][49] = reg2hw.ie01.e49.q;
assign ie[0][50] = reg2hw.ie01.e50.q;
assign ie[0][51] = reg2hw.ie01.e51.q;
- assign ie[0][52] = reg2hw.ie01.e52.q;
- assign ie[0][53] = reg2hw.ie01.e53.q;
//----------------------------------------------------------------------------
//////////////////////////////////////////////////////////////////////////////
@@ -287,8 +283,6 @@
assign hw2reg.ip1.p49.de = 1'b1; // Always write
assign hw2reg.ip1.p50.de = 1'b1; // Always write
assign hw2reg.ip1.p51.de = 1'b1; // Always write
- assign hw2reg.ip1.p52.de = 1'b1; // Always write
- assign hw2reg.ip1.p53.de = 1'b1; // Always write
assign hw2reg.ip0.p0.d = ip[0];
assign hw2reg.ip0.p1.d = ip[1];
assign hw2reg.ip0.p2.d = ip[2];
@@ -341,8 +335,6 @@
assign hw2reg.ip1.p49.d = ip[49];
assign hw2reg.ip1.p50.d = ip[50];
assign hw2reg.ip1.p51.d = ip[51];
- assign hw2reg.ip1.p52.d = ip[52];
- assign hw2reg.ip1.p53.d = ip[53];
//----------------------------------------------------------------------------
//////////////////////////////////////////////////////////////////////////////
@@ -399,8 +391,6 @@
assign le[49] = reg2hw.le1.le49.q;
assign le[50] = reg2hw.le1.le50.q;
assign le[51] = reg2hw.le1.le51.q;
- assign le[52] = reg2hw.le1.le52.q;
- assign le[53] = reg2hw.le1.le53.q;
//----------------------------------------------------------------------------
// Gateways
diff --git a/hw/top_earlgrey/rtl/rv_plic_reg_pkg.sv b/hw/top_earlgrey/rtl/rv_plic_reg_pkg.sv
index f704b54..4b083da 100644
--- a/hw/top_earlgrey/rtl/rv_plic_reg_pkg.sv
+++ b/hw/top_earlgrey/rtl/rv_plic_reg_pkg.sv
@@ -11,497 +11,479 @@
struct packed {
struct packed {
- logic q; // [226]
+ logic q; // [218]
} le0;
struct packed {
- logic q; // [225]
+ logic q; // [217]
} le1;
struct packed {
- logic q; // [224]
+ logic q; // [216]
} le2;
struct packed {
- logic q; // [223]
+ logic q; // [215]
} le3;
struct packed {
- logic q; // [222]
+ logic q; // [214]
} le4;
struct packed {
- logic q; // [221]
+ logic q; // [213]
} le5;
struct packed {
- logic q; // [220]
+ logic q; // [212]
} le6;
struct packed {
- logic q; // [219]
+ logic q; // [211]
} le7;
struct packed {
- logic q; // [218]
+ logic q; // [210]
} le8;
struct packed {
- logic q; // [217]
+ logic q; // [209]
} le9;
struct packed {
- logic q; // [216]
+ logic q; // [208]
} le10;
struct packed {
- logic q; // [215]
+ logic q; // [207]
} le11;
struct packed {
- logic q; // [214]
+ logic q; // [206]
} le12;
struct packed {
- logic q; // [213]
+ logic q; // [205]
} le13;
struct packed {
- logic q; // [212]
+ logic q; // [204]
} le14;
struct packed {
- logic q; // [211]
+ logic q; // [203]
} le15;
struct packed {
- logic q; // [210]
+ logic q; // [202]
} le16;
struct packed {
- logic q; // [209]
+ logic q; // [201]
} le17;
struct packed {
- logic q; // [208]
+ logic q; // [200]
} le18;
struct packed {
- logic q; // [207]
+ logic q; // [199]
} le19;
struct packed {
- logic q; // [206]
+ logic q; // [198]
} le20;
struct packed {
- logic q; // [205]
+ logic q; // [197]
} le21;
struct packed {
- logic q; // [204]
+ logic q; // [196]
} le22;
struct packed {
- logic q; // [203]
+ logic q; // [195]
} le23;
struct packed {
- logic q; // [202]
+ logic q; // [194]
} le24;
struct packed {
- logic q; // [201]
+ logic q; // [193]
} le25;
struct packed {
- logic q; // [200]
+ logic q; // [192]
} le26;
struct packed {
- logic q; // [199]
+ logic q; // [191]
} le27;
struct packed {
- logic q; // [198]
+ logic q; // [190]
} le28;
struct packed {
- logic q; // [197]
+ logic q; // [189]
} le29;
struct packed {
- logic q; // [196]
+ logic q; // [188]
} le30;
struct packed {
- logic q; // [195]
+ logic q; // [187]
} le31;
} le0;
struct packed {
struct packed {
- logic q; // [194]
+ logic q; // [186]
} le32;
struct packed {
- logic q; // [193]
+ logic q; // [185]
} le33;
struct packed {
- logic q; // [192]
+ logic q; // [184]
} le34;
struct packed {
- logic q; // [191]
+ logic q; // [183]
} le35;
struct packed {
- logic q; // [190]
+ logic q; // [182]
} le36;
struct packed {
- logic q; // [189]
+ logic q; // [181]
} le37;
struct packed {
- logic q; // [188]
+ logic q; // [180]
} le38;
struct packed {
- logic q; // [187]
+ logic q; // [179]
} le39;
struct packed {
- logic q; // [186]
+ logic q; // [178]
} le40;
struct packed {
- logic q; // [185]
+ logic q; // [177]
} le41;
struct packed {
- logic q; // [184]
+ logic q; // [176]
} le42;
struct packed {
- logic q; // [183]
+ logic q; // [175]
} le43;
struct packed {
- logic q; // [182]
+ logic q; // [174]
} le44;
struct packed {
- logic q; // [181]
+ logic q; // [173]
} le45;
struct packed {
- logic q; // [180]
+ logic q; // [172]
} le46;
struct packed {
- logic q; // [179]
+ logic q; // [171]
} le47;
struct packed {
- logic q; // [178]
+ logic q; // [170]
} le48;
struct packed {
- logic q; // [177]
+ logic q; // [169]
} le49;
struct packed {
- logic q; // [176]
+ logic q; // [168]
} le50;
struct packed {
- logic q; // [175]
+ logic q; // [167]
} le51;
- struct packed {
- logic q; // [174]
- } le52;
- struct packed {
- logic q; // [173]
- } le53;
} le1;
struct packed {
- logic [1:0] q; // [172:171]
+ logic [1:0] q; // [166:165]
} prio0;
struct packed {
- logic [1:0] q; // [170:169]
+ logic [1:0] q; // [164:163]
} prio1;
struct packed {
- logic [1:0] q; // [168:167]
+ logic [1:0] q; // [162:161]
} prio2;
struct packed {
- logic [1:0] q; // [166:165]
+ logic [1:0] q; // [160:159]
} prio3;
struct packed {
- logic [1:0] q; // [164:163]
+ logic [1:0] q; // [158:157]
} prio4;
struct packed {
- logic [1:0] q; // [162:161]
+ logic [1:0] q; // [156:155]
} prio5;
struct packed {
- logic [1:0] q; // [160:159]
+ logic [1:0] q; // [154:153]
} prio6;
struct packed {
- logic [1:0] q; // [158:157]
+ logic [1:0] q; // [152:151]
} prio7;
struct packed {
- logic [1:0] q; // [156:155]
+ logic [1:0] q; // [150:149]
} prio8;
struct packed {
- logic [1:0] q; // [154:153]
+ logic [1:0] q; // [148:147]
} prio9;
struct packed {
- logic [1:0] q; // [152:151]
+ logic [1:0] q; // [146:145]
} prio10;
struct packed {
- logic [1:0] q; // [150:149]
+ logic [1:0] q; // [144:143]
} prio11;
struct packed {
- logic [1:0] q; // [148:147]
+ logic [1:0] q; // [142:141]
} prio12;
struct packed {
- logic [1:0] q; // [146:145]
+ logic [1:0] q; // [140:139]
} prio13;
struct packed {
- logic [1:0] q; // [144:143]
+ logic [1:0] q; // [138:137]
} prio14;
struct packed {
- logic [1:0] q; // [142:141]
+ logic [1:0] q; // [136:135]
} prio15;
struct packed {
- logic [1:0] q; // [140:139]
+ logic [1:0] q; // [134:133]
} prio16;
struct packed {
- logic [1:0] q; // [138:137]
+ logic [1:0] q; // [132:131]
} prio17;
struct packed {
- logic [1:0] q; // [136:135]
+ logic [1:0] q; // [130:129]
} prio18;
struct packed {
- logic [1:0] q; // [134:133]
+ logic [1:0] q; // [128:127]
} prio19;
struct packed {
- logic [1:0] q; // [132:131]
+ logic [1:0] q; // [126:125]
} prio20;
struct packed {
- logic [1:0] q; // [130:129]
+ logic [1:0] q; // [124:123]
} prio21;
struct packed {
- logic [1:0] q; // [128:127]
+ logic [1:0] q; // [122:121]
} prio22;
struct packed {
- logic [1:0] q; // [126:125]
+ logic [1:0] q; // [120:119]
} prio23;
struct packed {
- logic [1:0] q; // [124:123]
+ logic [1:0] q; // [118:117]
} prio24;
struct packed {
- logic [1:0] q; // [122:121]
+ logic [1:0] q; // [116:115]
} prio25;
struct packed {
- logic [1:0] q; // [120:119]
+ logic [1:0] q; // [114:113]
} prio26;
struct packed {
- logic [1:0] q; // [118:117]
+ logic [1:0] q; // [112:111]
} prio27;
struct packed {
- logic [1:0] q; // [116:115]
+ logic [1:0] q; // [110:109]
} prio28;
struct packed {
- logic [1:0] q; // [114:113]
+ logic [1:0] q; // [108:107]
} prio29;
struct packed {
- logic [1:0] q; // [112:111]
+ logic [1:0] q; // [106:105]
} prio30;
struct packed {
- logic [1:0] q; // [110:109]
+ logic [1:0] q; // [104:103]
} prio31;
struct packed {
- logic [1:0] q; // [108:107]
+ logic [1:0] q; // [102:101]
} prio32;
struct packed {
- logic [1:0] q; // [106:105]
+ logic [1:0] q; // [100:99]
} prio33;
struct packed {
- logic [1:0] q; // [104:103]
+ logic [1:0] q; // [98:97]
} prio34;
struct packed {
- logic [1:0] q; // [102:101]
+ logic [1:0] q; // [96:95]
} prio35;
struct packed {
- logic [1:0] q; // [100:99]
+ logic [1:0] q; // [94:93]
} prio36;
struct packed {
- logic [1:0] q; // [98:97]
+ logic [1:0] q; // [92:91]
} prio37;
struct packed {
- logic [1:0] q; // [96:95]
+ logic [1:0] q; // [90:89]
} prio38;
struct packed {
- logic [1:0] q; // [94:93]
+ logic [1:0] q; // [88:87]
} prio39;
struct packed {
- logic [1:0] q; // [92:91]
+ logic [1:0] q; // [86:85]
} prio40;
struct packed {
- logic [1:0] q; // [90:89]
+ logic [1:0] q; // [84:83]
} prio41;
struct packed {
- logic [1:0] q; // [88:87]
+ logic [1:0] q; // [82:81]
} prio42;
struct packed {
- logic [1:0] q; // [86:85]
+ logic [1:0] q; // [80:79]
} prio43;
struct packed {
- logic [1:0] q; // [84:83]
+ logic [1:0] q; // [78:77]
} prio44;
struct packed {
- logic [1:0] q; // [82:81]
+ logic [1:0] q; // [76:75]
} prio45;
struct packed {
- logic [1:0] q; // [80:79]
+ logic [1:0] q; // [74:73]
} prio46;
struct packed {
- logic [1:0] q; // [78:77]
+ logic [1:0] q; // [72:71]
} prio47;
struct packed {
- logic [1:0] q; // [76:75]
+ logic [1:0] q; // [70:69]
} prio48;
struct packed {
- logic [1:0] q; // [74:73]
+ logic [1:0] q; // [68:67]
} prio49;
struct packed {
- logic [1:0] q; // [72:71]
+ logic [1:0] q; // [66:65]
} prio50;
struct packed {
- logic [1:0] q; // [70:69]
+ logic [1:0] q; // [64:63]
} prio51;
struct packed {
- logic [1:0] q; // [68:67]
- } prio52;
- struct packed {
- logic [1:0] q; // [66:65]
- } prio53;
- struct packed {
- struct packed {
- logic q; // [64]
- } e0;
- struct packed {
- logic q; // [63]
- } e1;
struct packed {
logic q; // [62]
- } e2;
+ } e0;
struct packed {
logic q; // [61]
- } e3;
+ } e1;
struct packed {
logic q; // [60]
- } e4;
+ } e2;
struct packed {
logic q; // [59]
- } e5;
+ } e3;
struct packed {
logic q; // [58]
- } e6;
+ } e4;
struct packed {
logic q; // [57]
- } e7;
+ } e5;
struct packed {
logic q; // [56]
- } e8;
+ } e6;
struct packed {
logic q; // [55]
- } e9;
+ } e7;
struct packed {
logic q; // [54]
- } e10;
+ } e8;
struct packed {
logic q; // [53]
- } e11;
+ } e9;
struct packed {
logic q; // [52]
- } e12;
+ } e10;
struct packed {
logic q; // [51]
- } e13;
+ } e11;
struct packed {
logic q; // [50]
- } e14;
+ } e12;
struct packed {
logic q; // [49]
- } e15;
+ } e13;
struct packed {
logic q; // [48]
- } e16;
+ } e14;
struct packed {
logic q; // [47]
- } e17;
+ } e15;
struct packed {
logic q; // [46]
- } e18;
+ } e16;
struct packed {
logic q; // [45]
- } e19;
+ } e17;
struct packed {
logic q; // [44]
- } e20;
+ } e18;
struct packed {
logic q; // [43]
- } e21;
+ } e19;
struct packed {
logic q; // [42]
- } e22;
+ } e20;
struct packed {
logic q; // [41]
- } e23;
+ } e21;
struct packed {
logic q; // [40]
- } e24;
+ } e22;
struct packed {
logic q; // [39]
- } e25;
+ } e23;
struct packed {
logic q; // [38]
- } e26;
+ } e24;
struct packed {
logic q; // [37]
- } e27;
+ } e25;
struct packed {
logic q; // [36]
- } e28;
+ } e26;
struct packed {
logic q; // [35]
- } e29;
+ } e27;
struct packed {
logic q; // [34]
- } e30;
+ } e28;
struct packed {
logic q; // [33]
+ } e29;
+ struct packed {
+ logic q; // [32]
+ } e30;
+ struct packed {
+ logic q; // [31]
} e31;
} ie00;
struct packed {
struct packed {
- logic q; // [32]
+ logic q; // [30]
} e32;
struct packed {
- logic q; // [31]
+ logic q; // [29]
} e33;
struct packed {
- logic q; // [30]
+ logic q; // [28]
} e34;
struct packed {
- logic q; // [29]
+ logic q; // [27]
} e35;
struct packed {
- logic q; // [28]
+ logic q; // [26]
} e36;
struct packed {
- logic q; // [27]
+ logic q; // [25]
} e37;
struct packed {
- logic q; // [26]
+ logic q; // [24]
} e38;
struct packed {
- logic q; // [25]
+ logic q; // [23]
} e39;
struct packed {
- logic q; // [24]
+ logic q; // [22]
} e40;
struct packed {
- logic q; // [23]
+ logic q; // [21]
} e41;
struct packed {
- logic q; // [22]
+ logic q; // [20]
} e42;
struct packed {
- logic q; // [21]
+ logic q; // [19]
} e43;
struct packed {
- logic q; // [20]
+ logic q; // [18]
} e44;
struct packed {
- logic q; // [19]
+ logic q; // [17]
} e45;
struct packed {
- logic q; // [18]
+ logic q; // [16]
} e46;
struct packed {
- logic q; // [17]
+ logic q; // [15]
} e47;
struct packed {
- logic q; // [16]
+ logic q; // [14]
} e48;
struct packed {
- logic q; // [15]
+ logic q; // [13]
} e49;
struct packed {
- logic q; // [14]
+ logic q; // [12]
} e50;
struct packed {
- logic q; // [13]
- } e51;
- struct packed {
- logic q; // [12]
- } e52;
- struct packed {
logic q; // [11]
- } e53;
+ } e51;
} ie01;
struct packed {
logic [1:0] q; // [10:9]
@@ -521,223 +503,215 @@
struct packed {
struct packed {
- logic d; // [113]
- logic de; // [112]
- } p0;
- struct packed {
- logic d; // [111]
- logic de; // [110]
- } p1;
- struct packed {
logic d; // [109]
logic de; // [108]
- } p2;
+ } p0;
struct packed {
logic d; // [107]
logic de; // [106]
- } p3;
+ } p1;
struct packed {
logic d; // [105]
logic de; // [104]
- } p4;
+ } p2;
struct packed {
logic d; // [103]
logic de; // [102]
- } p5;
+ } p3;
struct packed {
logic d; // [101]
logic de; // [100]
- } p6;
+ } p4;
struct packed {
logic d; // [99]
logic de; // [98]
- } p7;
+ } p5;
struct packed {
logic d; // [97]
logic de; // [96]
- } p8;
+ } p6;
struct packed {
logic d; // [95]
logic de; // [94]
- } p9;
+ } p7;
struct packed {
logic d; // [93]
logic de; // [92]
- } p10;
+ } p8;
struct packed {
logic d; // [91]
logic de; // [90]
- } p11;
+ } p9;
struct packed {
logic d; // [89]
logic de; // [88]
- } p12;
+ } p10;
struct packed {
logic d; // [87]
logic de; // [86]
- } p13;
+ } p11;
struct packed {
logic d; // [85]
logic de; // [84]
- } p14;
+ } p12;
struct packed {
logic d; // [83]
logic de; // [82]
- } p15;
+ } p13;
struct packed {
logic d; // [81]
logic de; // [80]
- } p16;
+ } p14;
struct packed {
logic d; // [79]
logic de; // [78]
- } p17;
+ } p15;
struct packed {
logic d; // [77]
logic de; // [76]
- } p18;
+ } p16;
struct packed {
logic d; // [75]
logic de; // [74]
- } p19;
+ } p17;
struct packed {
logic d; // [73]
logic de; // [72]
- } p20;
+ } p18;
struct packed {
logic d; // [71]
logic de; // [70]
- } p21;
+ } p19;
struct packed {
logic d; // [69]
logic de; // [68]
- } p22;
+ } p20;
struct packed {
logic d; // [67]
logic de; // [66]
- } p23;
+ } p21;
struct packed {
logic d; // [65]
logic de; // [64]
- } p24;
+ } p22;
struct packed {
logic d; // [63]
logic de; // [62]
- } p25;
+ } p23;
struct packed {
logic d; // [61]
logic de; // [60]
- } p26;
+ } p24;
struct packed {
logic d; // [59]
logic de; // [58]
- } p27;
+ } p25;
struct packed {
logic d; // [57]
logic de; // [56]
- } p28;
+ } p26;
struct packed {
logic d; // [55]
logic de; // [54]
- } p29;
+ } p27;
struct packed {
logic d; // [53]
logic de; // [52]
- } p30;
+ } p28;
struct packed {
logic d; // [51]
logic de; // [50]
+ } p29;
+ struct packed {
+ logic d; // [49]
+ logic de; // [48]
+ } p30;
+ struct packed {
+ logic d; // [47]
+ logic de; // [46]
} p31;
} ip0;
struct packed {
struct packed {
- logic d; // [49]
- logic de; // [48]
- } p32;
- struct packed {
- logic d; // [47]
- logic de; // [46]
- } p33;
- struct packed {
logic d; // [45]
logic de; // [44]
- } p34;
+ } p32;
struct packed {
logic d; // [43]
logic de; // [42]
- } p35;
+ } p33;
struct packed {
logic d; // [41]
logic de; // [40]
- } p36;
+ } p34;
struct packed {
logic d; // [39]
logic de; // [38]
- } p37;
+ } p35;
struct packed {
logic d; // [37]
logic de; // [36]
- } p38;
+ } p36;
struct packed {
logic d; // [35]
logic de; // [34]
- } p39;
+ } p37;
struct packed {
logic d; // [33]
logic de; // [32]
- } p40;
+ } p38;
struct packed {
logic d; // [31]
logic de; // [30]
- } p41;
+ } p39;
struct packed {
logic d; // [29]
logic de; // [28]
- } p42;
+ } p40;
struct packed {
logic d; // [27]
logic de; // [26]
- } p43;
+ } p41;
struct packed {
logic d; // [25]
logic de; // [24]
- } p44;
+ } p42;
struct packed {
logic d; // [23]
logic de; // [22]
- } p45;
+ } p43;
struct packed {
logic d; // [21]
logic de; // [20]
- } p46;
+ } p44;
struct packed {
logic d; // [19]
logic de; // [18]
- } p47;
+ } p45;
struct packed {
logic d; // [17]
logic de; // [16]
- } p48;
+ } p46;
struct packed {
logic d; // [15]
logic de; // [14]
- } p49;
+ } p47;
struct packed {
logic d; // [13]
logic de; // [12]
- } p50;
+ } p48;
struct packed {
logic d; // [11]
logic de; // [10]
- } p51;
+ } p49;
struct packed {
logic d; // [9]
logic de; // [8]
- } p52;
+ } p50;
struct packed {
logic d; // [7]
logic de; // [6]
- } p53;
+ } p51;
} ip1;
struct packed {
logic [5:0] d; // [5:0]
@@ -801,8 +775,6 @@
parameter RV_PLIC_PRIO49_OFFSET = 9'h d4;
parameter RV_PLIC_PRIO50_OFFSET = 9'h d8;
parameter RV_PLIC_PRIO51_OFFSET = 9'h dc;
- parameter RV_PLIC_PRIO52_OFFSET = 9'h e0;
- parameter RV_PLIC_PRIO53_OFFSET = 9'h e4;
parameter RV_PLIC_IE00_OFFSET = 9'h 100;
parameter RV_PLIC_IE01_OFFSET = 9'h 104;
parameter RV_PLIC_THRESHOLD0_OFFSET = 9'h 108;
diff --git a/hw/top_earlgrey/rtl/rv_plic_reg_top.sv b/hw/top_earlgrey/rtl/rv_plic_reg_top.sv
index 7f56d4f..f64f327 100644
--- a/hw/top_earlgrey/rtl/rv_plic_reg_top.sv
+++ b/hw/top_earlgrey/rtl/rv_plic_reg_top.sv
@@ -180,8 +180,6 @@
logic ip1_p49_qs;
logic ip1_p50_qs;
logic ip1_p51_qs;
- logic ip1_p52_qs;
- logic ip1_p53_qs;
logic le0_le0_qs;
logic le0_le0_wd;
logic le0_le0_we;
@@ -338,12 +336,6 @@
logic le1_le51_qs;
logic le1_le51_wd;
logic le1_le51_we;
- logic le1_le52_qs;
- logic le1_le52_wd;
- logic le1_le52_we;
- logic le1_le53_qs;
- logic le1_le53_wd;
- logic le1_le53_we;
logic [1:0] prio0_qs;
logic [1:0] prio0_wd;
logic prio0_we;
@@ -500,12 +492,6 @@
logic [1:0] prio51_qs;
logic [1:0] prio51_wd;
logic prio51_we;
- logic [1:0] prio52_qs;
- logic [1:0] prio52_wd;
- logic prio52_we;
- logic [1:0] prio53_qs;
- logic [1:0] prio53_wd;
- logic prio53_we;
logic ie00_e0_qs;
logic ie00_e0_wd;
logic ie00_e0_we;
@@ -662,12 +648,6 @@
logic ie01_e51_qs;
logic ie01_e51_wd;
logic ie01_e51_we;
- logic ie01_e52_qs;
- logic ie01_e52_wd;
- logic ie01_e52_we;
- logic ie01_e53_qs;
- logic ie01_e53_wd;
- logic ie01_e53_we;
logic [1:0] threshold0_qs;
logic [1:0] threshold0_wd;
logic threshold0_we;
@@ -1984,56 +1964,6 @@
);
- // F[p52]: 20:20
- prim_subreg #(
- .DW (1),
- .SWACCESS("RO"),
- .RESVAL (1'h0)
- ) u_ip1_p52 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
-
- .we (1'b0),
- .wd ('0 ),
-
- // from internal hardware
- .de (hw2reg.ip1.p52.de),
- .d (hw2reg.ip1.p52.d ),
-
- // to internal hardware
- .qe (),
- .q (),
-
- // to register interface (read)
- .qs (ip1_p52_qs)
- );
-
-
- // F[p53]: 21:21
- prim_subreg #(
- .DW (1),
- .SWACCESS("RO"),
- .RESVAL (1'h0)
- ) u_ip1_p53 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
-
- .we (1'b0),
- .wd ('0 ),
-
- // from internal hardware
- .de (hw2reg.ip1.p53.de),
- .d (hw2reg.ip1.p53.d ),
-
- // to internal hardware
- .qe (),
- .q (),
-
- // to register interface (read)
- .qs (ip1_p53_qs)
- );
-
-
// R[le0]: V(False)
// F[le0]: 0:0
@@ -3390,58 +3320,6 @@
);
- // F[le52]: 20:20
- prim_subreg #(
- .DW (1),
- .SWACCESS("RW"),
- .RESVAL (1'h0)
- ) u_le1_le52 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
-
- // from register interface
- .we (le1_le52_we),
- .wd (le1_le52_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0 ),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.le1.le52.q ),
-
- // to register interface (read)
- .qs (le1_le52_qs)
- );
-
-
- // F[le53]: 21:21
- prim_subreg #(
- .DW (1),
- .SWACCESS("RW"),
- .RESVAL (1'h0)
- ) u_le1_le53 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
-
- // from register interface
- .we (le1_le53_we),
- .wd (le1_le53_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0 ),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.le1.le53.q ),
-
- // to register interface (read)
- .qs (le1_le53_qs)
- );
-
-
// R[prio0]: V(False)
prim_subreg #(
@@ -4846,60 +4724,6 @@
);
- // R[prio52]: V(False)
-
- prim_subreg #(
- .DW (2),
- .SWACCESS("RW"),
- .RESVAL (2'h0)
- ) u_prio52 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
-
- // from register interface
- .we (prio52_we),
- .wd (prio52_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0 ),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.prio52.q ),
-
- // to register interface (read)
- .qs (prio52_qs)
- );
-
-
- // R[prio53]: V(False)
-
- prim_subreg #(
- .DW (2),
- .SWACCESS("RW"),
- .RESVAL (2'h0)
- ) u_prio53 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
-
- // from register interface
- .we (prio53_we),
- .wd (prio53_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0 ),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.prio53.q ),
-
- // to register interface (read)
- .qs (prio53_qs)
- );
-
-
// R[ie00]: V(False)
// F[e0]: 0:0
@@ -6256,58 +6080,6 @@
);
- // F[e52]: 20:20
- prim_subreg #(
- .DW (1),
- .SWACCESS("RW"),
- .RESVAL (1'h0)
- ) u_ie01_e52 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
-
- // from register interface
- .we (ie01_e52_we),
- .wd (ie01_e52_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0 ),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.ie01.e52.q ),
-
- // to register interface (read)
- .qs (ie01_e52_qs)
- );
-
-
- // F[e53]: 21:21
- prim_subreg #(
- .DW (1),
- .SWACCESS("RW"),
- .RESVAL (1'h0)
- ) u_ie01_e53 (
- .clk_i (clk_i ),
- .rst_ni (rst_ni ),
-
- // from register interface
- .we (ie01_e53_we),
- .wd (ie01_e53_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0 ),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.ie01.e53.q ),
-
- // to register interface (read)
- .qs (ie01_e53_qs)
- );
-
-
// R[threshold0]: V(False)
prim_subreg #(
@@ -6379,7 +6151,7 @@
- logic [62:0] addr_hit;
+ logic [60:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[0] = (reg_addr == RV_PLIC_IP0_OFFSET);
@@ -6438,13 +6210,11 @@
addr_hit[53] = (reg_addr == RV_PLIC_PRIO49_OFFSET);
addr_hit[54] = (reg_addr == RV_PLIC_PRIO50_OFFSET);
addr_hit[55] = (reg_addr == RV_PLIC_PRIO51_OFFSET);
- addr_hit[56] = (reg_addr == RV_PLIC_PRIO52_OFFSET);
- addr_hit[57] = (reg_addr == RV_PLIC_PRIO53_OFFSET);
- addr_hit[58] = (reg_addr == RV_PLIC_IE00_OFFSET);
- addr_hit[59] = (reg_addr == RV_PLIC_IE01_OFFSET);
- addr_hit[60] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET);
- addr_hit[61] = (reg_addr == RV_PLIC_CC0_OFFSET);
- addr_hit[62] = (reg_addr == RV_PLIC_MSIP0_OFFSET);
+ addr_hit[56] = (reg_addr == RV_PLIC_IE00_OFFSET);
+ addr_hit[57] = (reg_addr == RV_PLIC_IE01_OFFSET);
+ addr_hit[58] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET);
+ addr_hit[59] = (reg_addr == RV_PLIC_CC0_OFFSET);
+ addr_hit[60] = (reg_addr == RV_PLIC_MSIP0_OFFSET);
end
always_ff @(posedge clk_i or negedge rst_ni) begin
@@ -6509,8 +6279,6 @@
-
-
assign le0_le0_we = addr_hit[2] && reg_we;
assign le0_le0_wd = reg_wdata[0];
@@ -6667,12 +6435,6 @@
assign le1_le51_we = addr_hit[3] && reg_we;
assign le1_le51_wd = reg_wdata[19];
- assign le1_le52_we = addr_hit[3] && reg_we;
- assign le1_le52_wd = reg_wdata[20];
-
- assign le1_le53_we = addr_hit[3] && reg_we;
- assign le1_le53_wd = reg_wdata[21];
-
assign prio0_we = addr_hit[4] && reg_we;
assign prio0_wd = reg_wdata[1:0];
@@ -6829,182 +6591,170 @@
assign prio51_we = addr_hit[55] && reg_we;
assign prio51_wd = reg_wdata[1:0];
- assign prio52_we = addr_hit[56] && reg_we;
- assign prio52_wd = reg_wdata[1:0];
-
- assign prio53_we = addr_hit[57] && reg_we;
- assign prio53_wd = reg_wdata[1:0];
-
- assign ie00_e0_we = addr_hit[58] && reg_we;
+ assign ie00_e0_we = addr_hit[56] && reg_we;
assign ie00_e0_wd = reg_wdata[0];
- assign ie00_e1_we = addr_hit[58] && reg_we;
+ assign ie00_e1_we = addr_hit[56] && reg_we;
assign ie00_e1_wd = reg_wdata[1];
- assign ie00_e2_we = addr_hit[58] && reg_we;
+ assign ie00_e2_we = addr_hit[56] && reg_we;
assign ie00_e2_wd = reg_wdata[2];
- assign ie00_e3_we = addr_hit[58] && reg_we;
+ assign ie00_e3_we = addr_hit[56] && reg_we;
assign ie00_e3_wd = reg_wdata[3];
- assign ie00_e4_we = addr_hit[58] && reg_we;
+ assign ie00_e4_we = addr_hit[56] && reg_we;
assign ie00_e4_wd = reg_wdata[4];
- assign ie00_e5_we = addr_hit[58] && reg_we;
+ assign ie00_e5_we = addr_hit[56] && reg_we;
assign ie00_e5_wd = reg_wdata[5];
- assign ie00_e6_we = addr_hit[58] && reg_we;
+ assign ie00_e6_we = addr_hit[56] && reg_we;
assign ie00_e6_wd = reg_wdata[6];
- assign ie00_e7_we = addr_hit[58] && reg_we;
+ assign ie00_e7_we = addr_hit[56] && reg_we;
assign ie00_e7_wd = reg_wdata[7];
- assign ie00_e8_we = addr_hit[58] && reg_we;
+ assign ie00_e8_we = addr_hit[56] && reg_we;
assign ie00_e8_wd = reg_wdata[8];
- assign ie00_e9_we = addr_hit[58] && reg_we;
+ assign ie00_e9_we = addr_hit[56] && reg_we;
assign ie00_e9_wd = reg_wdata[9];
- assign ie00_e10_we = addr_hit[58] && reg_we;
+ assign ie00_e10_we = addr_hit[56] && reg_we;
assign ie00_e10_wd = reg_wdata[10];
- assign ie00_e11_we = addr_hit[58] && reg_we;
+ assign ie00_e11_we = addr_hit[56] && reg_we;
assign ie00_e11_wd = reg_wdata[11];
- assign ie00_e12_we = addr_hit[58] && reg_we;
+ assign ie00_e12_we = addr_hit[56] && reg_we;
assign ie00_e12_wd = reg_wdata[12];
- assign ie00_e13_we = addr_hit[58] && reg_we;
+ assign ie00_e13_we = addr_hit[56] && reg_we;
assign ie00_e13_wd = reg_wdata[13];
- assign ie00_e14_we = addr_hit[58] && reg_we;
+ assign ie00_e14_we = addr_hit[56] && reg_we;
assign ie00_e14_wd = reg_wdata[14];
- assign ie00_e15_we = addr_hit[58] && reg_we;
+ assign ie00_e15_we = addr_hit[56] && reg_we;
assign ie00_e15_wd = reg_wdata[15];
- assign ie00_e16_we = addr_hit[58] && reg_we;
+ assign ie00_e16_we = addr_hit[56] && reg_we;
assign ie00_e16_wd = reg_wdata[16];
- assign ie00_e17_we = addr_hit[58] && reg_we;
+ assign ie00_e17_we = addr_hit[56] && reg_we;
assign ie00_e17_wd = reg_wdata[17];
- assign ie00_e18_we = addr_hit[58] && reg_we;
+ assign ie00_e18_we = addr_hit[56] && reg_we;
assign ie00_e18_wd = reg_wdata[18];
- assign ie00_e19_we = addr_hit[58] && reg_we;
+ assign ie00_e19_we = addr_hit[56] && reg_we;
assign ie00_e19_wd = reg_wdata[19];
- assign ie00_e20_we = addr_hit[58] && reg_we;
+ assign ie00_e20_we = addr_hit[56] && reg_we;
assign ie00_e20_wd = reg_wdata[20];
- assign ie00_e21_we = addr_hit[58] && reg_we;
+ assign ie00_e21_we = addr_hit[56] && reg_we;
assign ie00_e21_wd = reg_wdata[21];
- assign ie00_e22_we = addr_hit[58] && reg_we;
+ assign ie00_e22_we = addr_hit[56] && reg_we;
assign ie00_e22_wd = reg_wdata[22];
- assign ie00_e23_we = addr_hit[58] && reg_we;
+ assign ie00_e23_we = addr_hit[56] && reg_we;
assign ie00_e23_wd = reg_wdata[23];
- assign ie00_e24_we = addr_hit[58] && reg_we;
+ assign ie00_e24_we = addr_hit[56] && reg_we;
assign ie00_e24_wd = reg_wdata[24];
- assign ie00_e25_we = addr_hit[58] && reg_we;
+ assign ie00_e25_we = addr_hit[56] && reg_we;
assign ie00_e25_wd = reg_wdata[25];
- assign ie00_e26_we = addr_hit[58] && reg_we;
+ assign ie00_e26_we = addr_hit[56] && reg_we;
assign ie00_e26_wd = reg_wdata[26];
- assign ie00_e27_we = addr_hit[58] && reg_we;
+ assign ie00_e27_we = addr_hit[56] && reg_we;
assign ie00_e27_wd = reg_wdata[27];
- assign ie00_e28_we = addr_hit[58] && reg_we;
+ assign ie00_e28_we = addr_hit[56] && reg_we;
assign ie00_e28_wd = reg_wdata[28];
- assign ie00_e29_we = addr_hit[58] && reg_we;
+ assign ie00_e29_we = addr_hit[56] && reg_we;
assign ie00_e29_wd = reg_wdata[29];
- assign ie00_e30_we = addr_hit[58] && reg_we;
+ assign ie00_e30_we = addr_hit[56] && reg_we;
assign ie00_e30_wd = reg_wdata[30];
- assign ie00_e31_we = addr_hit[58] && reg_we;
+ assign ie00_e31_we = addr_hit[56] && reg_we;
assign ie00_e31_wd = reg_wdata[31];
- assign ie01_e32_we = addr_hit[59] && reg_we;
+ assign ie01_e32_we = addr_hit[57] && reg_we;
assign ie01_e32_wd = reg_wdata[0];
- assign ie01_e33_we = addr_hit[59] && reg_we;
+ assign ie01_e33_we = addr_hit[57] && reg_we;
assign ie01_e33_wd = reg_wdata[1];
- assign ie01_e34_we = addr_hit[59] && reg_we;
+ assign ie01_e34_we = addr_hit[57] && reg_we;
assign ie01_e34_wd = reg_wdata[2];
- assign ie01_e35_we = addr_hit[59] && reg_we;
+ assign ie01_e35_we = addr_hit[57] && reg_we;
assign ie01_e35_wd = reg_wdata[3];
- assign ie01_e36_we = addr_hit[59] && reg_we;
+ assign ie01_e36_we = addr_hit[57] && reg_we;
assign ie01_e36_wd = reg_wdata[4];
- assign ie01_e37_we = addr_hit[59] && reg_we;
+ assign ie01_e37_we = addr_hit[57] && reg_we;
assign ie01_e37_wd = reg_wdata[5];
- assign ie01_e38_we = addr_hit[59] && reg_we;
+ assign ie01_e38_we = addr_hit[57] && reg_we;
assign ie01_e38_wd = reg_wdata[6];
- assign ie01_e39_we = addr_hit[59] && reg_we;
+ assign ie01_e39_we = addr_hit[57] && reg_we;
assign ie01_e39_wd = reg_wdata[7];
- assign ie01_e40_we = addr_hit[59] && reg_we;
+ assign ie01_e40_we = addr_hit[57] && reg_we;
assign ie01_e40_wd = reg_wdata[8];
- assign ie01_e41_we = addr_hit[59] && reg_we;
+ assign ie01_e41_we = addr_hit[57] && reg_we;
assign ie01_e41_wd = reg_wdata[9];
- assign ie01_e42_we = addr_hit[59] && reg_we;
+ assign ie01_e42_we = addr_hit[57] && reg_we;
assign ie01_e42_wd = reg_wdata[10];
- assign ie01_e43_we = addr_hit[59] && reg_we;
+ assign ie01_e43_we = addr_hit[57] && reg_we;
assign ie01_e43_wd = reg_wdata[11];
- assign ie01_e44_we = addr_hit[59] && reg_we;
+ assign ie01_e44_we = addr_hit[57] && reg_we;
assign ie01_e44_wd = reg_wdata[12];
- assign ie01_e45_we = addr_hit[59] && reg_we;
+ assign ie01_e45_we = addr_hit[57] && reg_we;
assign ie01_e45_wd = reg_wdata[13];
- assign ie01_e46_we = addr_hit[59] && reg_we;
+ assign ie01_e46_we = addr_hit[57] && reg_we;
assign ie01_e46_wd = reg_wdata[14];
- assign ie01_e47_we = addr_hit[59] && reg_we;
+ assign ie01_e47_we = addr_hit[57] && reg_we;
assign ie01_e47_wd = reg_wdata[15];
- assign ie01_e48_we = addr_hit[59] && reg_we;
+ assign ie01_e48_we = addr_hit[57] && reg_we;
assign ie01_e48_wd = reg_wdata[16];
- assign ie01_e49_we = addr_hit[59] && reg_we;
+ assign ie01_e49_we = addr_hit[57] && reg_we;
assign ie01_e49_wd = reg_wdata[17];
- assign ie01_e50_we = addr_hit[59] && reg_we;
+ assign ie01_e50_we = addr_hit[57] && reg_we;
assign ie01_e50_wd = reg_wdata[18];
- assign ie01_e51_we = addr_hit[59] && reg_we;
+ assign ie01_e51_we = addr_hit[57] && reg_we;
assign ie01_e51_wd = reg_wdata[19];
- assign ie01_e52_we = addr_hit[59] && reg_we;
- assign ie01_e52_wd = reg_wdata[20];
-
- assign ie01_e53_we = addr_hit[59] && reg_we;
- assign ie01_e53_wd = reg_wdata[21];
-
- assign threshold0_we = addr_hit[60] && reg_we;
+ assign threshold0_we = addr_hit[58] && reg_we;
assign threshold0_wd = reg_wdata[1:0];
- assign cc0_we = addr_hit[61] && reg_we;
+ assign cc0_we = addr_hit[59] && reg_we;
assign cc0_wd = reg_wdata[5:0];
- assign cc0_re = addr_hit[61] && reg_re;
+ assign cc0_re = addr_hit[59] && reg_re;
- assign msip0_we = addr_hit[62] && reg_we;
+ assign msip0_we = addr_hit[60] && reg_we;
assign msip0_wd = reg_wdata[0];
// Read data return
@@ -7068,8 +6818,6 @@
reg_rdata_next[17] = ip1_p49_qs;
reg_rdata_next[18] = ip1_p50_qs;
reg_rdata_next[19] = ip1_p51_qs;
- reg_rdata_next[20] = ip1_p52_qs;
- reg_rdata_next[21] = ip1_p53_qs;
end
addr_hit[2]: begin
@@ -7128,8 +6876,6 @@
reg_rdata_next[17] = le1_le49_qs;
reg_rdata_next[18] = le1_le50_qs;
reg_rdata_next[19] = le1_le51_qs;
- reg_rdata_next[20] = le1_le52_qs;
- reg_rdata_next[21] = le1_le53_qs;
end
addr_hit[4]: begin
@@ -7341,14 +7087,6 @@
end
addr_hit[56]: begin
- reg_rdata_next[1:0] = prio52_qs;
- end
-
- addr_hit[57]: begin
- reg_rdata_next[1:0] = prio53_qs;
- end
-
- addr_hit[58]: begin
reg_rdata_next[0] = ie00_e0_qs;
reg_rdata_next[1] = ie00_e1_qs;
reg_rdata_next[2] = ie00_e2_qs;
@@ -7383,7 +7121,7 @@
reg_rdata_next[31] = ie00_e31_qs;
end
- addr_hit[59]: begin
+ addr_hit[57]: begin
reg_rdata_next[0] = ie01_e32_qs;
reg_rdata_next[1] = ie01_e33_qs;
reg_rdata_next[2] = ie01_e34_qs;
@@ -7404,19 +7142,17 @@
reg_rdata_next[17] = ie01_e49_qs;
reg_rdata_next[18] = ie01_e50_qs;
reg_rdata_next[19] = ie01_e51_qs;
- reg_rdata_next[20] = ie01_e52_qs;
- reg_rdata_next[21] = ie01_e53_qs;
end
- addr_hit[60]: begin
+ addr_hit[58]: begin
reg_rdata_next[1:0] = threshold0_qs;
end
- addr_hit[61]: begin
+ addr_hit[59]: begin
reg_rdata_next[5:0] = cc0_qs;
end
- addr_hit[62]: begin
+ addr_hit[60]: begin
reg_rdata_next[0] = msip0_qs;
end
diff --git a/hw/top_earlgrey/rtl/top_earlgrey.sv b/hw/top_earlgrey/rtl/top_earlgrey.sv
index 8128ba7..b67b3b3 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey.sv
@@ -74,7 +74,7 @@
tl_d2h_t tl_ram_main_d_d2h;
tl_h2d_t tl_eflash_d_h2d;
tl_d2h_t tl_eflash_d_d2h;
- logic [53:0] intr_vector;
+ logic [51:0] intr_vector;
// Interrupt source list
logic intr_uart_tx_watermark;
logic intr_uart_rx_watermark;
@@ -85,10 +85,8 @@
logic intr_uart_rx_timeout;
logic intr_uart_rx_parity_err;
logic [31:0] intr_gpio_gpio;
- logic intr_spi_device_rxne;
+ logic intr_spi_device_rxf;
logic intr_spi_device_rxlvl;
- logic intr_spi_device_txe;
- logic intr_spi_device_txf;
logic intr_spi_device_txlvl;
logic intr_spi_device_rxerr;
logic intr_flash_ctrl_prog_empty;
@@ -360,10 +358,8 @@
.cio_mosi_i (cio_spi_device_mosi_p2d_i),
.cio_miso_o (cio_spi_device_miso_d2p_o),
.cio_miso_en_o (cio_spi_device_miso_en_d2p_o),
- .intr_rxne_o (intr_spi_device_rxne),
+ .intr_rxf_o (intr_spi_device_rxf),
.intr_rxlvl_o (intr_spi_device_rxlvl),
- .intr_txe_o (intr_spi_device_txe),
- .intr_txf_o (intr_spi_device_txf),
.intr_txlvl_o (intr_spi_device_txlvl),
.intr_rxerr_o (intr_spi_device_rxerr),
.clk_i(clk_i),
@@ -427,10 +423,8 @@
intr_flash_ctrl_prog_empty,
intr_spi_device_rxerr,
intr_spi_device_txlvl,
- intr_spi_device_txf,
- intr_spi_device_txe,
intr_spi_device_rxlvl,
- intr_spi_device_rxne,
+ intr_spi_device_rxf,
intr_uart_rx_parity_err,
intr_uart_rx_timeout,
intr_uart_rx_break_err,
