[AST] Update ENV_ISO & More
Signed-off-by: Jacob Levy <jacob.levy@opentitan.org>
diff --git a/hw/top_earlgrey/ip/ast/ast.core b/hw/top_earlgrey/ip/ast/ast.core
index 2d70633..481e34f 100644
--- a/hw/top_earlgrey/ip/ast/ast.core
+++ b/hw/top_earlgrey/ip/ast/ast.core
@@ -37,12 +37,11 @@
- rtl/io_osc.sv
- rtl/rglts_pdm_3p3v.sv
- rtl/rng.sv
- - rtl/rng_osc.sv
- rtl/sys_clk.sv
- rtl/sys_osc.sv
- rtl/usb_clk.sv
- rtl/usb_osc.sv
-
+
file_type: systemVerilogSource
@@ -71,7 +70,7 @@
- "-Wall"
sim:
- <<: *default_target
+ <<: *default_target
default_tool: vcs
filesets:
- files_rtl
@@ -79,3 +78,4 @@
vcs:
vcs_options: [-timescale=1ns/1ps -l vcs.log]
toplevel: ast
+
diff --git a/hw/top_earlgrey/ip/ast/rtl/ast.sv b/hw/top_earlgrey/ip/ast/rtl/ast.sv
index d473c4e..e709ea8 100644
--- a/hw/top_earlgrey/ip/ast/rtl/ast.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/ast.sv
@@ -13,7 +13,7 @@
parameter int AdcDataWidth = 10,
parameter int EntropyStreams = 4,
parameter int Ast2PadOutWidth = 16, // TODO:final size
- parameter int Pad2AstInWidth = 6, // TODO:final size
+ parameter int Pad2AstInWidth = 16, // TODO:final size
parameter int UsbCalibWidth = 16 // TODO:final size
) (
// tlul if
@@ -52,7 +52,7 @@
// Power and IO pin connections
input main_pd_ni, // MAIN Regulator Power Down
- input main_iso_en_i, // Isolation enable for main core power (VCMAIN).
+ input main_env_iso_en_i, // Enveloped ISOlation ENable for MAIN
// power down monitor logic - flash/otp related
output logic flash_power_down_h_o, // Flash Power Down
@@ -282,7 +282,7 @@
.vcmain_pok_o_h_i ( vcmain_pok_por ),
.clk_src_aon_h_i ( clk_src_aon_o ),
.main_pd_h_ni ( main_pd_ni ),
- .main_iso_en_i ( main_iso_en_i ),
+ .main_env_iso_en_h_i ( main_env_iso_en_i ),
.otp_power_seq_h_i ( otp_power_seq_i[1:0] ),
.vcaon_pok_h_o ( vcaon_pok_h_int ),
.main_pwr_dly_o ( main_pwr_dly_o ),
@@ -412,15 +412,17 @@
///////////////////////////////////////
// RNG (Always ON)
///////////////////////////////////////
+
rng #(
.EntropyStreams ( EntropyStreams )
) u_rng (
- .clk_i ( clk_ast_rng_i ),
- .rst_ni ( rst_ast_rng_ni ),
- .vcaon_pok_i ( vcaon_pok ),
+ .clk_i ( clk_ast_tlul_i ),
+ .rst_ni ( rst_ast_tlul_ni ),
+ .clk_ast_rng_i ( clk_ast_rng_i ),
+ .rst_ast_rng_ni ( rst_ast_rng_ni ),
.rng_en_i ( rng_en_i ),
+ .rng_fips_i ( rng_fips_i ),
.scan_mode_i ( scan_mode ),
- .scan_reset_ni ( scan_reset_n ),
.rng_b_o ( rng_b_o[EntropyStreams-1:0] ),
.rng_val_o ( rng_val_o )
); // of u_rng
diff --git a/hw/top_earlgrey/ip/ast/rtl/ast_entropy.sv b/hw/top_earlgrey/ip/ast/rtl/ast_entropy.sv
index d94823d..0fe2205 100644
--- a/hw/top_earlgrey/ip/ast/rtl/ast_entropy.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/ast_entropy.sv
@@ -139,7 +139,7 @@
.ResetValue ( 1'b0 )
) u_entropy_clr_sync (
.clk_i ( clk_ast_es_i ),
- .rst_ni ( rst_ast_es_ni ),
+ .rst_ni ( 1'b1 ),
.d_i ( !(clk_src_sys_en_i && clk_src_sys_jen_i) ),
.q_o ( entropy_clr )
);
diff --git a/hw/top_earlgrey/ip/ast/rtl/ast_pkg.sv b/hw/top_earlgrey/ip/ast/rtl/ast_pkg.sv
index c2255b0..f721cb3 100644
--- a/hw/top_earlgrey/ip/ast/rtl/ast_pkg.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/ast_pkg.sv
@@ -18,19 +18,19 @@
parameter int AdcDataWidth = top_pkg::ADC_DATAW;
parameter int UsbCalibWidth = 16;
parameter int Ast2PadOutWidth = 10;
- parameter int Pad2AstInWidth = 6;
+ parameter int Pad2AstInWidth = 10;
// Memories Read-Write Margin Interface
typedef struct packed {
- logic marg_en_a;
- logic [3:0] marg_a;
- logic marg_en_b;
- logic [3:0] marg_b;
+ logic marg_en_a;
+ logic [4-1:0] marg_a;
+ logic marg_en_b;
+ logic [4-1:0] marg_b;
} dpm_rm_t;
typedef struct packed {
- logic marg_en;
- logic [3:0] marg;
+ logic marg_en;
+ logic [4-1:0] marg;
} spm_rm_t;
// ADC Interface
diff --git a/hw/top_earlgrey/ip/ast/rtl/rglts_pdm_3p3v.sv b/hw/top_earlgrey/ip/ast/rtl/rglts_pdm_3p3v.sv
index 34abfd3..c51b9a6 100644
--- a/hw/top_earlgrey/ip/ast/rtl/rglts_pdm_3p3v.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/rglts_pdm_3p3v.sv
@@ -16,8 +16,8 @@
input vcmain_pok_h_i, // VCMAIN (1.1v) Exist @3.3v
input vcmain_pok_o_h_i, // vcmain_pok_o signal (1.1v) @3.3v
input clk_src_aon_h_i, // AON Clock @3.3v
- input main_pd_h_ni, // VCMAIN/Regulator Power Down @3.3v
- input main_iso_en_i, // Isolation enable for main core power (VCMAIN).
+ input main_pd_h_ni, // MAIN Regulator Power Down @3.3v
+ input main_env_iso_en_h_i, // Enveloped ISOlation ENable for MAIN @3.3v
input [1:0] otp_power_seq_h_i, // MMR0,24 in @3.3v
output logic vcaon_pok_h_o, // VCAON (1.1v) Exist @3.3v
output logic main_pwr_dly_o, // For modeling only.
diff --git a/hw/top_earlgrey/ip/ast/rtl/rng.sv b/hw/top_earlgrey/ip/ast/rtl/rng.sv
index 5b38ee8..375fa35 100644
--- a/hw/top_earlgrey/ip/ast/rtl/rng.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/rng.sv
@@ -9,43 +9,27 @@
module rng #(
parameter int EntropyStreams = 4
) (
- input clk_i,
- input rst_ni,
- input vcaon_pok_i,
- input rng_en_i,
- input scan_mode_i,
- input scan_reset_ni,
- output logic [EntropyStreams-1:0] rng_b_o,
- output logic rng_val_o
+ input clk_i, // Non-Jittery Clock (TLUL)
+ input rst_ni, // Non-Jittery Reset (TLUL)
+ input clk_ast_rng_i, // Jittery Clock (RNG)
+ input rst_ast_rng_ni, // Jittery Reset (RNG)
+ input rng_en_i, // RNG Enable
+ input rng_fips_i, // RNG FIPS Enable
+ input scan_mode_i, // Scan Mode
+ output logic [EntropyStreams-1:0] rng_b_o, // RNG Bus/Bits Output
+ output logic rng_val_o // RNG Bus/Bits Valid
);
///////////////////////////////////////
-// Clock Oscilator
+// RNG Bus using LFSR
///////////////////////////////////////
-logic clk, rng_clk_en, rng_clk;
-
-// clock Oschilator
-////////////////////////////////////////
-logic rng_clk_o;
-
-// For FPGA, it can be replace with clk_src_aon_o/4 (200K/4=50K)
-rng_osc u_rng_osc (
- .vcaon_pok_i ( vcaon_pok_i ),
- .rng_en_i ( rng_en_i ),
- .rng_clk_o ( rng_clk_o )
-); // of u_rng_osc
-
-
-///////////////////////////////////////
-// LFSR for Pseudo Random Numbers
-///////////////////////////////////////
-logic rng_rst_n;
+logic rst_n;
logic[32-1:0] lfsr_val;
-assign rng_rst_n = scan_mode_i ? scan_reset_ni : rst_ni && rng_en_i;
+assign rst_n = scan_mode_i ? rst_ni : rst_ni && rng_en_i;
-always_ff @(posedge rng_clk_o, negedge rng_rst_n ) begin
- if ( !rng_rst_n ) begin
+always_ff @(posedge clk_i, negedge rst_n ) begin
+ if ( !rst_n ) begin
lfsr_val <= 32'h0000_0001;
end else if ( lfsr_val == {32{1'b1}} ) begin // Skip one problematic value
lfsr_val <= {{31{1'b1}}, 1'b0};
@@ -55,57 +39,59 @@
end
end
+logic srate_rng_val;
+logic [12-1:0] srate_cnt, srate_value;
+logic [EntropyStreams-1:0] rng_b;
-///////////////////////////////////////
-// RNG Bus & OK
-///////////////////////////////////////
-logic rng_rdy;
-logic [2-1:0] rng_rdy_cnt;
+assign srate_value = 12'd120;
-always_ff @( posedge rng_clk_o, negedge rng_rst_n ) begin
- if ( !rng_rst_n ) begin
- rng_rdy_cnt <= 2'b00;
- end else if ( !rng_rdy ) begin
- rng_rdy_cnt <= rng_rdy_cnt + 1'b1;
+always_ff @( posedge clk_i, negedge rst_n ) begin
+ if ( !rst_n ) begin
+ srate_cnt <= 12'h000;
+ srate_rng_val <= 1'b0;
+ end else if ( srate_cnt == srate_value ) begin
+ srate_cnt <= 12'h000;
+ srate_rng_val <= 1'b1;
+ end else begin
+ srate_cnt <= srate_cnt + 1'b1;
+ srate_rng_val <= 1'b0;
end
end
-assign rng_rdy = (rng_rdy_cnt == 2'b11);
-
-logic [EntropyStreams-1:0] rng_b;
-
-always_ff @( posedge rng_clk_o, negedge rng_rst_n ) begin
- if ( !rng_rst_n ) begin
+always_ff @( posedge clk_i, negedge rst_n ) begin
+ if ( !rst_n ) begin
rng_b <= {EntropyStreams{1'b0}};
- end else begin
+ end else if ( srate_rng_val ) begin
rng_b <= lfsr_val[EntropyStreams-1:0];
end
end
-// Sync RNG OK to clk_i
-logic rng_rdy_s;
+////////////////////////////////////////
+// Sychronize Bus & Valid to RNG Clock
+////////////////////////////////////////
+logic sync_rng_val;
-always_ff @( posedge clk_i, negedge rst_ni ) begin
- if ( !rst_ni ) begin
- rng_rdy_s <= 1'b0;
- rng_val_o <= 1'b0;
- end else begin
- rng_rdy_s <= rng_rdy;
- rng_val_o <= rng_rdy_s;
- end
-end
+prim_pulse_sync u_rng_val_pulse_sync (
+ // source clock domain
+ .clk_src_i ( clk_i ),
+ .rst_src_ni ( rst_n ),
+ .src_pulse_i ( srate_rng_val ),
+ // destination clock domain
+ .clk_dst_i ( clk_ast_rng_i ),
+ .rst_dst_ni ( rst_ast_rng_ni ),
+ .dst_pulse_o ( sync_rng_val )
+);
-// Sync RNG Bits to clk_i
-logic [EntropyStreams-1:0] rng_b_r;
-
-always_ff @( posedge clk_i, negedge rst_ni ) begin
- if ( !rst_ni ) begin
- rng_b_r <= {EntropyStreams{1'b0}};
+always_ff @( posedge clk_ast_rng_i, negedge rst_ast_rng_ni ) begin
+ if (!rst_ast_rng_ni ) begin
rng_b_o <= {EntropyStreams{1'b0}};
+ rng_val_o <= 1'b0;
+ end else if ( sync_rng_val ) begin
+ rng_b_o <= rng_b[EntropyStreams-1:0];
+ rng_val_o <= 1'b1;
end else begin
- rng_b_r <= rng_b;
- rng_b_o <= rng_b_r;
+ rng_val_o <= 1'b0;
end
end
diff --git a/hw/top_earlgrey/ip/ast/rtl/rng_osc.sv b/hw/top_earlgrey/ip/ast/rtl/rng_osc.sv
deleted file mode 100644
index 074ae6c..0000000
--- a/hw/top_earlgrey/ip/ast/rtl/rng_osc.sv
+++ /dev/null
@@ -1,91 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//############################################################################
-// *Name: rng_osc
-// *Module Description: RNG Clock Oscilator
-//############################################################################
-`ifdef SYNTHESIS
-`ifndef PRIM_DEFAULT_IMPL
-`define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric
-`endif
-`endif
-
-module rng_osc (
- input vcaon_pok_i, // VCAON POK @1.1V
- input rng_en_i, // RNG Source Clock Enable
- output logic rng_clk_o // RNG Clock Output
-);
-
-`ifndef SYNTHESIS
-timeunit 1ns / 1ps;
-import ast_bhv_pkg::* ;
-
-// Behavioral Model
-///////////////////////////////////////
-integer CLK_PERIOD;
-logic clk, en_dly, en_osc, en_osc_re, en_osc_fe;
-
-initial begin
- clk = 1'b0;
- // Seed is set from the vcs run command
- CLK_PERIOD = 10**9/$urandom_range(70000, 50000); // ns (50Khz-70Khz)
- $display( "\nRNG Internal Clock Period: %0dns", CLK_PERIOD);
- en_dly = 1'b0; // to block init X
- #(RNG_EN_RDLY+1) en_dly = 1'b1;
-end
-
-// Enable 5us RC Delay
-logic rng_en_dly;
-assign #(RNG_EN_RDLY) rng_en_dly = rng_en_i;
-assign en_osc_re = vcaon_pok_i && rng_en_i && (rng_en_dly && en_dly);
-
-// Syncronize en_osc to clk FE for glitch free disable
-always_ff @( negedge clk or negedge vcaon_pok_i ) begin
- if ( !vcaon_pok_i ) begin
- en_osc_fe <= 1'b0;
- end else begin
- en_osc_fe <= en_osc_re;
- end
-end
-
-assign en_osc = en_osc_re || en_osc_fe; // EN -> 1 || EN -> 0
-
-always begin
- #(CLK_PERIOD/2) clk = ~clk && en_osc;
-end
-
-assign rng_clk_o = clk;
-`else // of SYNTHESIS
-localparam prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL;
-
-// SYNTHESUS/VERILATOR/LINTER/FPGA
-///////////////////////////////////////
-logic clk, en_osc, en_osc_re, en_osc_fe;
-
-assign en_osc_re = vcaon_pok_i && rng_en_i;
-
-// Syncronize en_osc to clk FE for glitch free disable
-always_ff @( negedge clk or negedge vcaon_pok_i ) begin
- if ( !vcaon_pok_i ) begin
- en_osc_fe <= 1'b0;
- end else begin
- en_osc_fe <= en_osc_re;
- end
-end
-
-assign en_osc = en_osc_re || en_osc_fe; // EN -> 1 || EN -> 0
-
-assign clk = (/*TODO*/ 1'b1) && en_osc;
-assign rng_clk_o = clk;
-
-if (Impl == prim_pkg::ImplXilinx) begin : gen_xilinx
- // FPGA Model (place holder)
- ///////////////////////////////////////
- // TODO
-end else begin : gen_generic
- // TODO
-end
-`endif
-
-endmodule : rng_osc
diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
index 655e364..239f18d 100644
--- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
+++ b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_asic.sv
@@ -980,7 +980,7 @@
.vioa_pok_o ( ast_status.io_pok[0] ),
.viob_pok_o ( ast_status.io_pok[1] ),
// main regulator
- .main_iso_en_i ( base_ast_pwr.pwr_clamp ),
+ .main_env_iso_en_i ( base_ast_pwr.pwr_clamp ),
.main_pd_ni ( base_ast_pwr.main_pd_n ),
// pdm control (flash)/otp
.flash_power_down_h_o ( flash_power_down_h ),
diff --git a/util/topgen/templates/chiplevel.sv.tpl b/util/topgen/templates/chiplevel.sv.tpl
index 7e856ba..acc34e4 100644
--- a/util/topgen/templates/chiplevel.sv.tpl
+++ b/util/topgen/templates/chiplevel.sv.tpl
@@ -845,7 +845,7 @@
.vioa_pok_o ( ast_status.io_pok[0] ),
.viob_pok_o ( ast_status.io_pok[1] ),
// main regulator
- .main_iso_en_i ( base_ast_pwr.pwr_clamp ),
+ .main_env_iso_en_i ( base_ast_pwr.pwr_clamp ),
.main_pd_ni ( base_ast_pwr.main_pd_n ),
// pdm control (flash)/otp
.flash_power_down_h_o ( flash_power_down_h ),
