[alert_handler] Correct a waive diagram and enable condition.
Signed-off-by: Michael Schaffner <msf@opentitan.org>
diff --git a/hw/ip/alert_handler/doc/_index.md b/hw/ip/alert_handler/doc/_index.md
index 56cd326..fffb8f9 100644
--- a/hw/ip/alert_handler/doc/_index.md
+++ b/hw/ip/alert_handler/doc/_index.md
@@ -578,20 +578,20 @@
{ name: 'irq_o[0]', wave: '01.|................' },
{ name: 'CLASSA_STATE', wave: '3..|.3|3.|3..|3..|3.', data: ['Idle', ' Phase0','Phase1','Phase2','Phase3','Terminal'] },
{ name: 'CLASSA_ESC_CNT', wave: '3..|.3|33|333|333|3.', data: ['0','1','1','2','1','2','3','1','2','3','0'] },
- { name: 'esc_tx_o.esc_p[0]', wave: '0..|.1|0............', node: '.....a.b' },
- { name: 'esc_tx_o.esc_n[0]', wave: '1..|.0|1............' },
- { name: 'esc_tx_o.esc_p[1]', wave: '0..|..|1.|0.........', node: '.......c..d' },
- { name: 'esc_tx_o.esc_n[1]', wave: '1..|..|0.|1.........' },
- { name: 'esc_tx_o.esc_p[2]', wave: '0..|.....|1..|0.....', node: '..........e...f' },
- { name: 'esc_tx_o.esc_n[2]', wave: '1..|.....|0..|1.....' },
- { name: 'esc_tx_o.esc_p[3]', wave: '0..|.........|1..|0.', node: '..............g...h' },
- { name: 'esc_tx_o.esc_n[3]', wave: '1..|.........|0..|1.' },
+ { name: 'esc_tx_o.esc_p[0]', wave: '0..|.1|.0...........', node: '.....a..b' },
+ { name: 'esc_tx_o.esc_n[0]', wave: '1..|.0|.1...........' },
+ { name: 'esc_tx_o.esc_p[1]', wave: '0..|..|1.|.0........', node: '.......c...d' },
+ { name: 'esc_tx_o.esc_n[1]', wave: '1..|..|0.|.1........' },
+ { name: 'esc_tx_o.esc_p[2]', wave: '0..|.....|1..|.0....', node: '..........e....f' },
+ { name: 'esc_tx_o.esc_n[2]', wave: '1..|.....|0..|.1....' },
+ { name: 'esc_tx_o.esc_p[3]', wave: '0..|.........|1..|.0', node: '..............g....h' },
+ { name: 'esc_tx_o.esc_n[3]', wave: '1..|.........|0..|.1' },
],
edge: [
- 'a->b 1e3 cycles',
- 'c->d 1e4 cycles',
- 'e->f 1e5 cycles',
- 'g->h 1e6 cycles',
+ 'a->b 1e3 + 1 cycles',
+ 'c->d 1e4 + 1 cycles',
+ 'e->f 1e5 + 1 cycles',
+ 'g->h 1e6 + 1 cycles',
],
head: {
text: 'Alert class gathering and escalation triggers (fully synchronous case)',
@@ -613,7 +613,6 @@
set to 0. Also note that it takes one cycle to activate escalation and enter
phase 0.
-
The next wave shows a case where an interrupt remains unhandled and hence the
interrupt timeout counter triggers escalation.
@@ -626,14 +625,14 @@
{ name: 'irq_o[0]', wave: '01..|.................', node: '.a..|.b' },
{ name: 'CLASSA_ESC_STATE', wave: '33..|.3|3.|3..|3...|3.', data: ['Idle', 'Timeout',' Phase0','Phase1','Phase2','Phase3','Terminal'] },
{ name: 'CLASSA_ESC_CNT', wave: '3333|33|33|333|3333|3.', data: ['0', '1','2','3','1e4','1','1','2','1','2','3','1','2','3','4','0'] },
- { name: 'esc_tx_o.esc_p[0]', wave: '0...|.1|0.............' },
- { name: 'esc_tx_o.esc_n[0]', wave: '1...|.0|1.............' },
- { name: 'esc_tx_o.esc_p[1]', wave: '0...|..|1.|0..........' },
- { name: 'esc_tx_o.esc_n[1]', wave: '1...|..|0.|1..........' },
- { name: 'esc_tx_o.esc_p[2]', wave: '0...|.....|1..|0......' },
- { name: 'esc_tx_o.esc_n[2]', wave: '1...|.....|0..|1......' },
- { name: 'esc_tx_o.esc_p[3]', wave: '0...|.........|1...|0.' },
- { name: 'esc_tx_o.esc_n[3]', wave: '1...|.........|0...|1.' },
+ { name: 'esc_tx_o.esc_p[0]', wave: '0...|.1|.0............' },
+ { name: 'esc_tx_o.esc_n[0]', wave: '1...|.0|.1............' },
+ { name: 'esc_tx_o.esc_p[1]', wave: '0...|..|1.|.0.........' },
+ { name: 'esc_tx_o.esc_n[1]', wave: '1...|..|0.|.1.........' },
+ { name: 'esc_tx_o.esc_p[2]', wave: '0...|.....|1..|.0.....' },
+ { name: 'esc_tx_o.esc_n[2]', wave: '1...|.....|0..|.1.....' },
+ { name: 'esc_tx_o.esc_p[3]', wave: '0...|.........|1...|.0' },
+ { name: 'esc_tx_o.esc_n[3]', wave: '1...|.........|0...|.1' },
],
edge: [
'a->b 1e4 cycles',
@@ -648,6 +647,11 @@
}
{{< /wavejson >}}
+It should be noted here that the differential escalation signaling protocol
+distinguishes 'true' escalation conditions from mere pings by encoding them as
+pulses that are N + 1 cycles long. This is reflected in the two wave diagrams
+above. Refer to the subsequent section on escalation signaling for more details.
+
### Escalation Signaling
For each of the four escalation severities, the alert handler instantiates a
@@ -842,6 +846,8 @@
- For each escalation signal (0..3):
- Determine whether to enable the escalation signal, and set the
{{< regref "CLASSA_CTRL.E0_EN" >}} bit accordingly (default is enabled).
+ Note that setting all of the `E*_EN` bits to 0 within a class has the same
+ effect of disabling the entire class by setting {{< regref "CLASSA_CTRL.EN" >}} to zero.
- Determine the phase -> escalation mapping of this class and
program it via the {{< regref "CLASSA_CTRL.E0_MAP" >}} values if it needs to be
changed from the default mapping (0->0, 1->1, 2->2, 3->3).
diff --git a/hw/ip/alert_handler/rtl/alert_handler_reg_wrap.sv b/hw/ip/alert_handler/rtl/alert_handler_reg_wrap.sv
index 1a245c0..e795ee4 100644
--- a/hw/ip/alert_handler/rtl/alert_handler_reg_wrap.sv
+++ b/hw/ip/alert_handler/rtl/alert_handler_reg_wrap.sv
@@ -170,10 +170,28 @@
assign reg2hw_wrap.ping_timeout_cyc = reg2hw.ping_timeout_cyc.q;
// class enable
- assign reg2hw_wrap.class_en = { reg2hw.classd_ctrl.en,
- reg2hw.classc_ctrl.en,
- reg2hw.classb_ctrl.en,
- reg2hw.classa_ctrl.en };
+ // we require that at least one of the enable signals is
+ // set for a class to be enabled
+ assign reg2hw_wrap.class_en = { reg2hw.classd_ctrl.en & ( reg2hw.classd_ctrl.en_e3 |
+ reg2hw.classd_ctrl.en_e2 |
+ reg2hw.classd_ctrl.en_e1 |
+ reg2hw.classd_ctrl.en_e0 ),
+ //
+ reg2hw.classc_ctrl.en & ( reg2hw.classc_ctrl.en_e3 |
+ reg2hw.classc_ctrl.en_e2 |
+ reg2hw.classc_ctrl.en_e1 |
+ reg2hw.classc_ctrl.en_e0 ),
+ //
+ reg2hw.classb_ctrl.en & ( reg2hw.classb_ctrl.en_e3 |
+ reg2hw.classb_ctrl.en_e2 |
+ reg2hw.classb_ctrl.en_e1 |
+ reg2hw.classb_ctrl.en_e0 ),
+ //
+ reg2hw.classa_ctrl.en & ( reg2hw.classa_ctrl.en_e3 |
+ reg2hw.classa_ctrl.en_e2 |
+ reg2hw.classa_ctrl.en_e1 |
+ reg2hw.classa_ctrl.en_e0 ) };
+
// autolock enable
assign class_autolock_en = { reg2hw.classd_ctrl.lock,
