[pwm, rtl] SV formatter trial
- Try to run the sv formatter on PWM RTL codes
- Revert back the sv formatter changes that don't look good
- Parameterize the counter data width
Signed-off-by: Muqing Liu <muqing.liu@wdc.com>
diff --git a/hw/ip/pwm/rtl/pwm.sv b/hw/ip/pwm/rtl/pwm.sv
index 21f963a..4cfb051 100644
--- a/hw/ip/pwm/rtl/pwm.sv
+++ b/hw/ip/pwm/rtl/pwm.sv
@@ -7,7 +7,9 @@
module pwm
import pwm_reg_pkg::*;
#(
- parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}
+ parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}},
+ parameter int PhaseCntDw = 16,
+ parameter int BeatCntDw = 27
) (
input clk_i,
input rst_ni,
@@ -67,7 +69,11 @@
assign cio_pwm_en_o = {NOutputs{1'b1}};
- pwm_core #(.NOutputs(NOutputs)) u_pwm_core (
+ pwm_core #(
+ .NOutputs(NOutputs),
+ .PhaseCntDw(PhaseCntDw),
+ .BeatCntDw(BeatCntDw)
+ ) u_pwm_core (
.clk_core_i,
.rst_core_ni,
.reg2hw,
diff --git a/hw/ip/pwm/rtl/pwm_chan.sv b/hw/ip/pwm/rtl/pwm_chan.sv
index 122bc18..4c99054 100644
--- a/hw/ip/pwm/rtl/pwm_chan.sv
+++ b/hw/ip/pwm/rtl/pwm_chan.sv
@@ -2,7 +2,9 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-module pwm_chan (
+module pwm_chan #(
+ parameter int CntDw = 16
+) (
input clk_i,
input rst_ni,
@@ -31,23 +33,23 @@
logic pwm_int;
// Standard blink mode
- logic [15:0] blink_ctr_q;
- logic [15:0] blink_ctr_d;
- logic [15:0] duty_cycle_blink;
+ logic [CntDw-1:0] blink_ctr_q;
+ logic [CntDw-1:0] blink_ctr_d;
+ logic [CntDw-1:0] duty_cycle_blink;
logic unused_sum;
- logic [15:0] blink_sum;
- assign {unused_sum, blink_sum} = blink_param_x_i + blink_param_y_i + 16'h1;
- assign blink_ctr_d = (!(blink_en_i && !htbt_en_i) || clr_blink_cntr_i) ? 16'h0 :
- ((blink_ctr_q == blink_sum[15:0]) && cycle_end_i)
- ? 16'h0 : (cycle_end_i) ? blink_ctr_q + 16'h1 : blink_ctr_q;
+ logic [CntDw-1:0] blink_sum;
+ assign {unused_sum, blink_sum} = blink_param_x_i + blink_param_y_i + 1'b1;
+ assign blink_ctr_d = (!(blink_en_i && !htbt_en_i) || clr_blink_cntr_i) ? '0 :
+ ((blink_ctr_q == blink_sum[CntDw-1:0]) && cycle_end_i)
+ ? '0 : (cycle_end_i) ? blink_ctr_q + 1'b1 : blink_ctr_q;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
- blink_ctr_q <= 16'h0;
+ blink_ctr_q <= '0;
end else begin
if (clr_blink_cntr_i) begin
- blink_ctr_q <= 16'h0;
+ blink_ctr_q <= '0;
end else begin
blink_ctr_q <= (blink_en_i && !htbt_en_i) ? blink_ctr_d : blink_ctr_q;
end
@@ -58,23 +60,23 @@
duty_cycle_b_i : duty_cycle_a_i;
// Heartbeat mode
- logic [15:0] htbt_ctr_q;
- logic [15:0] htbt_ctr_d;
- logic [15:0] duty_cycle_htbt;
- logic [15:0] dc_htbt_d;
- logic [15:0] dc_htbt_q;
+ logic [CntDw-1:0] htbt_ctr_q;
+ logic [CntDw-1:0] htbt_ctr_d;
+ logic [CntDw-1:0] duty_cycle_htbt;
+ logic [CntDw-1:0] dc_htbt_d;
+ logic [CntDw-1:0] dc_htbt_q;
logic dc_htbt_end;
- assign htbt_ctr_d = (!(blink_en_i && htbt_en_i) || clr_blink_cntr_i) ? 16'h0 :
- ((htbt_ctr_q == blink_param_x_i) && cycle_end_i) ? 16'h0 :
- (cycle_end_i) ? htbt_ctr_q + 16'h1 : htbt_ctr_q;
+ assign htbt_ctr_d = (!(blink_en_i && htbt_en_i) || clr_blink_cntr_i) ? '0 :
+ ((htbt_ctr_q == blink_param_x_i) && cycle_end_i) ? '0 :
+ (cycle_end_i) ? (htbt_ctr_q + 1'b1) : htbt_ctr_q;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
- htbt_ctr_q <= 16'h0;
+ htbt_ctr_q <= '0;
end else begin
if (clr_blink_cntr_i) begin
- htbt_ctr_q <= 16'h0;
+ htbt_ctr_q <= '0;
end else begin
htbt_ctr_q <= (blink_en_i && htbt_en_i) ? htbt_ctr_d : htbt_ctr_q;
end
@@ -107,11 +109,12 @@
logic pattern_repeat;
assign pattern_repeat = (pos_htbt & htbt_direction) | (neg_htbt & ~htbt_direction) |
(~pos_htbt & ~neg_htbt);
- assign {dc_wrap, dc_htbt_d} = !(htbt_ctr_q == blink_param_x_i) ? {1'b0, dc_htbt_q} :
+ localparam int CntExtDw = CntDw + 1;
+ assign {dc_wrap, dc_htbt_d} = !(htbt_ctr_q == blink_param_x_i) ? (CntExtDw)'(dc_htbt_q) :
((dc_htbt_q == duty_cycle_a_i) && pattern_repeat) ?
- {1'b0, duty_cycle_a_i} : (htbt_direction) ?
- {1'b0, dc_htbt_q} - {1'b0, blink_param_y_i} - 1'b1 :
- {1'b0, dc_htbt_q} + {1'b0, blink_param_y_i} + 1'b1;
+ (CntExtDw)'(duty_cycle_a_i) : (htbt_direction) ?
+ (CntExtDw)'(dc_htbt_q) - (CntExtDw)'(blink_param_y_i) - 1'b1 :
+ (CntExtDw)'(dc_htbt_q) + (CntExtDw)'(blink_param_y_i) + 1'b1;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
dc_htbt_q <= '0;
diff --git a/hw/ip/pwm/rtl/pwm_core.sv b/hw/ip/pwm/rtl/pwm_core.sv
index fd2b9df..11f9586 100644
--- a/hw/ip/pwm/rtl/pwm_core.sv
+++ b/hw/ip/pwm/rtl/pwm_core.sv
@@ -5,7 +5,9 @@
// Description: PWM Core Module
module pwm_core #(
- parameter int NOutputs = 6
+ parameter int NOutputs = 6,
+ parameter int PhaseCntDw = 16,
+ parameter int BeatCntDw = 27
) (
input clk_core_i,
input rst_core_ni,
@@ -42,24 +44,24 @@
// Beat and phase counters (in core clock domain)
//
- logic cntr_en;
- logic [26:0] clk_div;
- logic [3:0] dc_resn;
+ logic cntr_en;
+ logic [BeatCntDw-1:0] clk_div;
+ logic [3:0] dc_resn;
- logic [26:0] beat_ctr_q;
- logic [26:0] beat_ctr_d;
- logic beat_ctr_en;
- logic beat_end;
+ logic [BeatCntDw-1:0] beat_ctr_q;
+ logic [BeatCntDw-1:0] beat_ctr_d;
+ logic beat_ctr_en;
+ logic beat_end;
- logic [15:0] phase_ctr_q;
- logic [15:0] phase_ctr_d;
- logic [15:0] phase_ctr_incr;
- logic [15:0] phase_ctr_next;
- logic phase_ctr_overflow;
- logic phase_ctr_en;
- logic cycle_end;
+ logic [PhaseCntDw-1:0] phase_ctr_q;
+ logic [PhaseCntDw-1:0] phase_ctr_d;
+ logic [PhaseCntDw-1:0] phase_ctr_incr;
+ logic [PhaseCntDw-1:0] phase_ctr_next;
+ logic phase_ctr_overflow;
+ logic phase_ctr_en;
+ logic cycle_end;
- logic unused_regen;
+ logic unused_regen;
// TODO: implement register locking
assign unused_regen = reg2hw.regen.q;
@@ -68,14 +70,14 @@
assign dc_resn = reg2hw.cfg.dc_resn.q;
assign clk_div = reg2hw.cfg.clk_div.q;
- assign beat_ctr_d = (clr_phase_cntr) ? 27'h0 :
- (beat_ctr_q == clk_div) ? 27'h0 : (beat_ctr_q + 27'h1);
+ assign beat_ctr_d = (clr_phase_cntr) ? '0 :
+ (beat_ctr_q == clk_div) ? '0 : (beat_ctr_q + 1'b1);
assign beat_ctr_en = clr_phase_cntr | cntr_en;
assign beat_end = (beat_ctr_q == clk_div);
always_ff @(posedge clk_core_i or negedge rst_core_ni) begin
if (!rst_core_ni) begin
- beat_ctr_q <= 27'h0;
+ beat_ctr_q <= '0;
end else begin
beat_ctr_q <= beat_ctr_en ? beat_ctr_d : beat_ctr_q;
end
@@ -84,14 +86,14 @@
// Only update phase_ctr at the end of each beat
// Exception: allow reset to zero whenever not enabled
assign phase_ctr_en = beat_end & (clr_phase_cntr | cntr_en);
- assign phase_ctr_incr = 16'h1 << (15 -dc_resn);
+ assign phase_ctr_incr = (PhaseCntDw)'('h1) << (4'd15 - dc_resn);
assign {phase_ctr_overflow, phase_ctr_next} = phase_ctr_q + phase_ctr_incr;
- assign phase_ctr_d = clr_phase_cntr ? 16'h0 : phase_ctr_next;
+ assign phase_ctr_d = clr_phase_cntr ? '0 : phase_ctr_next;
assign cycle_end = beat_end & phase_ctr_overflow;
always_ff @(posedge clk_core_i or negedge rst_core_ni) begin
if (!rst_core_ni) begin
- phase_ctr_q <= 16'h0;
+ phase_ctr_q <= '0;
end else begin
phase_ctr_q <= phase_ctr_en ? phase_ctr_d : phase_ctr_q;
end
@@ -103,7 +105,7 @@
// PWM Channel Instantiation
//
- pwm_chan u_chan (
+ pwm_chan #(.CntDw(PhaseCntDw)) u_chan (
.clk_i (clk_core_i),
.rst_ni (rst_core_ni),
.pwm_en_i (reg2hw.pwm_en[ii].q),
