[pattgen] Wire up integrity alert
Signed-off-by: Michael Schaffner <msf@opentitan.org>
diff --git a/hw/ip/pattgen/data/pattgen.hjson b/hw/ip/pattgen/data/pattgen.hjson
index 53bd2fa..e87236f 100644
--- a/hw/ip/pattgen/data/pattgen.hjson
+++ b/hw/ip/pattgen/data/pattgen.hjson
@@ -24,6 +24,13 @@
desc: "raise if pattern generation on Channel 1 is complete"
}
],
+ alert_list: [
+ { name: "fatal_fault",
+ desc: '''
+ This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected inside the PATTGEN unit.
+ '''
+ }
+ ],
param_list: [
{ name: "NumRegsData",
type: "int",
diff --git a/hw/ip/pattgen/dv/env/pattgen_env_cfg.sv b/hw/ip/pattgen/dv/env/pattgen_env_cfg.sv
index 26928a9..f38dffe 100644
--- a/hw/ip/pattgen/dv/env/pattgen_env_cfg.sv
+++ b/hw/ip/pattgen/dv/env/pattgen_env_cfg.sv
@@ -19,6 +19,7 @@
`uvm_object_new
virtual function void initialize(bit [TL_AW-1:0] csr_base_addr = '1);
+ list_of_alerts = pattgen_env_pkg::LIST_OF_ALERTS;
super.initialize(csr_base_addr);
// create pattgen_agent_cfg
diff --git a/hw/ip/pattgen/dv/env/pattgen_env_pkg.sv b/hw/ip/pattgen/dv/env/pattgen_env_pkg.sv
index f7836d6..4f5ea42 100644
--- a/hw/ip/pattgen/dv/env/pattgen_env_pkg.sv
+++ b/hw/ip/pattgen/dv/env/pattgen_env_pkg.sv
@@ -38,6 +38,10 @@
Disable = 1'b0
} channel_status_e;
+ // alerts
+ parameter uint NUM_ALERTS = 1;
+ parameter string LIST_OF_ALERTS[] = {"fatal_fault"};
+
// package sources
`include "pattgen_seq_cfg.sv"
`include "pattgen_channel_cfg.sv"
diff --git a/hw/ip/pattgen/dv/tb.sv b/hw/ip/pattgen/dv/tb.sv
index 1af62d0..49c6a7f 100644
--- a/hw/ip/pattgen/dv/tb.sv
+++ b/hw/ip/pattgen/dv/tb.sv
@@ -30,6 +30,8 @@
pattgen_if #(NUM_PATTGEN_CHANNELS) pattgen_if();
tl_if tl_if(.clk(clk), .rst_n(rst_n));
+ `DV_ALERT_IF_CONNECT
+
// dut
pattgen dut (
.clk_i (clk ),
@@ -38,6 +40,9 @@
.tl_i (tl_if.h2d ),
.tl_o (tl_if.d2h ),
+ .alert_rx_i (alert_rx ),
+ .alert_tx_o (alert_tx ),
+
.cio_pda0_tx_o (pda_tx_o[0] ),
.cio_pcl0_tx_o (pcl_tx_o[0] ),
.cio_pda1_tx_o (pda_tx_o[1] ),
diff --git a/hw/ip/pattgen/rtl/pattgen.sv b/hw/ip/pattgen/rtl/pattgen.sv
index cbd0917..2c6ed26 100644
--- a/hw/ip/pattgen/rtl/pattgen.sv
+++ b/hw/ip/pattgen/rtl/pattgen.sv
@@ -6,13 +6,18 @@
module pattgen
import pattgen_reg_pkg::*;
-(
+#(
+ parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}}
+) (
input clk_i,
input rst_ni,
input tlul_pkg::tl_h2d_t tl_i,
output tlul_pkg::tl_d2h_t tl_o,
+ input prim_alert_pkg::alert_rx_t [NumAlerts-1:0] alert_rx_i,
+ output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
+
output logic cio_pda0_tx_o,
output logic cio_pcl0_tx_o,
output logic cio_pda1_tx_o,
@@ -26,6 +31,7 @@
output logic intr_done_ch1_o
);
+ logic [NumAlerts-1:0] alert_test, alerts;
pattgen_reg2hw_t reg2hw;
pattgen_hw2reg_t hw2reg;
@@ -36,10 +42,31 @@
.tl_o,
.reg2hw,
.hw2reg,
- .intg_err_o(),
+ .intg_err_o(alerts[0]),
.devmode_i(1'b1)
);
+ assign alert_test = {
+ reg2hw.alert_test.q &
+ reg2hw.alert_test.qe
+ };
+
+ for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
+ prim_alert_sender #(
+ .AsyncOn(AlertAsyncOn[i]),
+ .IsFatal(1'b1)
+ ) u_prim_alert_sender (
+ .clk_i,
+ .rst_ni,
+ .alert_test_i ( alert_test[i] ),
+ .alert_req_i ( alerts[0] ),
+ .alert_ack_o ( ),
+ .alert_state_o ( ),
+ .alert_rx_i ( alert_rx_i[i] ),
+ .alert_tx_o ( alert_tx_o[i] )
+ );
+ end
+
assign cio_pda0_tx_en_o = 1'b1;
assign cio_pcl0_tx_en_o = 1'b1;
assign cio_pda1_tx_en_o = 1'b1;
@@ -62,6 +89,7 @@
`ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid)
`ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready)
+ `ASSERT_KNOWN(AlertsKnown_A, alert_tx_o)
`ASSERT_KNOWN(Pcl0TxKnownO_A, cio_pcl0_tx_o)
`ASSERT_KNOWN(Pda0TxKnownO_A, cio_pda0_tx_o)
`ASSERT_KNOWN(Pcl1TxKnownO_A, cio_pcl1_tx_o)
diff --git a/hw/ip/pattgen/rtl/pattgen_reg_pkg.sv b/hw/ip/pattgen/rtl/pattgen_reg_pkg.sv
index f2da20a..5a3f582 100644
--- a/hw/ip/pattgen/rtl/pattgen_reg_pkg.sv
+++ b/hw/ip/pattgen/rtl/pattgen_reg_pkg.sv
@@ -8,6 +8,7 @@
// Param list
parameter int NumRegsData = 2;
+ parameter int NumAlerts = 1;
// Address widths within the block
parameter int BlockAw = 6;
@@ -46,6 +47,11 @@
} pattgen_reg2hw_intr_test_reg_t;
typedef struct packed {
+ logic q;
+ logic qe;
+ } pattgen_reg2hw_alert_test_reg_t;
+
+ typedef struct packed {
struct packed {
logic q;
} enable_ch0;
@@ -104,9 +110,10 @@
// Register -> HW type
typedef struct packed {
- pattgen_reg2hw_intr_state_reg_t intr_state; // [235:234]
- pattgen_reg2hw_intr_enable_reg_t intr_enable; // [233:232]
- pattgen_reg2hw_intr_test_reg_t intr_test; // [231:228]
+ pattgen_reg2hw_intr_state_reg_t intr_state; // [237:236]
+ pattgen_reg2hw_intr_enable_reg_t intr_enable; // [235:234]
+ pattgen_reg2hw_intr_test_reg_t intr_test; // [233:230]
+ pattgen_reg2hw_alert_test_reg_t alert_test; // [229:228]
pattgen_reg2hw_ctrl_reg_t ctrl; // [227:224]
pattgen_reg2hw_prediv_ch0_reg_t prediv_ch0; // [223:192]
pattgen_reg2hw_prediv_ch1_reg_t prediv_ch1; // [191:160]
@@ -124,25 +131,29 @@
parameter logic [BlockAw-1:0] PATTGEN_INTR_STATE_OFFSET = 6'h 0;
parameter logic [BlockAw-1:0] PATTGEN_INTR_ENABLE_OFFSET = 6'h 4;
parameter logic [BlockAw-1:0] PATTGEN_INTR_TEST_OFFSET = 6'h 8;
- parameter logic [BlockAw-1:0] PATTGEN_CTRL_OFFSET = 6'h c;
- parameter logic [BlockAw-1:0] PATTGEN_PREDIV_CH0_OFFSET = 6'h 10;
- parameter logic [BlockAw-1:0] PATTGEN_PREDIV_CH1_OFFSET = 6'h 14;
- parameter logic [BlockAw-1:0] PATTGEN_DATA_CH0_0_OFFSET = 6'h 18;
- parameter logic [BlockAw-1:0] PATTGEN_DATA_CH0_1_OFFSET = 6'h 1c;
- parameter logic [BlockAw-1:0] PATTGEN_DATA_CH1_0_OFFSET = 6'h 20;
- parameter logic [BlockAw-1:0] PATTGEN_DATA_CH1_1_OFFSET = 6'h 24;
- parameter logic [BlockAw-1:0] PATTGEN_SIZE_OFFSET = 6'h 28;
+ parameter logic [BlockAw-1:0] PATTGEN_ALERT_TEST_OFFSET = 6'h c;
+ parameter logic [BlockAw-1:0] PATTGEN_CTRL_OFFSET = 6'h 10;
+ parameter logic [BlockAw-1:0] PATTGEN_PREDIV_CH0_OFFSET = 6'h 14;
+ parameter logic [BlockAw-1:0] PATTGEN_PREDIV_CH1_OFFSET = 6'h 18;
+ parameter logic [BlockAw-1:0] PATTGEN_DATA_CH0_0_OFFSET = 6'h 1c;
+ parameter logic [BlockAw-1:0] PATTGEN_DATA_CH0_1_OFFSET = 6'h 20;
+ parameter logic [BlockAw-1:0] PATTGEN_DATA_CH1_0_OFFSET = 6'h 24;
+ parameter logic [BlockAw-1:0] PATTGEN_DATA_CH1_1_OFFSET = 6'h 28;
+ parameter logic [BlockAw-1:0] PATTGEN_SIZE_OFFSET = 6'h 2c;
// Reset values for hwext registers and their fields
parameter logic [1:0] PATTGEN_INTR_TEST_RESVAL = 2'h 0;
parameter logic [0:0] PATTGEN_INTR_TEST_DONE_CH0_RESVAL = 1'h 0;
parameter logic [0:0] PATTGEN_INTR_TEST_DONE_CH1_RESVAL = 1'h 0;
+ parameter logic [0:0] PATTGEN_ALERT_TEST_RESVAL = 1'h 0;
+ parameter logic [0:0] PATTGEN_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0;
// Register index
typedef enum int {
PATTGEN_INTR_STATE,
PATTGEN_INTR_ENABLE,
PATTGEN_INTR_TEST,
+ PATTGEN_ALERT_TEST,
PATTGEN_CTRL,
PATTGEN_PREDIV_CH0,
PATTGEN_PREDIV_CH1,
@@ -154,18 +165,19 @@
} pattgen_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] PATTGEN_PERMIT [11] = '{
+ parameter logic [3:0] PATTGEN_PERMIT [12] = '{
4'b 0001, // index[ 0] PATTGEN_INTR_STATE
4'b 0001, // index[ 1] PATTGEN_INTR_ENABLE
4'b 0001, // index[ 2] PATTGEN_INTR_TEST
- 4'b 0001, // index[ 3] PATTGEN_CTRL
- 4'b 1111, // index[ 4] PATTGEN_PREDIV_CH0
- 4'b 1111, // index[ 5] PATTGEN_PREDIV_CH1
- 4'b 1111, // index[ 6] PATTGEN_DATA_CH0_0
- 4'b 1111, // index[ 7] PATTGEN_DATA_CH0_1
- 4'b 1111, // index[ 8] PATTGEN_DATA_CH1_0
- 4'b 1111, // index[ 9] PATTGEN_DATA_CH1_1
- 4'b 1111 // index[10] PATTGEN_SIZE
+ 4'b 0001, // index[ 3] PATTGEN_ALERT_TEST
+ 4'b 0001, // index[ 4] PATTGEN_CTRL
+ 4'b 1111, // index[ 5] PATTGEN_PREDIV_CH0
+ 4'b 1111, // index[ 6] PATTGEN_PREDIV_CH1
+ 4'b 1111, // index[ 7] PATTGEN_DATA_CH0_0
+ 4'b 1111, // index[ 8] PATTGEN_DATA_CH0_1
+ 4'b 1111, // index[ 9] PATTGEN_DATA_CH1_0
+ 4'b 1111, // index[10] PATTGEN_DATA_CH1_1
+ 4'b 1111 // index[11] PATTGEN_SIZE
};
endpackage
diff --git a/hw/ip/pattgen/rtl/pattgen_reg_top.sv b/hw/ip/pattgen/rtl/pattgen_reg_top.sv
index 2b449fe..aca48a6 100644
--- a/hw/ip/pattgen/rtl/pattgen_reg_top.sv
+++ b/hw/ip/pattgen/rtl/pattgen_reg_top.sv
@@ -120,6 +120,8 @@
logic intr_test_done_ch0_we;
logic intr_test_done_ch1_wd;
logic intr_test_done_ch1_we;
+ logic alert_test_wd;
+ logic alert_test_we;
logic ctrl_enable_ch0_qs;
logic ctrl_enable_ch0_wd;
logic ctrl_enable_ch0_we;
@@ -304,6 +306,22 @@
);
+ // R[alert_test]: V(True)
+
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_alert_test (
+ .re (1'b0),
+ .we (alert_test_we),
+ .wd (alert_test_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.alert_test.qe),
+ .q (reg2hw.alert_test.q),
+ .qs ()
+ );
+
+
// R[ctrl]: V(False)
// F[enable_ch0]: 0:0
@@ -684,20 +702,21 @@
- logic [10:0] addr_hit;
+ logic [11:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == PATTGEN_INTR_STATE_OFFSET);
addr_hit[ 1] = (reg_addr == PATTGEN_INTR_ENABLE_OFFSET);
addr_hit[ 2] = (reg_addr == PATTGEN_INTR_TEST_OFFSET);
- addr_hit[ 3] = (reg_addr == PATTGEN_CTRL_OFFSET);
- addr_hit[ 4] = (reg_addr == PATTGEN_PREDIV_CH0_OFFSET);
- addr_hit[ 5] = (reg_addr == PATTGEN_PREDIV_CH1_OFFSET);
- addr_hit[ 6] = (reg_addr == PATTGEN_DATA_CH0_0_OFFSET);
- addr_hit[ 7] = (reg_addr == PATTGEN_DATA_CH0_1_OFFSET);
- addr_hit[ 8] = (reg_addr == PATTGEN_DATA_CH1_0_OFFSET);
- addr_hit[ 9] = (reg_addr == PATTGEN_DATA_CH1_1_OFFSET);
- addr_hit[10] = (reg_addr == PATTGEN_SIZE_OFFSET);
+ addr_hit[ 3] = (reg_addr == PATTGEN_ALERT_TEST_OFFSET);
+ addr_hit[ 4] = (reg_addr == PATTGEN_CTRL_OFFSET);
+ addr_hit[ 5] = (reg_addr == PATTGEN_PREDIV_CH0_OFFSET);
+ addr_hit[ 6] = (reg_addr == PATTGEN_PREDIV_CH1_OFFSET);
+ addr_hit[ 7] = (reg_addr == PATTGEN_DATA_CH0_0_OFFSET);
+ addr_hit[ 8] = (reg_addr == PATTGEN_DATA_CH0_1_OFFSET);
+ addr_hit[ 9] = (reg_addr == PATTGEN_DATA_CH1_0_OFFSET);
+ addr_hit[10] = (reg_addr == PATTGEN_DATA_CH1_1_OFFSET);
+ addr_hit[11] = (reg_addr == PATTGEN_SIZE_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -715,7 +734,8 @@
(addr_hit[ 7] & (|(PATTGEN_PERMIT[ 7] & ~reg_be))) |
(addr_hit[ 8] & (|(PATTGEN_PERMIT[ 8] & ~reg_be))) |
(addr_hit[ 9] & (|(PATTGEN_PERMIT[ 9] & ~reg_be))) |
- (addr_hit[10] & (|(PATTGEN_PERMIT[10] & ~reg_be)))));
+ (addr_hit[10] & (|(PATTGEN_PERMIT[10] & ~reg_be))) |
+ (addr_hit[11] & (|(PATTGEN_PERMIT[11] & ~reg_be)))));
end
assign intr_state_done_ch0_we = addr_hit[0] & reg_we & !reg_error;
@@ -736,46 +756,49 @@
assign intr_test_done_ch1_we = addr_hit[2] & reg_we & !reg_error;
assign intr_test_done_ch1_wd = reg_wdata[1];
- assign ctrl_enable_ch0_we = addr_hit[3] & reg_we & !reg_error;
+ assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
+ assign alert_test_wd = reg_wdata[0];
+
+ assign ctrl_enable_ch0_we = addr_hit[4] & reg_we & !reg_error;
assign ctrl_enable_ch0_wd = reg_wdata[0];
- assign ctrl_enable_ch1_we = addr_hit[3] & reg_we & !reg_error;
+ assign ctrl_enable_ch1_we = addr_hit[4] & reg_we & !reg_error;
assign ctrl_enable_ch1_wd = reg_wdata[1];
- assign ctrl_polarity_ch0_we = addr_hit[3] & reg_we & !reg_error;
+ assign ctrl_polarity_ch0_we = addr_hit[4] & reg_we & !reg_error;
assign ctrl_polarity_ch0_wd = reg_wdata[2];
- assign ctrl_polarity_ch1_we = addr_hit[3] & reg_we & !reg_error;
+ assign ctrl_polarity_ch1_we = addr_hit[4] & reg_we & !reg_error;
assign ctrl_polarity_ch1_wd = reg_wdata[3];
- assign prediv_ch0_we = addr_hit[4] & reg_we & !reg_error;
+ assign prediv_ch0_we = addr_hit[5] & reg_we & !reg_error;
assign prediv_ch0_wd = reg_wdata[31:0];
- assign prediv_ch1_we = addr_hit[5] & reg_we & !reg_error;
+ assign prediv_ch1_we = addr_hit[6] & reg_we & !reg_error;
assign prediv_ch1_wd = reg_wdata[31:0];
- assign data_ch0_0_we = addr_hit[6] & reg_we & !reg_error;
+ assign data_ch0_0_we = addr_hit[7] & reg_we & !reg_error;
assign data_ch0_0_wd = reg_wdata[31:0];
- assign data_ch0_1_we = addr_hit[7] & reg_we & !reg_error;
+ assign data_ch0_1_we = addr_hit[8] & reg_we & !reg_error;
assign data_ch0_1_wd = reg_wdata[31:0];
- assign data_ch1_0_we = addr_hit[8] & reg_we & !reg_error;
+ assign data_ch1_0_we = addr_hit[9] & reg_we & !reg_error;
assign data_ch1_0_wd = reg_wdata[31:0];
- assign data_ch1_1_we = addr_hit[9] & reg_we & !reg_error;
+ assign data_ch1_1_we = addr_hit[10] & reg_we & !reg_error;
assign data_ch1_1_wd = reg_wdata[31:0];
- assign size_len_ch0_we = addr_hit[10] & reg_we & !reg_error;
+ assign size_len_ch0_we = addr_hit[11] & reg_we & !reg_error;
assign size_len_ch0_wd = reg_wdata[5:0];
- assign size_reps_ch0_we = addr_hit[10] & reg_we & !reg_error;
+ assign size_reps_ch0_we = addr_hit[11] & reg_we & !reg_error;
assign size_reps_ch0_wd = reg_wdata[15:6];
- assign size_len_ch1_we = addr_hit[10] & reg_we & !reg_error;
+ assign size_len_ch1_we = addr_hit[11] & reg_we & !reg_error;
assign size_len_ch1_wd = reg_wdata[21:16];
- assign size_reps_ch1_we = addr_hit[10] & reg_we & !reg_error;
+ assign size_reps_ch1_we = addr_hit[11] & reg_we & !reg_error;
assign size_reps_ch1_wd = reg_wdata[31:22];
// Read data return
@@ -798,37 +821,41 @@
end
addr_hit[3]: begin
+ reg_rdata_next[0] = '0;
+ end
+
+ addr_hit[4]: begin
reg_rdata_next[0] = ctrl_enable_ch0_qs;
reg_rdata_next[1] = ctrl_enable_ch1_qs;
reg_rdata_next[2] = ctrl_polarity_ch0_qs;
reg_rdata_next[3] = ctrl_polarity_ch1_qs;
end
- addr_hit[4]: begin
+ addr_hit[5]: begin
reg_rdata_next[31:0] = prediv_ch0_qs;
end
- addr_hit[5]: begin
+ addr_hit[6]: begin
reg_rdata_next[31:0] = prediv_ch1_qs;
end
- addr_hit[6]: begin
+ addr_hit[7]: begin
reg_rdata_next[31:0] = data_ch0_0_qs;
end
- addr_hit[7]: begin
+ addr_hit[8]: begin
reg_rdata_next[31:0] = data_ch0_1_qs;
end
- addr_hit[8]: begin
+ addr_hit[9]: begin
reg_rdata_next[31:0] = data_ch1_0_qs;
end
- addr_hit[9]: begin
+ addr_hit[10]: begin
reg_rdata_next[31:0] = data_ch1_1_qs;
end
- addr_hit[10]: begin
+ addr_hit[11]: begin
reg_rdata_next[5:0] = size_len_ch0_qs;
reg_rdata_next[15:6] = size_reps_ch0_qs;
reg_rdata_next[21:16] = size_len_ch1_qs;
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 6313138..596bc54 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -11524,6 +11524,7 @@
[
spi_host0
spi_host1
+ pattgen
otp_ctrl
lc_ctrl
sensor_ctrl_aon
@@ -11558,6 +11559,13 @@
module_name: spi_host1
}
{
+ name: pattgen_fatal_fault
+ width: 1
+ type: alert
+ async: "0"
+ module_name: pattgen
+ }
+ {
name: otp_ctrl_fatal_macro_error
width: 1
type: alert
diff --git a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
index 631c2a1..bbaa32d 100644
--- a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
+++ b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
@@ -6,41 +6,42 @@
assign alert_if[0].alert_tx = `CHIP_HIER.u_spi_host0.alert_tx_o[0];
assign alert_if[1].alert_tx = `CHIP_HIER.u_spi_host1.alert_tx_o[0];
-assign alert_if[2].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[0];
-assign alert_if[3].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[1];
-assign alert_if[4].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[0];
-assign alert_if[5].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[1];
-assign alert_if[6].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[2];
-assign alert_if[7].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[0];
-assign alert_if[8].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[1];
-assign alert_if[9].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[2];
-assign alert_if[10].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[3];
-assign alert_if[11].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[4];
-assign alert_if[12].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[5];
-assign alert_if[13].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[6];
-assign alert_if[14].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[7];
-assign alert_if[15].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[8];
-assign alert_if[16].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[9];
-assign alert_if[17].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[10];
-assign alert_if[18].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0];
-assign alert_if[19].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[1];
-assign alert_if[20].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0];
-assign alert_if[21].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1];
-assign alert_if[22].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2];
-assign alert_if[23].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[3];
-assign alert_if[24].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0];
-assign alert_if[25].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1];
-assign alert_if[26].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0];
-assign alert_if[27].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0];
-assign alert_if[28].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0];
-assign alert_if[29].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1];
-assign alert_if[30].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0];
-assign alert_if[31].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0];
-assign alert_if[32].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1];
-assign alert_if[33].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0];
-assign alert_if[34].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0];
-assign alert_if[35].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
-assign alert_if[36].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[1];
-assign alert_if[37].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0];
-assign alert_if[38].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1];
-assign alert_if[39].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0];
+assign alert_if[2].alert_tx = `CHIP_HIER.u_pattgen.alert_tx_o[0];
+assign alert_if[3].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[0];
+assign alert_if[4].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[1];
+assign alert_if[5].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[0];
+assign alert_if[6].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[1];
+assign alert_if[7].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[2];
+assign alert_if[8].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[0];
+assign alert_if[9].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[1];
+assign alert_if[10].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[2];
+assign alert_if[11].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[3];
+assign alert_if[12].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[4];
+assign alert_if[13].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[5];
+assign alert_if[14].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[6];
+assign alert_if[15].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[7];
+assign alert_if[16].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[8];
+assign alert_if[17].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[9];
+assign alert_if[18].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[10];
+assign alert_if[19].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0];
+assign alert_if[20].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[1];
+assign alert_if[21].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0];
+assign alert_if[22].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1];
+assign alert_if[23].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2];
+assign alert_if[24].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[3];
+assign alert_if[25].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[0];
+assign alert_if[26].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1];
+assign alert_if[27].alert_tx = `CHIP_HIER.u_hmac.alert_tx_o[0];
+assign alert_if[28].alert_tx = `CHIP_HIER.u_kmac.alert_tx_o[0];
+assign alert_if[29].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0];
+assign alert_if[30].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1];
+assign alert_if[31].alert_tx = `CHIP_HIER.u_csrng.alert_tx_o[0];
+assign alert_if[32].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0];
+assign alert_if[33].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[1];
+assign alert_if[34].alert_tx = `CHIP_HIER.u_edn0.alert_tx_o[0];
+assign alert_if[35].alert_tx = `CHIP_HIER.u_edn1.alert_tx_o[0];
+assign alert_if[36].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
+assign alert_if[37].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[1];
+assign alert_if[38].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0];
+assign alert_if[39].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1];
+assign alert_if[40].alert_tx = `CHIP_HIER.u_rom_ctrl.alert_tx_o[0];
diff --git a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
index fc1ed79..94aca81 100644
--- a/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
+++ b/hw/top_earlgrey/dv/env/autogen/chip_env_pkg__params.sv
@@ -7,6 +7,7 @@
parameter string LIST_OF_ALERTS[] = {
"spi_host0_fatal_fault",
"spi_host1_fatal_fault",
+ "pattgen_fatal_fault",
"otp_ctrl_fatal_macro_error",
"otp_ctrl_fatal_check_error",
"lc_ctrl_fatal_prog_error",
@@ -47,4 +48,4 @@
"rom_ctrl_fatal"
};
-parameter uint NUM_ALERTS = 40;
+parameter uint NUM_ALERTS = 41;
diff --git a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
index 126c560..ca8418f 100644
--- a/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
+++ b/hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson
@@ -48,7 +48,7 @@
{ name: "NAlerts",
desc: "Number of peripheral inputs",
type: "int",
- default: "40",
+ default: "41",
local: "true"
},
{ name: "EscCntDw",
@@ -66,7 +66,7 @@
{ name: "AsyncOn",
desc: "Number of peripheral outputs",
type: "logic [NAlerts-1:0]",
- default: "40'b1111111111111111111100000000000000000000",
+ default: "41'b11111111111111111111000000000000000000000",
local: "true"
},
{ name: "N_CLASSES",
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
index 02890d5..cd71a28 100644
--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv
@@ -7,10 +7,10 @@
package alert_handler_reg_pkg;
// Param list
- parameter int NAlerts = 40;
+ parameter int NAlerts = 41;
parameter int EscCntDw = 32;
parameter int AccuCntDw = 16;
- parameter logic [NAlerts-1:0] AsyncOn = 40'b1111111111111111111100000000000000000000;
+ parameter logic [NAlerts-1:0] AsyncOn = 41'b11111111111111111111000000000000000000000;
parameter int N_CLASSES = 4;
parameter int N_ESC_SEV = 4;
parameter int N_PHASES = 4;
@@ -458,15 +458,15 @@
// Register -> HW type
typedef struct packed {
- alert_handler_reg2hw_intr_state_reg_t intr_state; // [1028:1025]
- alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1024:1021]
- alert_handler_reg2hw_intr_test_reg_t intr_test; // [1020:1013]
- alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [1012:989]
- alert_handler_reg2hw_ping_timer_en_reg_t ping_timer_en; // [988:988]
- alert_handler_reg2hw_alert_regwen_mreg_t [39:0] alert_regwen; // [987:948]
- alert_handler_reg2hw_alert_en_mreg_t [39:0] alert_en; // [947:908]
- alert_handler_reg2hw_alert_class_mreg_t [39:0] alert_class; // [907:828]
- alert_handler_reg2hw_alert_cause_mreg_t [39:0] alert_cause; // [827:788]
+ alert_handler_reg2hw_intr_state_reg_t intr_state; // [1033:1030]
+ alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [1029:1026]
+ alert_handler_reg2hw_intr_test_reg_t intr_test; // [1025:1018]
+ alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [1017:994]
+ alert_handler_reg2hw_ping_timer_en_reg_t ping_timer_en; // [993:993]
+ alert_handler_reg2hw_alert_regwen_mreg_t [40:0] alert_regwen; // [992:952]
+ alert_handler_reg2hw_alert_en_mreg_t [40:0] alert_en; // [951:911]
+ alert_handler_reg2hw_alert_class_mreg_t [40:0] alert_class; // [910:829]
+ alert_handler_reg2hw_alert_cause_mreg_t [40:0] alert_cause; // [828:788]
alert_handler_reg2hw_loc_alert_en_mreg_t [4:0] loc_alert_en; // [787:783]
alert_handler_reg2hw_loc_alert_class_mreg_t [4:0] loc_alert_class; // [782:773]
alert_handler_reg2hw_loc_alert_cause_mreg_t [4:0] loc_alert_cause; // [772:768]
@@ -506,8 +506,8 @@
// HW -> register type
typedef struct packed {
- alert_handler_hw2reg_intr_state_reg_t intr_state; // [309:302]
- alert_handler_hw2reg_alert_cause_mreg_t [39:0] alert_cause; // [301:222]
+ alert_handler_hw2reg_intr_state_reg_t intr_state; // [311:304]
+ alert_handler_hw2reg_alert_cause_mreg_t [40:0] alert_cause; // [303:222]
alert_handler_hw2reg_loc_alert_cause_mreg_t [4:0] loc_alert_cause; // [221:212]
alert_handler_hw2reg_classa_clr_regwen_reg_t classa_clr_regwen; // [211:210]
alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [209:194]
@@ -574,198 +574,202 @@
parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_37_OFFSET = 10'h ac;
parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_38_OFFSET = 10'h b0;
parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_39_OFFSET = 10'h b4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_0_OFFSET = 10'h b8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_1_OFFSET = 10'h bc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_2_OFFSET = 10'h c0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_3_OFFSET = 10'h c4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_4_OFFSET = 10'h c8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_5_OFFSET = 10'h cc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_6_OFFSET = 10'h d0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_7_OFFSET = 10'h d4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_8_OFFSET = 10'h d8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_9_OFFSET = 10'h dc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_10_OFFSET = 10'h e0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_11_OFFSET = 10'h e4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_12_OFFSET = 10'h e8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_13_OFFSET = 10'h ec;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_14_OFFSET = 10'h f0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_15_OFFSET = 10'h f4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_16_OFFSET = 10'h f8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_17_OFFSET = 10'h fc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_18_OFFSET = 10'h 100;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_19_OFFSET = 10'h 104;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_20_OFFSET = 10'h 108;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_21_OFFSET = 10'h 10c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_22_OFFSET = 10'h 110;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_23_OFFSET = 10'h 114;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_24_OFFSET = 10'h 118;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_25_OFFSET = 10'h 11c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_26_OFFSET = 10'h 120;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_27_OFFSET = 10'h 124;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_28_OFFSET = 10'h 128;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_29_OFFSET = 10'h 12c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_30_OFFSET = 10'h 130;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_31_OFFSET = 10'h 134;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_32_OFFSET = 10'h 138;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_33_OFFSET = 10'h 13c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_34_OFFSET = 10'h 140;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_35_OFFSET = 10'h 144;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_36_OFFSET = 10'h 148;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_37_OFFSET = 10'h 14c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_38_OFFSET = 10'h 150;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_39_OFFSET = 10'h 154;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_0_OFFSET = 10'h 158;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_1_OFFSET = 10'h 15c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_2_OFFSET = 10'h 160;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_3_OFFSET = 10'h 164;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_4_OFFSET = 10'h 168;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_5_OFFSET = 10'h 16c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_6_OFFSET = 10'h 170;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_7_OFFSET = 10'h 174;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_8_OFFSET = 10'h 178;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_9_OFFSET = 10'h 17c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_10_OFFSET = 10'h 180;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_11_OFFSET = 10'h 184;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_12_OFFSET = 10'h 188;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_13_OFFSET = 10'h 18c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_14_OFFSET = 10'h 190;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_15_OFFSET = 10'h 194;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_16_OFFSET = 10'h 198;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_17_OFFSET = 10'h 19c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_18_OFFSET = 10'h 1a0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_19_OFFSET = 10'h 1a4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_20_OFFSET = 10'h 1a8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_21_OFFSET = 10'h 1ac;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_22_OFFSET = 10'h 1b0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_23_OFFSET = 10'h 1b4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_24_OFFSET = 10'h 1b8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_25_OFFSET = 10'h 1bc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_26_OFFSET = 10'h 1c0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_27_OFFSET = 10'h 1c4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_28_OFFSET = 10'h 1c8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_29_OFFSET = 10'h 1cc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_30_OFFSET = 10'h 1d0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_31_OFFSET = 10'h 1d4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_32_OFFSET = 10'h 1d8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_33_OFFSET = 10'h 1dc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_34_OFFSET = 10'h 1e0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_35_OFFSET = 10'h 1e4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_36_OFFSET = 10'h 1e8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_37_OFFSET = 10'h 1ec;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_38_OFFSET = 10'h 1f0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_39_OFFSET = 10'h 1f4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 10'h 1f8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 10'h 1fc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 10'h 200;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 10'h 204;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 10'h 208;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 10'h 20c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 10'h 210;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 10'h 214;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 10'h 218;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 10'h 21c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 10'h 220;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 10'h 224;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 10'h 228;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 10'h 22c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 10'h 230;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 10'h 234;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 10'h 238;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 10'h 23c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 10'h 240;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 10'h 244;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 10'h 248;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 10'h 24c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 10'h 250;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 10'h 254;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 10'h 258;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 10'h 25c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 10'h 260;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 10'h 264;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 10'h 268;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 10'h 26c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 10'h 270;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 10'h 274;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 10'h 278;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 10'h 27c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 10'h 280;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 10'h 284;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 10'h 288;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 10'h 28c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 10'h 290;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 10'h 294;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 10'h 298;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 10'h 29c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 10'h 2a0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 10'h 2a4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 10'h 2a8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET = 10'h 2ac;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET = 10'h 2b0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET = 10'h 2b4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET = 10'h 2b8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_4_OFFSET = 10'h 2bc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET = 10'h 2c0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET = 10'h 2c4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET = 10'h 2c8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET = 10'h 2cc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_4_OFFSET = 10'h 2d0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 10'h 2d4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 10'h 2d8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 10'h 2dc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 10'h 2e0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 10'h 2e4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 10'h 2e8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_OFFSET = 10'h 2ec;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 10'h 2f0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_OFFSET = 10'h 2f4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 10'h 2f8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET = 10'h 2fc;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET = 10'h 300;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET = 10'h 304;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET = 10'h 308;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET = 10'h 30c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET = 10'h 310;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 10'h 314;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 10'h 318;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 10'h 31c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_OFFSET = 10'h 320;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 10'h 324;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_OFFSET = 10'h 328;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 10'h 32c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET = 10'h 330;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET = 10'h 334;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET = 10'h 338;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET = 10'h 33c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET = 10'h 340;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET = 10'h 344;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 10'h 348;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 10'h 34c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 10'h 350;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_OFFSET = 10'h 354;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 10'h 358;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_OFFSET = 10'h 35c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 10'h 360;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET = 10'h 364;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET = 10'h 368;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET = 10'h 36c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET = 10'h 370;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET = 10'h 374;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET = 10'h 378;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 10'h 37c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 10'h 380;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 10'h 384;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_OFFSET = 10'h 388;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 10'h 38c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_OFFSET = 10'h 390;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 10'h 394;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET = 10'h 398;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET = 10'h 39c;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET = 10'h 3a0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET = 10'h 3a4;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET = 10'h 3a8;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET = 10'h 3ac;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 10'h 3b0;
- parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 10'h 3b4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_REGWEN_40_OFFSET = 10'h b8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_0_OFFSET = 10'h bc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_1_OFFSET = 10'h c0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_2_OFFSET = 10'h c4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_3_OFFSET = 10'h c8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_4_OFFSET = 10'h cc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_5_OFFSET = 10'h d0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_6_OFFSET = 10'h d4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_7_OFFSET = 10'h d8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_8_OFFSET = 10'h dc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_9_OFFSET = 10'h e0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_10_OFFSET = 10'h e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_11_OFFSET = 10'h e8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_12_OFFSET = 10'h ec;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_13_OFFSET = 10'h f0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_14_OFFSET = 10'h f4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_15_OFFSET = 10'h f8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_16_OFFSET = 10'h fc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_17_OFFSET = 10'h 100;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_18_OFFSET = 10'h 104;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_19_OFFSET = 10'h 108;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_20_OFFSET = 10'h 10c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_21_OFFSET = 10'h 110;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_22_OFFSET = 10'h 114;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_23_OFFSET = 10'h 118;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_24_OFFSET = 10'h 11c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_25_OFFSET = 10'h 120;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_26_OFFSET = 10'h 124;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_27_OFFSET = 10'h 128;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_28_OFFSET = 10'h 12c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_29_OFFSET = 10'h 130;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_30_OFFSET = 10'h 134;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_31_OFFSET = 10'h 138;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_32_OFFSET = 10'h 13c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_33_OFFSET = 10'h 140;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_34_OFFSET = 10'h 144;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_35_OFFSET = 10'h 148;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_36_OFFSET = 10'h 14c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_37_OFFSET = 10'h 150;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_38_OFFSET = 10'h 154;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_39_OFFSET = 10'h 158;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_EN_40_OFFSET = 10'h 15c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_0_OFFSET = 10'h 160;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_1_OFFSET = 10'h 164;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_2_OFFSET = 10'h 168;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_3_OFFSET = 10'h 16c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_4_OFFSET = 10'h 170;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_5_OFFSET = 10'h 174;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_6_OFFSET = 10'h 178;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_7_OFFSET = 10'h 17c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_8_OFFSET = 10'h 180;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_9_OFFSET = 10'h 184;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_10_OFFSET = 10'h 188;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_11_OFFSET = 10'h 18c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_12_OFFSET = 10'h 190;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_13_OFFSET = 10'h 194;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_14_OFFSET = 10'h 198;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_15_OFFSET = 10'h 19c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_16_OFFSET = 10'h 1a0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_17_OFFSET = 10'h 1a4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_18_OFFSET = 10'h 1a8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_19_OFFSET = 10'h 1ac;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_20_OFFSET = 10'h 1b0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_21_OFFSET = 10'h 1b4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_22_OFFSET = 10'h 1b8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_23_OFFSET = 10'h 1bc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_24_OFFSET = 10'h 1c0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_25_OFFSET = 10'h 1c4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_26_OFFSET = 10'h 1c8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_27_OFFSET = 10'h 1cc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_28_OFFSET = 10'h 1d0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_29_OFFSET = 10'h 1d4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_30_OFFSET = 10'h 1d8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_31_OFFSET = 10'h 1dc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_32_OFFSET = 10'h 1e0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_33_OFFSET = 10'h 1e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_34_OFFSET = 10'h 1e8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_35_OFFSET = 10'h 1ec;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_36_OFFSET = 10'h 1f0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_37_OFFSET = 10'h 1f4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_38_OFFSET = 10'h 1f8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_39_OFFSET = 10'h 1fc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CLASS_40_OFFSET = 10'h 200;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_0_OFFSET = 10'h 204;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_1_OFFSET = 10'h 208;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_2_OFFSET = 10'h 20c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_3_OFFSET = 10'h 210;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_4_OFFSET = 10'h 214;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_5_OFFSET = 10'h 218;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_6_OFFSET = 10'h 21c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_7_OFFSET = 10'h 220;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_8_OFFSET = 10'h 224;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_9_OFFSET = 10'h 228;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_10_OFFSET = 10'h 22c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_11_OFFSET = 10'h 230;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_12_OFFSET = 10'h 234;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_13_OFFSET = 10'h 238;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_14_OFFSET = 10'h 23c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_15_OFFSET = 10'h 240;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_16_OFFSET = 10'h 244;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_17_OFFSET = 10'h 248;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_18_OFFSET = 10'h 24c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_19_OFFSET = 10'h 250;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_20_OFFSET = 10'h 254;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_21_OFFSET = 10'h 258;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_22_OFFSET = 10'h 25c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_23_OFFSET = 10'h 260;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_24_OFFSET = 10'h 264;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_25_OFFSET = 10'h 268;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_26_OFFSET = 10'h 26c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_27_OFFSET = 10'h 270;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_28_OFFSET = 10'h 274;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_29_OFFSET = 10'h 278;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_30_OFFSET = 10'h 27c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_31_OFFSET = 10'h 280;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_32_OFFSET = 10'h 284;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_33_OFFSET = 10'h 288;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_34_OFFSET = 10'h 28c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_35_OFFSET = 10'h 290;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_36_OFFSET = 10'h 294;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_37_OFFSET = 10'h 298;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_38_OFFSET = 10'h 29c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_39_OFFSET = 10'h 2a0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_ALERT_CAUSE_40_OFFSET = 10'h 2a4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET = 10'h 2a8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET = 10'h 2ac;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET = 10'h 2b0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET = 10'h 2b4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET = 10'h 2b8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET = 10'h 2bc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET = 10'h 2c0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET = 10'h 2c4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET = 10'h 2c8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_EN_4_OFFSET = 10'h 2cc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET = 10'h 2d0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET = 10'h 2d4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET = 10'h 2d8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET = 10'h 2dc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CLASS_4_OFFSET = 10'h 2e0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET = 10'h 2e4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET = 10'h 2e8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET = 10'h 2ec;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET = 10'h 2f0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET = 10'h 2f4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_REGWEN_OFFSET = 10'h 2f8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CTRL_OFFSET = 10'h 2fc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET = 10'h 300;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_CLR_OFFSET = 10'h 304;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 10'h 308;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET = 10'h 30c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET = 10'h 310;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET = 10'h 314;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET = 10'h 318;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET = 10'h 31c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET = 10'h 320;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 10'h 324;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSA_STATE_OFFSET = 10'h 328;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_REGWEN_OFFSET = 10'h 32c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CTRL_OFFSET = 10'h 330;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET = 10'h 334;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_CLR_OFFSET = 10'h 338;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 10'h 33c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET = 10'h 340;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET = 10'h 344;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET = 10'h 348;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET = 10'h 34c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET = 10'h 350;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET = 10'h 354;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 10'h 358;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSB_STATE_OFFSET = 10'h 35c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_REGWEN_OFFSET = 10'h 360;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CTRL_OFFSET = 10'h 364;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET = 10'h 368;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_CLR_OFFSET = 10'h 36c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 10'h 370;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET = 10'h 374;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET = 10'h 378;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET = 10'h 37c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET = 10'h 380;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET = 10'h 384;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET = 10'h 388;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 10'h 38c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSC_STATE_OFFSET = 10'h 390;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_REGWEN_OFFSET = 10'h 394;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CTRL_OFFSET = 10'h 398;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET = 10'h 39c;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_CLR_OFFSET = 10'h 3a0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 10'h 3a4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET = 10'h 3a8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET = 10'h 3ac;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET = 10'h 3b0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET = 10'h 3b4;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET = 10'h 3b8;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET = 10'h 3bc;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 10'h 3c0;
+ parameter logic [BlockAw-1:0] ALERT_HANDLER_CLASSD_STATE_OFFSET = 10'h 3c4;
// Reset values for hwext registers and their fields
parameter logic [3:0] ALERT_HANDLER_INTR_TEST_RESVAL = 4'h 0;
@@ -834,6 +838,7 @@
ALERT_HANDLER_ALERT_REGWEN_37,
ALERT_HANDLER_ALERT_REGWEN_38,
ALERT_HANDLER_ALERT_REGWEN_39,
+ ALERT_HANDLER_ALERT_REGWEN_40,
ALERT_HANDLER_ALERT_EN_0,
ALERT_HANDLER_ALERT_EN_1,
ALERT_HANDLER_ALERT_EN_2,
@@ -874,6 +879,7 @@
ALERT_HANDLER_ALERT_EN_37,
ALERT_HANDLER_ALERT_EN_38,
ALERT_HANDLER_ALERT_EN_39,
+ ALERT_HANDLER_ALERT_EN_40,
ALERT_HANDLER_ALERT_CLASS_0,
ALERT_HANDLER_ALERT_CLASS_1,
ALERT_HANDLER_ALERT_CLASS_2,
@@ -914,6 +920,7 @@
ALERT_HANDLER_ALERT_CLASS_37,
ALERT_HANDLER_ALERT_CLASS_38,
ALERT_HANDLER_ALERT_CLASS_39,
+ ALERT_HANDLER_ALERT_CLASS_40,
ALERT_HANDLER_ALERT_CAUSE_0,
ALERT_HANDLER_ALERT_CAUSE_1,
ALERT_HANDLER_ALERT_CAUSE_2,
@@ -954,6 +961,7 @@
ALERT_HANDLER_ALERT_CAUSE_37,
ALERT_HANDLER_ALERT_CAUSE_38,
ALERT_HANDLER_ALERT_CAUSE_39,
+ ALERT_HANDLER_ALERT_CAUSE_40,
ALERT_HANDLER_LOC_ALERT_REGWEN_0,
ALERT_HANDLER_LOC_ALERT_REGWEN_1,
ALERT_HANDLER_LOC_ALERT_REGWEN_2,
@@ -1029,7 +1037,7 @@
} alert_handler_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] ALERT_HANDLER_PERMIT [238] = '{
+ parameter logic [3:0] ALERT_HANDLER_PERMIT [242] = '{
4'b 0001, // index[ 0] ALERT_HANDLER_INTR_STATE
4'b 0001, // index[ 1] ALERT_HANDLER_INTR_ENABLE
4'b 0001, // index[ 2] ALERT_HANDLER_INTR_TEST
@@ -1076,198 +1084,202 @@
4'b 0001, // index[ 43] ALERT_HANDLER_ALERT_REGWEN_37
4'b 0001, // index[ 44] ALERT_HANDLER_ALERT_REGWEN_38
4'b 0001, // index[ 45] ALERT_HANDLER_ALERT_REGWEN_39
- 4'b 0001, // index[ 46] ALERT_HANDLER_ALERT_EN_0
- 4'b 0001, // index[ 47] ALERT_HANDLER_ALERT_EN_1
- 4'b 0001, // index[ 48] ALERT_HANDLER_ALERT_EN_2
- 4'b 0001, // index[ 49] ALERT_HANDLER_ALERT_EN_3
- 4'b 0001, // index[ 50] ALERT_HANDLER_ALERT_EN_4
- 4'b 0001, // index[ 51] ALERT_HANDLER_ALERT_EN_5
- 4'b 0001, // index[ 52] ALERT_HANDLER_ALERT_EN_6
- 4'b 0001, // index[ 53] ALERT_HANDLER_ALERT_EN_7
- 4'b 0001, // index[ 54] ALERT_HANDLER_ALERT_EN_8
- 4'b 0001, // index[ 55] ALERT_HANDLER_ALERT_EN_9
- 4'b 0001, // index[ 56] ALERT_HANDLER_ALERT_EN_10
- 4'b 0001, // index[ 57] ALERT_HANDLER_ALERT_EN_11
- 4'b 0001, // index[ 58] ALERT_HANDLER_ALERT_EN_12
- 4'b 0001, // index[ 59] ALERT_HANDLER_ALERT_EN_13
- 4'b 0001, // index[ 60] ALERT_HANDLER_ALERT_EN_14
- 4'b 0001, // index[ 61] ALERT_HANDLER_ALERT_EN_15
- 4'b 0001, // index[ 62] ALERT_HANDLER_ALERT_EN_16
- 4'b 0001, // index[ 63] ALERT_HANDLER_ALERT_EN_17
- 4'b 0001, // index[ 64] ALERT_HANDLER_ALERT_EN_18
- 4'b 0001, // index[ 65] ALERT_HANDLER_ALERT_EN_19
- 4'b 0001, // index[ 66] ALERT_HANDLER_ALERT_EN_20
- 4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_EN_21
- 4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_EN_22
- 4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_EN_23
- 4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_EN_24
- 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_EN_25
- 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_26
- 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_27
- 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_28
- 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_29
- 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_30
- 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_31
- 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_32
- 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_33
- 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_34
- 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_35
- 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_36
- 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_37
- 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_38
- 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_39
- 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_CLASS_0
- 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_CLASS_1
- 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_CLASS_2
- 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_CLASS_3
- 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_CLASS_4
- 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_CLASS_5
- 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_CLASS_6
- 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_CLASS_7
- 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_CLASS_8
- 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_CLASS_9
- 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_CLASS_10
- 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_CLASS_11
- 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_CLASS_12
- 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_CLASS_13
- 4'b 0001, // index[100] ALERT_HANDLER_ALERT_CLASS_14
- 4'b 0001, // index[101] ALERT_HANDLER_ALERT_CLASS_15
- 4'b 0001, // index[102] ALERT_HANDLER_ALERT_CLASS_16
- 4'b 0001, // index[103] ALERT_HANDLER_ALERT_CLASS_17
- 4'b 0001, // index[104] ALERT_HANDLER_ALERT_CLASS_18
- 4'b 0001, // index[105] ALERT_HANDLER_ALERT_CLASS_19
- 4'b 0001, // index[106] ALERT_HANDLER_ALERT_CLASS_20
- 4'b 0001, // index[107] ALERT_HANDLER_ALERT_CLASS_21
- 4'b 0001, // index[108] ALERT_HANDLER_ALERT_CLASS_22
- 4'b 0001, // index[109] ALERT_HANDLER_ALERT_CLASS_23
- 4'b 0001, // index[110] ALERT_HANDLER_ALERT_CLASS_24
- 4'b 0001, // index[111] ALERT_HANDLER_ALERT_CLASS_25
- 4'b 0001, // index[112] ALERT_HANDLER_ALERT_CLASS_26
- 4'b 0001, // index[113] ALERT_HANDLER_ALERT_CLASS_27
- 4'b 0001, // index[114] ALERT_HANDLER_ALERT_CLASS_28
- 4'b 0001, // index[115] ALERT_HANDLER_ALERT_CLASS_29
- 4'b 0001, // index[116] ALERT_HANDLER_ALERT_CLASS_30
- 4'b 0001, // index[117] ALERT_HANDLER_ALERT_CLASS_31
- 4'b 0001, // index[118] ALERT_HANDLER_ALERT_CLASS_32
- 4'b 0001, // index[119] ALERT_HANDLER_ALERT_CLASS_33
- 4'b 0001, // index[120] ALERT_HANDLER_ALERT_CLASS_34
- 4'b 0001, // index[121] ALERT_HANDLER_ALERT_CLASS_35
- 4'b 0001, // index[122] ALERT_HANDLER_ALERT_CLASS_36
- 4'b 0001, // index[123] ALERT_HANDLER_ALERT_CLASS_37
- 4'b 0001, // index[124] ALERT_HANDLER_ALERT_CLASS_38
- 4'b 0001, // index[125] ALERT_HANDLER_ALERT_CLASS_39
- 4'b 0001, // index[126] ALERT_HANDLER_ALERT_CAUSE_0
- 4'b 0001, // index[127] ALERT_HANDLER_ALERT_CAUSE_1
- 4'b 0001, // index[128] ALERT_HANDLER_ALERT_CAUSE_2
- 4'b 0001, // index[129] ALERT_HANDLER_ALERT_CAUSE_3
- 4'b 0001, // index[130] ALERT_HANDLER_ALERT_CAUSE_4
- 4'b 0001, // index[131] ALERT_HANDLER_ALERT_CAUSE_5
- 4'b 0001, // index[132] ALERT_HANDLER_ALERT_CAUSE_6
- 4'b 0001, // index[133] ALERT_HANDLER_ALERT_CAUSE_7
- 4'b 0001, // index[134] ALERT_HANDLER_ALERT_CAUSE_8
- 4'b 0001, // index[135] ALERT_HANDLER_ALERT_CAUSE_9
- 4'b 0001, // index[136] ALERT_HANDLER_ALERT_CAUSE_10
- 4'b 0001, // index[137] ALERT_HANDLER_ALERT_CAUSE_11
- 4'b 0001, // index[138] ALERT_HANDLER_ALERT_CAUSE_12
- 4'b 0001, // index[139] ALERT_HANDLER_ALERT_CAUSE_13
- 4'b 0001, // index[140] ALERT_HANDLER_ALERT_CAUSE_14
- 4'b 0001, // index[141] ALERT_HANDLER_ALERT_CAUSE_15
- 4'b 0001, // index[142] ALERT_HANDLER_ALERT_CAUSE_16
- 4'b 0001, // index[143] ALERT_HANDLER_ALERT_CAUSE_17
- 4'b 0001, // index[144] ALERT_HANDLER_ALERT_CAUSE_18
- 4'b 0001, // index[145] ALERT_HANDLER_ALERT_CAUSE_19
- 4'b 0001, // index[146] ALERT_HANDLER_ALERT_CAUSE_20
- 4'b 0001, // index[147] ALERT_HANDLER_ALERT_CAUSE_21
- 4'b 0001, // index[148] ALERT_HANDLER_ALERT_CAUSE_22
- 4'b 0001, // index[149] ALERT_HANDLER_ALERT_CAUSE_23
- 4'b 0001, // index[150] ALERT_HANDLER_ALERT_CAUSE_24
- 4'b 0001, // index[151] ALERT_HANDLER_ALERT_CAUSE_25
- 4'b 0001, // index[152] ALERT_HANDLER_ALERT_CAUSE_26
- 4'b 0001, // index[153] ALERT_HANDLER_ALERT_CAUSE_27
- 4'b 0001, // index[154] ALERT_HANDLER_ALERT_CAUSE_28
- 4'b 0001, // index[155] ALERT_HANDLER_ALERT_CAUSE_29
- 4'b 0001, // index[156] ALERT_HANDLER_ALERT_CAUSE_30
- 4'b 0001, // index[157] ALERT_HANDLER_ALERT_CAUSE_31
- 4'b 0001, // index[158] ALERT_HANDLER_ALERT_CAUSE_32
- 4'b 0001, // index[159] ALERT_HANDLER_ALERT_CAUSE_33
- 4'b 0001, // index[160] ALERT_HANDLER_ALERT_CAUSE_34
- 4'b 0001, // index[161] ALERT_HANDLER_ALERT_CAUSE_35
- 4'b 0001, // index[162] ALERT_HANDLER_ALERT_CAUSE_36
- 4'b 0001, // index[163] ALERT_HANDLER_ALERT_CAUSE_37
- 4'b 0001, // index[164] ALERT_HANDLER_ALERT_CAUSE_38
- 4'b 0001, // index[165] ALERT_HANDLER_ALERT_CAUSE_39
- 4'b 0001, // index[166] ALERT_HANDLER_LOC_ALERT_REGWEN_0
- 4'b 0001, // index[167] ALERT_HANDLER_LOC_ALERT_REGWEN_1
- 4'b 0001, // index[168] ALERT_HANDLER_LOC_ALERT_REGWEN_2
- 4'b 0001, // index[169] ALERT_HANDLER_LOC_ALERT_REGWEN_3
- 4'b 0001, // index[170] ALERT_HANDLER_LOC_ALERT_REGWEN_4
- 4'b 0001, // index[171] ALERT_HANDLER_LOC_ALERT_EN_0
- 4'b 0001, // index[172] ALERT_HANDLER_LOC_ALERT_EN_1
- 4'b 0001, // index[173] ALERT_HANDLER_LOC_ALERT_EN_2
- 4'b 0001, // index[174] ALERT_HANDLER_LOC_ALERT_EN_3
- 4'b 0001, // index[175] ALERT_HANDLER_LOC_ALERT_EN_4
- 4'b 0001, // index[176] ALERT_HANDLER_LOC_ALERT_CLASS_0
- 4'b 0001, // index[177] ALERT_HANDLER_LOC_ALERT_CLASS_1
- 4'b 0001, // index[178] ALERT_HANDLER_LOC_ALERT_CLASS_2
- 4'b 0001, // index[179] ALERT_HANDLER_LOC_ALERT_CLASS_3
- 4'b 0001, // index[180] ALERT_HANDLER_LOC_ALERT_CLASS_4
- 4'b 0001, // index[181] ALERT_HANDLER_LOC_ALERT_CAUSE_0
- 4'b 0001, // index[182] ALERT_HANDLER_LOC_ALERT_CAUSE_1
- 4'b 0001, // index[183] ALERT_HANDLER_LOC_ALERT_CAUSE_2
- 4'b 0001, // index[184] ALERT_HANDLER_LOC_ALERT_CAUSE_3
- 4'b 0001, // index[185] ALERT_HANDLER_LOC_ALERT_CAUSE_4
- 4'b 0001, // index[186] ALERT_HANDLER_CLASSA_REGWEN
- 4'b 0011, // index[187] ALERT_HANDLER_CLASSA_CTRL
- 4'b 0001, // index[188] ALERT_HANDLER_CLASSA_CLR_REGWEN
- 4'b 0001, // index[189] ALERT_HANDLER_CLASSA_CLR
- 4'b 0011, // index[190] ALERT_HANDLER_CLASSA_ACCUM_CNT
- 4'b 0011, // index[191] ALERT_HANDLER_CLASSA_ACCUM_THRESH
- 4'b 1111, // index[192] ALERT_HANDLER_CLASSA_TIMEOUT_CYC
- 4'b 1111, // index[193] ALERT_HANDLER_CLASSA_PHASE0_CYC
- 4'b 1111, // index[194] ALERT_HANDLER_CLASSA_PHASE1_CYC
- 4'b 1111, // index[195] ALERT_HANDLER_CLASSA_PHASE2_CYC
- 4'b 1111, // index[196] ALERT_HANDLER_CLASSA_PHASE3_CYC
- 4'b 1111, // index[197] ALERT_HANDLER_CLASSA_ESC_CNT
- 4'b 0001, // index[198] ALERT_HANDLER_CLASSA_STATE
- 4'b 0001, // index[199] ALERT_HANDLER_CLASSB_REGWEN
- 4'b 0011, // index[200] ALERT_HANDLER_CLASSB_CTRL
- 4'b 0001, // index[201] ALERT_HANDLER_CLASSB_CLR_REGWEN
- 4'b 0001, // index[202] ALERT_HANDLER_CLASSB_CLR
- 4'b 0011, // index[203] ALERT_HANDLER_CLASSB_ACCUM_CNT
- 4'b 0011, // index[204] ALERT_HANDLER_CLASSB_ACCUM_THRESH
- 4'b 1111, // index[205] ALERT_HANDLER_CLASSB_TIMEOUT_CYC
- 4'b 1111, // index[206] ALERT_HANDLER_CLASSB_PHASE0_CYC
- 4'b 1111, // index[207] ALERT_HANDLER_CLASSB_PHASE1_CYC
- 4'b 1111, // index[208] ALERT_HANDLER_CLASSB_PHASE2_CYC
- 4'b 1111, // index[209] ALERT_HANDLER_CLASSB_PHASE3_CYC
- 4'b 1111, // index[210] ALERT_HANDLER_CLASSB_ESC_CNT
- 4'b 0001, // index[211] ALERT_HANDLER_CLASSB_STATE
- 4'b 0001, // index[212] ALERT_HANDLER_CLASSC_REGWEN
- 4'b 0011, // index[213] ALERT_HANDLER_CLASSC_CTRL
- 4'b 0001, // index[214] ALERT_HANDLER_CLASSC_CLR_REGWEN
- 4'b 0001, // index[215] ALERT_HANDLER_CLASSC_CLR
- 4'b 0011, // index[216] ALERT_HANDLER_CLASSC_ACCUM_CNT
- 4'b 0011, // index[217] ALERT_HANDLER_CLASSC_ACCUM_THRESH
- 4'b 1111, // index[218] ALERT_HANDLER_CLASSC_TIMEOUT_CYC
- 4'b 1111, // index[219] ALERT_HANDLER_CLASSC_PHASE0_CYC
- 4'b 1111, // index[220] ALERT_HANDLER_CLASSC_PHASE1_CYC
- 4'b 1111, // index[221] ALERT_HANDLER_CLASSC_PHASE2_CYC
- 4'b 1111, // index[222] ALERT_HANDLER_CLASSC_PHASE3_CYC
- 4'b 1111, // index[223] ALERT_HANDLER_CLASSC_ESC_CNT
- 4'b 0001, // index[224] ALERT_HANDLER_CLASSC_STATE
- 4'b 0001, // index[225] ALERT_HANDLER_CLASSD_REGWEN
- 4'b 0011, // index[226] ALERT_HANDLER_CLASSD_CTRL
- 4'b 0001, // index[227] ALERT_HANDLER_CLASSD_CLR_REGWEN
- 4'b 0001, // index[228] ALERT_HANDLER_CLASSD_CLR
- 4'b 0011, // index[229] ALERT_HANDLER_CLASSD_ACCUM_CNT
- 4'b 0011, // index[230] ALERT_HANDLER_CLASSD_ACCUM_THRESH
- 4'b 1111, // index[231] ALERT_HANDLER_CLASSD_TIMEOUT_CYC
- 4'b 1111, // index[232] ALERT_HANDLER_CLASSD_PHASE0_CYC
- 4'b 1111, // index[233] ALERT_HANDLER_CLASSD_PHASE1_CYC
- 4'b 1111, // index[234] ALERT_HANDLER_CLASSD_PHASE2_CYC
- 4'b 1111, // index[235] ALERT_HANDLER_CLASSD_PHASE3_CYC
- 4'b 1111, // index[236] ALERT_HANDLER_CLASSD_ESC_CNT
- 4'b 0001 // index[237] ALERT_HANDLER_CLASSD_STATE
+ 4'b 0001, // index[ 46] ALERT_HANDLER_ALERT_REGWEN_40
+ 4'b 0001, // index[ 47] ALERT_HANDLER_ALERT_EN_0
+ 4'b 0001, // index[ 48] ALERT_HANDLER_ALERT_EN_1
+ 4'b 0001, // index[ 49] ALERT_HANDLER_ALERT_EN_2
+ 4'b 0001, // index[ 50] ALERT_HANDLER_ALERT_EN_3
+ 4'b 0001, // index[ 51] ALERT_HANDLER_ALERT_EN_4
+ 4'b 0001, // index[ 52] ALERT_HANDLER_ALERT_EN_5
+ 4'b 0001, // index[ 53] ALERT_HANDLER_ALERT_EN_6
+ 4'b 0001, // index[ 54] ALERT_HANDLER_ALERT_EN_7
+ 4'b 0001, // index[ 55] ALERT_HANDLER_ALERT_EN_8
+ 4'b 0001, // index[ 56] ALERT_HANDLER_ALERT_EN_9
+ 4'b 0001, // index[ 57] ALERT_HANDLER_ALERT_EN_10
+ 4'b 0001, // index[ 58] ALERT_HANDLER_ALERT_EN_11
+ 4'b 0001, // index[ 59] ALERT_HANDLER_ALERT_EN_12
+ 4'b 0001, // index[ 60] ALERT_HANDLER_ALERT_EN_13
+ 4'b 0001, // index[ 61] ALERT_HANDLER_ALERT_EN_14
+ 4'b 0001, // index[ 62] ALERT_HANDLER_ALERT_EN_15
+ 4'b 0001, // index[ 63] ALERT_HANDLER_ALERT_EN_16
+ 4'b 0001, // index[ 64] ALERT_HANDLER_ALERT_EN_17
+ 4'b 0001, // index[ 65] ALERT_HANDLER_ALERT_EN_18
+ 4'b 0001, // index[ 66] ALERT_HANDLER_ALERT_EN_19
+ 4'b 0001, // index[ 67] ALERT_HANDLER_ALERT_EN_20
+ 4'b 0001, // index[ 68] ALERT_HANDLER_ALERT_EN_21
+ 4'b 0001, // index[ 69] ALERT_HANDLER_ALERT_EN_22
+ 4'b 0001, // index[ 70] ALERT_HANDLER_ALERT_EN_23
+ 4'b 0001, // index[ 71] ALERT_HANDLER_ALERT_EN_24
+ 4'b 0001, // index[ 72] ALERT_HANDLER_ALERT_EN_25
+ 4'b 0001, // index[ 73] ALERT_HANDLER_ALERT_EN_26
+ 4'b 0001, // index[ 74] ALERT_HANDLER_ALERT_EN_27
+ 4'b 0001, // index[ 75] ALERT_HANDLER_ALERT_EN_28
+ 4'b 0001, // index[ 76] ALERT_HANDLER_ALERT_EN_29
+ 4'b 0001, // index[ 77] ALERT_HANDLER_ALERT_EN_30
+ 4'b 0001, // index[ 78] ALERT_HANDLER_ALERT_EN_31
+ 4'b 0001, // index[ 79] ALERT_HANDLER_ALERT_EN_32
+ 4'b 0001, // index[ 80] ALERT_HANDLER_ALERT_EN_33
+ 4'b 0001, // index[ 81] ALERT_HANDLER_ALERT_EN_34
+ 4'b 0001, // index[ 82] ALERT_HANDLER_ALERT_EN_35
+ 4'b 0001, // index[ 83] ALERT_HANDLER_ALERT_EN_36
+ 4'b 0001, // index[ 84] ALERT_HANDLER_ALERT_EN_37
+ 4'b 0001, // index[ 85] ALERT_HANDLER_ALERT_EN_38
+ 4'b 0001, // index[ 86] ALERT_HANDLER_ALERT_EN_39
+ 4'b 0001, // index[ 87] ALERT_HANDLER_ALERT_EN_40
+ 4'b 0001, // index[ 88] ALERT_HANDLER_ALERT_CLASS_0
+ 4'b 0001, // index[ 89] ALERT_HANDLER_ALERT_CLASS_1
+ 4'b 0001, // index[ 90] ALERT_HANDLER_ALERT_CLASS_2
+ 4'b 0001, // index[ 91] ALERT_HANDLER_ALERT_CLASS_3
+ 4'b 0001, // index[ 92] ALERT_HANDLER_ALERT_CLASS_4
+ 4'b 0001, // index[ 93] ALERT_HANDLER_ALERT_CLASS_5
+ 4'b 0001, // index[ 94] ALERT_HANDLER_ALERT_CLASS_6
+ 4'b 0001, // index[ 95] ALERT_HANDLER_ALERT_CLASS_7
+ 4'b 0001, // index[ 96] ALERT_HANDLER_ALERT_CLASS_8
+ 4'b 0001, // index[ 97] ALERT_HANDLER_ALERT_CLASS_9
+ 4'b 0001, // index[ 98] ALERT_HANDLER_ALERT_CLASS_10
+ 4'b 0001, // index[ 99] ALERT_HANDLER_ALERT_CLASS_11
+ 4'b 0001, // index[100] ALERT_HANDLER_ALERT_CLASS_12
+ 4'b 0001, // index[101] ALERT_HANDLER_ALERT_CLASS_13
+ 4'b 0001, // index[102] ALERT_HANDLER_ALERT_CLASS_14
+ 4'b 0001, // index[103] ALERT_HANDLER_ALERT_CLASS_15
+ 4'b 0001, // index[104] ALERT_HANDLER_ALERT_CLASS_16
+ 4'b 0001, // index[105] ALERT_HANDLER_ALERT_CLASS_17
+ 4'b 0001, // index[106] ALERT_HANDLER_ALERT_CLASS_18
+ 4'b 0001, // index[107] ALERT_HANDLER_ALERT_CLASS_19
+ 4'b 0001, // index[108] ALERT_HANDLER_ALERT_CLASS_20
+ 4'b 0001, // index[109] ALERT_HANDLER_ALERT_CLASS_21
+ 4'b 0001, // index[110] ALERT_HANDLER_ALERT_CLASS_22
+ 4'b 0001, // index[111] ALERT_HANDLER_ALERT_CLASS_23
+ 4'b 0001, // index[112] ALERT_HANDLER_ALERT_CLASS_24
+ 4'b 0001, // index[113] ALERT_HANDLER_ALERT_CLASS_25
+ 4'b 0001, // index[114] ALERT_HANDLER_ALERT_CLASS_26
+ 4'b 0001, // index[115] ALERT_HANDLER_ALERT_CLASS_27
+ 4'b 0001, // index[116] ALERT_HANDLER_ALERT_CLASS_28
+ 4'b 0001, // index[117] ALERT_HANDLER_ALERT_CLASS_29
+ 4'b 0001, // index[118] ALERT_HANDLER_ALERT_CLASS_30
+ 4'b 0001, // index[119] ALERT_HANDLER_ALERT_CLASS_31
+ 4'b 0001, // index[120] ALERT_HANDLER_ALERT_CLASS_32
+ 4'b 0001, // index[121] ALERT_HANDLER_ALERT_CLASS_33
+ 4'b 0001, // index[122] ALERT_HANDLER_ALERT_CLASS_34
+ 4'b 0001, // index[123] ALERT_HANDLER_ALERT_CLASS_35
+ 4'b 0001, // index[124] ALERT_HANDLER_ALERT_CLASS_36
+ 4'b 0001, // index[125] ALERT_HANDLER_ALERT_CLASS_37
+ 4'b 0001, // index[126] ALERT_HANDLER_ALERT_CLASS_38
+ 4'b 0001, // index[127] ALERT_HANDLER_ALERT_CLASS_39
+ 4'b 0001, // index[128] ALERT_HANDLER_ALERT_CLASS_40
+ 4'b 0001, // index[129] ALERT_HANDLER_ALERT_CAUSE_0
+ 4'b 0001, // index[130] ALERT_HANDLER_ALERT_CAUSE_1
+ 4'b 0001, // index[131] ALERT_HANDLER_ALERT_CAUSE_2
+ 4'b 0001, // index[132] ALERT_HANDLER_ALERT_CAUSE_3
+ 4'b 0001, // index[133] ALERT_HANDLER_ALERT_CAUSE_4
+ 4'b 0001, // index[134] ALERT_HANDLER_ALERT_CAUSE_5
+ 4'b 0001, // index[135] ALERT_HANDLER_ALERT_CAUSE_6
+ 4'b 0001, // index[136] ALERT_HANDLER_ALERT_CAUSE_7
+ 4'b 0001, // index[137] ALERT_HANDLER_ALERT_CAUSE_8
+ 4'b 0001, // index[138] ALERT_HANDLER_ALERT_CAUSE_9
+ 4'b 0001, // index[139] ALERT_HANDLER_ALERT_CAUSE_10
+ 4'b 0001, // index[140] ALERT_HANDLER_ALERT_CAUSE_11
+ 4'b 0001, // index[141] ALERT_HANDLER_ALERT_CAUSE_12
+ 4'b 0001, // index[142] ALERT_HANDLER_ALERT_CAUSE_13
+ 4'b 0001, // index[143] ALERT_HANDLER_ALERT_CAUSE_14
+ 4'b 0001, // index[144] ALERT_HANDLER_ALERT_CAUSE_15
+ 4'b 0001, // index[145] ALERT_HANDLER_ALERT_CAUSE_16
+ 4'b 0001, // index[146] ALERT_HANDLER_ALERT_CAUSE_17
+ 4'b 0001, // index[147] ALERT_HANDLER_ALERT_CAUSE_18
+ 4'b 0001, // index[148] ALERT_HANDLER_ALERT_CAUSE_19
+ 4'b 0001, // index[149] ALERT_HANDLER_ALERT_CAUSE_20
+ 4'b 0001, // index[150] ALERT_HANDLER_ALERT_CAUSE_21
+ 4'b 0001, // index[151] ALERT_HANDLER_ALERT_CAUSE_22
+ 4'b 0001, // index[152] ALERT_HANDLER_ALERT_CAUSE_23
+ 4'b 0001, // index[153] ALERT_HANDLER_ALERT_CAUSE_24
+ 4'b 0001, // index[154] ALERT_HANDLER_ALERT_CAUSE_25
+ 4'b 0001, // index[155] ALERT_HANDLER_ALERT_CAUSE_26
+ 4'b 0001, // index[156] ALERT_HANDLER_ALERT_CAUSE_27
+ 4'b 0001, // index[157] ALERT_HANDLER_ALERT_CAUSE_28
+ 4'b 0001, // index[158] ALERT_HANDLER_ALERT_CAUSE_29
+ 4'b 0001, // index[159] ALERT_HANDLER_ALERT_CAUSE_30
+ 4'b 0001, // index[160] ALERT_HANDLER_ALERT_CAUSE_31
+ 4'b 0001, // index[161] ALERT_HANDLER_ALERT_CAUSE_32
+ 4'b 0001, // index[162] ALERT_HANDLER_ALERT_CAUSE_33
+ 4'b 0001, // index[163] ALERT_HANDLER_ALERT_CAUSE_34
+ 4'b 0001, // index[164] ALERT_HANDLER_ALERT_CAUSE_35
+ 4'b 0001, // index[165] ALERT_HANDLER_ALERT_CAUSE_36
+ 4'b 0001, // index[166] ALERT_HANDLER_ALERT_CAUSE_37
+ 4'b 0001, // index[167] ALERT_HANDLER_ALERT_CAUSE_38
+ 4'b 0001, // index[168] ALERT_HANDLER_ALERT_CAUSE_39
+ 4'b 0001, // index[169] ALERT_HANDLER_ALERT_CAUSE_40
+ 4'b 0001, // index[170] ALERT_HANDLER_LOC_ALERT_REGWEN_0
+ 4'b 0001, // index[171] ALERT_HANDLER_LOC_ALERT_REGWEN_1
+ 4'b 0001, // index[172] ALERT_HANDLER_LOC_ALERT_REGWEN_2
+ 4'b 0001, // index[173] ALERT_HANDLER_LOC_ALERT_REGWEN_3
+ 4'b 0001, // index[174] ALERT_HANDLER_LOC_ALERT_REGWEN_4
+ 4'b 0001, // index[175] ALERT_HANDLER_LOC_ALERT_EN_0
+ 4'b 0001, // index[176] ALERT_HANDLER_LOC_ALERT_EN_1
+ 4'b 0001, // index[177] ALERT_HANDLER_LOC_ALERT_EN_2
+ 4'b 0001, // index[178] ALERT_HANDLER_LOC_ALERT_EN_3
+ 4'b 0001, // index[179] ALERT_HANDLER_LOC_ALERT_EN_4
+ 4'b 0001, // index[180] ALERT_HANDLER_LOC_ALERT_CLASS_0
+ 4'b 0001, // index[181] ALERT_HANDLER_LOC_ALERT_CLASS_1
+ 4'b 0001, // index[182] ALERT_HANDLER_LOC_ALERT_CLASS_2
+ 4'b 0001, // index[183] ALERT_HANDLER_LOC_ALERT_CLASS_3
+ 4'b 0001, // index[184] ALERT_HANDLER_LOC_ALERT_CLASS_4
+ 4'b 0001, // index[185] ALERT_HANDLER_LOC_ALERT_CAUSE_0
+ 4'b 0001, // index[186] ALERT_HANDLER_LOC_ALERT_CAUSE_1
+ 4'b 0001, // index[187] ALERT_HANDLER_LOC_ALERT_CAUSE_2
+ 4'b 0001, // index[188] ALERT_HANDLER_LOC_ALERT_CAUSE_3
+ 4'b 0001, // index[189] ALERT_HANDLER_LOC_ALERT_CAUSE_4
+ 4'b 0001, // index[190] ALERT_HANDLER_CLASSA_REGWEN
+ 4'b 0011, // index[191] ALERT_HANDLER_CLASSA_CTRL
+ 4'b 0001, // index[192] ALERT_HANDLER_CLASSA_CLR_REGWEN
+ 4'b 0001, // index[193] ALERT_HANDLER_CLASSA_CLR
+ 4'b 0011, // index[194] ALERT_HANDLER_CLASSA_ACCUM_CNT
+ 4'b 0011, // index[195] ALERT_HANDLER_CLASSA_ACCUM_THRESH
+ 4'b 1111, // index[196] ALERT_HANDLER_CLASSA_TIMEOUT_CYC
+ 4'b 1111, // index[197] ALERT_HANDLER_CLASSA_PHASE0_CYC
+ 4'b 1111, // index[198] ALERT_HANDLER_CLASSA_PHASE1_CYC
+ 4'b 1111, // index[199] ALERT_HANDLER_CLASSA_PHASE2_CYC
+ 4'b 1111, // index[200] ALERT_HANDLER_CLASSA_PHASE3_CYC
+ 4'b 1111, // index[201] ALERT_HANDLER_CLASSA_ESC_CNT
+ 4'b 0001, // index[202] ALERT_HANDLER_CLASSA_STATE
+ 4'b 0001, // index[203] ALERT_HANDLER_CLASSB_REGWEN
+ 4'b 0011, // index[204] ALERT_HANDLER_CLASSB_CTRL
+ 4'b 0001, // index[205] ALERT_HANDLER_CLASSB_CLR_REGWEN
+ 4'b 0001, // index[206] ALERT_HANDLER_CLASSB_CLR
+ 4'b 0011, // index[207] ALERT_HANDLER_CLASSB_ACCUM_CNT
+ 4'b 0011, // index[208] ALERT_HANDLER_CLASSB_ACCUM_THRESH
+ 4'b 1111, // index[209] ALERT_HANDLER_CLASSB_TIMEOUT_CYC
+ 4'b 1111, // index[210] ALERT_HANDLER_CLASSB_PHASE0_CYC
+ 4'b 1111, // index[211] ALERT_HANDLER_CLASSB_PHASE1_CYC
+ 4'b 1111, // index[212] ALERT_HANDLER_CLASSB_PHASE2_CYC
+ 4'b 1111, // index[213] ALERT_HANDLER_CLASSB_PHASE3_CYC
+ 4'b 1111, // index[214] ALERT_HANDLER_CLASSB_ESC_CNT
+ 4'b 0001, // index[215] ALERT_HANDLER_CLASSB_STATE
+ 4'b 0001, // index[216] ALERT_HANDLER_CLASSC_REGWEN
+ 4'b 0011, // index[217] ALERT_HANDLER_CLASSC_CTRL
+ 4'b 0001, // index[218] ALERT_HANDLER_CLASSC_CLR_REGWEN
+ 4'b 0001, // index[219] ALERT_HANDLER_CLASSC_CLR
+ 4'b 0011, // index[220] ALERT_HANDLER_CLASSC_ACCUM_CNT
+ 4'b 0011, // index[221] ALERT_HANDLER_CLASSC_ACCUM_THRESH
+ 4'b 1111, // index[222] ALERT_HANDLER_CLASSC_TIMEOUT_CYC
+ 4'b 1111, // index[223] ALERT_HANDLER_CLASSC_PHASE0_CYC
+ 4'b 1111, // index[224] ALERT_HANDLER_CLASSC_PHASE1_CYC
+ 4'b 1111, // index[225] ALERT_HANDLER_CLASSC_PHASE2_CYC
+ 4'b 1111, // index[226] ALERT_HANDLER_CLASSC_PHASE3_CYC
+ 4'b 1111, // index[227] ALERT_HANDLER_CLASSC_ESC_CNT
+ 4'b 0001, // index[228] ALERT_HANDLER_CLASSC_STATE
+ 4'b 0001, // index[229] ALERT_HANDLER_CLASSD_REGWEN
+ 4'b 0011, // index[230] ALERT_HANDLER_CLASSD_CTRL
+ 4'b 0001, // index[231] ALERT_HANDLER_CLASSD_CLR_REGWEN
+ 4'b 0001, // index[232] ALERT_HANDLER_CLASSD_CLR
+ 4'b 0011, // index[233] ALERT_HANDLER_CLASSD_ACCUM_CNT
+ 4'b 0011, // index[234] ALERT_HANDLER_CLASSD_ACCUM_THRESH
+ 4'b 1111, // index[235] ALERT_HANDLER_CLASSD_TIMEOUT_CYC
+ 4'b 1111, // index[236] ALERT_HANDLER_CLASSD_PHASE0_CYC
+ 4'b 1111, // index[237] ALERT_HANDLER_CLASSD_PHASE1_CYC
+ 4'b 1111, // index[238] ALERT_HANDLER_CLASSD_PHASE2_CYC
+ 4'b 1111, // index[239] ALERT_HANDLER_CLASSD_PHASE3_CYC
+ 4'b 1111, // index[240] ALERT_HANDLER_CLASSD_ESC_CNT
+ 4'b 0001 // index[241] ALERT_HANDLER_CLASSD_STATE
};
endpackage
diff --git a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
index 7e1e635..7391a1d 100644
--- a/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
+++ b/hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv
@@ -265,6 +265,9 @@
logic alert_regwen_39_qs;
logic alert_regwen_39_wd;
logic alert_regwen_39_we;
+ logic alert_regwen_40_qs;
+ logic alert_regwen_40_wd;
+ logic alert_regwen_40_we;
logic alert_en_0_qs;
logic alert_en_0_wd;
logic alert_en_0_we;
@@ -385,6 +388,9 @@
logic alert_en_39_qs;
logic alert_en_39_wd;
logic alert_en_39_we;
+ logic alert_en_40_qs;
+ logic alert_en_40_wd;
+ logic alert_en_40_we;
logic [1:0] alert_class_0_qs;
logic [1:0] alert_class_0_wd;
logic alert_class_0_we;
@@ -505,6 +511,9 @@
logic [1:0] alert_class_39_qs;
logic [1:0] alert_class_39_wd;
logic alert_class_39_we;
+ logic [1:0] alert_class_40_qs;
+ logic [1:0] alert_class_40_wd;
+ logic alert_class_40_we;
logic alert_cause_0_qs;
logic alert_cause_0_wd;
logic alert_cause_0_we;
@@ -625,6 +634,9 @@
logic alert_cause_39_qs;
logic alert_cause_39_wd;
logic alert_cause_39_we;
+ logic alert_cause_40_qs;
+ logic alert_cause_40_wd;
+ logic alert_cause_40_we;
logic loc_alert_regwen_0_qs;
logic loc_alert_regwen_0_wd;
logic loc_alert_regwen_0_we;
@@ -2371,6 +2383,33 @@
.qs (alert_regwen_39_qs)
);
+ // Subregister 40 of Multireg alert_regwen
+ // R[alert_regwen_40]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W0C"),
+ .RESVAL (1'h1)
+ ) u_alert_regwen_40 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_regwen_40_we),
+ .wd (alert_regwen_40_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_regwen[40].q),
+
+ // to register interface (read)
+ .qs (alert_regwen_40_qs)
+ );
+
// Subregister 0 of Multireg alert_en
@@ -3453,6 +3492,33 @@
.qs (alert_en_39_qs)
);
+ // Subregister 40 of Multireg alert_en
+ // R[alert_en_40]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_alert_en_40 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_en_40_we & alert_regwen_40_qs),
+ .wd (alert_en_40_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_en[40].q),
+
+ // to register interface (read)
+ .qs (alert_en_40_qs)
+ );
+
// Subregister 0 of Multireg alert_class
@@ -4535,6 +4601,33 @@
.qs (alert_class_39_qs)
);
+ // Subregister 40 of Multireg alert_class
+ // R[alert_class_40]: V(False)
+
+ prim_subreg #(
+ .DW (2),
+ .SWACCESS("RW"),
+ .RESVAL (2'h0)
+ ) u_alert_class_40 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_class_40_we & alert_regwen_40_qs),
+ .wd (alert_class_40_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_class[40].q),
+
+ // to register interface (read)
+ .qs (alert_class_40_qs)
+ );
+
// Subregister 0 of Multireg alert_cause
@@ -5617,6 +5710,33 @@
.qs (alert_cause_39_qs)
);
+ // Subregister 40 of Multireg alert_cause
+ // R[alert_cause_40]: V(False)
+
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_alert_cause_40 (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (alert_cause_40_we),
+ .wd (alert_cause_40_wd),
+
+ // from internal hardware
+ .de (hw2reg.alert_cause[40].de),
+ .d (hw2reg.alert_cause[40].d),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.alert_cause[40].q),
+
+ // to register interface (read)
+ .qs (alert_cause_40_qs)
+ );
+
// Subregister 0 of Multireg loc_alert_regwen
@@ -8380,7 +8500,7 @@
- logic [237:0] addr_hit;
+ logic [241:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == ALERT_HANDLER_INTR_STATE_OFFSET);
@@ -8429,198 +8549,202 @@
addr_hit[ 43] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_37_OFFSET);
addr_hit[ 44] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_38_OFFSET);
addr_hit[ 45] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_39_OFFSET);
- addr_hit[ 46] = (reg_addr == ALERT_HANDLER_ALERT_EN_0_OFFSET);
- addr_hit[ 47] = (reg_addr == ALERT_HANDLER_ALERT_EN_1_OFFSET);
- addr_hit[ 48] = (reg_addr == ALERT_HANDLER_ALERT_EN_2_OFFSET);
- addr_hit[ 49] = (reg_addr == ALERT_HANDLER_ALERT_EN_3_OFFSET);
- addr_hit[ 50] = (reg_addr == ALERT_HANDLER_ALERT_EN_4_OFFSET);
- addr_hit[ 51] = (reg_addr == ALERT_HANDLER_ALERT_EN_5_OFFSET);
- addr_hit[ 52] = (reg_addr == ALERT_HANDLER_ALERT_EN_6_OFFSET);
- addr_hit[ 53] = (reg_addr == ALERT_HANDLER_ALERT_EN_7_OFFSET);
- addr_hit[ 54] = (reg_addr == ALERT_HANDLER_ALERT_EN_8_OFFSET);
- addr_hit[ 55] = (reg_addr == ALERT_HANDLER_ALERT_EN_9_OFFSET);
- addr_hit[ 56] = (reg_addr == ALERT_HANDLER_ALERT_EN_10_OFFSET);
- addr_hit[ 57] = (reg_addr == ALERT_HANDLER_ALERT_EN_11_OFFSET);
- addr_hit[ 58] = (reg_addr == ALERT_HANDLER_ALERT_EN_12_OFFSET);
- addr_hit[ 59] = (reg_addr == ALERT_HANDLER_ALERT_EN_13_OFFSET);
- addr_hit[ 60] = (reg_addr == ALERT_HANDLER_ALERT_EN_14_OFFSET);
- addr_hit[ 61] = (reg_addr == ALERT_HANDLER_ALERT_EN_15_OFFSET);
- addr_hit[ 62] = (reg_addr == ALERT_HANDLER_ALERT_EN_16_OFFSET);
- addr_hit[ 63] = (reg_addr == ALERT_HANDLER_ALERT_EN_17_OFFSET);
- addr_hit[ 64] = (reg_addr == ALERT_HANDLER_ALERT_EN_18_OFFSET);
- addr_hit[ 65] = (reg_addr == ALERT_HANDLER_ALERT_EN_19_OFFSET);
- addr_hit[ 66] = (reg_addr == ALERT_HANDLER_ALERT_EN_20_OFFSET);
- addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_EN_21_OFFSET);
- addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_EN_22_OFFSET);
- addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_EN_23_OFFSET);
- addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_EN_24_OFFSET);
- addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_EN_25_OFFSET);
- addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_26_OFFSET);
- addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_27_OFFSET);
- addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_28_OFFSET);
- addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_29_OFFSET);
- addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_30_OFFSET);
- addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_31_OFFSET);
- addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_32_OFFSET);
- addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_33_OFFSET);
- addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_34_OFFSET);
- addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_35_OFFSET);
- addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_36_OFFSET);
- addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_37_OFFSET);
- addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_38_OFFSET);
- addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_39_OFFSET);
- addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_0_OFFSET);
- addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_1_OFFSET);
- addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_2_OFFSET);
- addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_3_OFFSET);
- addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_4_OFFSET);
- addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_5_OFFSET);
- addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_6_OFFSET);
- addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_7_OFFSET);
- addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_8_OFFSET);
- addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_9_OFFSET);
- addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_10_OFFSET);
- addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_11_OFFSET);
- addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_12_OFFSET);
- addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_13_OFFSET);
- addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_14_OFFSET);
- addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_15_OFFSET);
- addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_16_OFFSET);
- addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_17_OFFSET);
- addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_18_OFFSET);
- addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_19_OFFSET);
- addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_20_OFFSET);
- addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_21_OFFSET);
- addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_22_OFFSET);
- addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_23_OFFSET);
- addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_24_OFFSET);
- addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_25_OFFSET);
- addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_26_OFFSET);
- addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_27_OFFSET);
- addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_28_OFFSET);
- addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_29_OFFSET);
- addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_30_OFFSET);
- addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_31_OFFSET);
- addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_32_OFFSET);
- addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_33_OFFSET);
- addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_34_OFFSET);
- addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_35_OFFSET);
- addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_36_OFFSET);
- addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_37_OFFSET);
- addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_38_OFFSET);
- addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_39_OFFSET);
- addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET);
- addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET);
- addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET);
- addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET);
- addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET);
- addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET);
- addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET);
- addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET);
- addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET);
- addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET);
- addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET);
- addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET);
- addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET);
- addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET);
- addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET);
- addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET);
- addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET);
- addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET);
- addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET);
- addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET);
- addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET);
- addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET);
- addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET);
- addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET);
- addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET);
- addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET);
- addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET);
- addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET);
- addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET);
- addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET);
- addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET);
- addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET);
- addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET);
- addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET);
- addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET);
- addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET);
- addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET);
- addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET);
- addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET);
- addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET);
- addr_hit[166] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET);
- addr_hit[167] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET);
- addr_hit[168] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET);
- addr_hit[169] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET);
- addr_hit[170] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET);
- addr_hit[171] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET);
- addr_hit[172] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET);
- addr_hit[173] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET);
- addr_hit[174] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET);
- addr_hit[175] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_4_OFFSET);
- addr_hit[176] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET);
- addr_hit[177] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET);
- addr_hit[178] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET);
- addr_hit[179] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET);
- addr_hit[180] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_4_OFFSET);
- addr_hit[181] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET);
- addr_hit[182] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET);
- addr_hit[183] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET);
- addr_hit[184] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET);
- addr_hit[185] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET);
- addr_hit[186] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET);
- addr_hit[187] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_OFFSET);
- addr_hit[188] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET);
- addr_hit[189] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_OFFSET);
- addr_hit[190] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET);
- addr_hit[191] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET);
- addr_hit[192] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET);
- addr_hit[193] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET);
- addr_hit[194] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET);
- addr_hit[195] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET);
- addr_hit[196] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET);
- addr_hit[197] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET);
- addr_hit[198] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET);
- addr_hit[199] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET);
- addr_hit[200] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_OFFSET);
- addr_hit[201] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET);
- addr_hit[202] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_OFFSET);
- addr_hit[203] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET);
- addr_hit[204] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET);
- addr_hit[205] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET);
- addr_hit[206] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET);
- addr_hit[207] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET);
- addr_hit[208] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET);
- addr_hit[209] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET);
- addr_hit[210] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET);
- addr_hit[211] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET);
- addr_hit[212] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET);
- addr_hit[213] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_OFFSET);
- addr_hit[214] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET);
- addr_hit[215] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_OFFSET);
- addr_hit[216] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET);
- addr_hit[217] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET);
- addr_hit[218] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET);
- addr_hit[219] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET);
- addr_hit[220] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET);
- addr_hit[221] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET);
- addr_hit[222] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET);
- addr_hit[223] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET);
- addr_hit[224] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET);
- addr_hit[225] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET);
- addr_hit[226] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_OFFSET);
- addr_hit[227] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET);
- addr_hit[228] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_OFFSET);
- addr_hit[229] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET);
- addr_hit[230] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET);
- addr_hit[231] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET);
- addr_hit[232] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET);
- addr_hit[233] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET);
- addr_hit[234] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET);
- addr_hit[235] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET);
- addr_hit[236] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET);
- addr_hit[237] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET);
+ addr_hit[ 46] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_40_OFFSET);
+ addr_hit[ 47] = (reg_addr == ALERT_HANDLER_ALERT_EN_0_OFFSET);
+ addr_hit[ 48] = (reg_addr == ALERT_HANDLER_ALERT_EN_1_OFFSET);
+ addr_hit[ 49] = (reg_addr == ALERT_HANDLER_ALERT_EN_2_OFFSET);
+ addr_hit[ 50] = (reg_addr == ALERT_HANDLER_ALERT_EN_3_OFFSET);
+ addr_hit[ 51] = (reg_addr == ALERT_HANDLER_ALERT_EN_4_OFFSET);
+ addr_hit[ 52] = (reg_addr == ALERT_HANDLER_ALERT_EN_5_OFFSET);
+ addr_hit[ 53] = (reg_addr == ALERT_HANDLER_ALERT_EN_6_OFFSET);
+ addr_hit[ 54] = (reg_addr == ALERT_HANDLER_ALERT_EN_7_OFFSET);
+ addr_hit[ 55] = (reg_addr == ALERT_HANDLER_ALERT_EN_8_OFFSET);
+ addr_hit[ 56] = (reg_addr == ALERT_HANDLER_ALERT_EN_9_OFFSET);
+ addr_hit[ 57] = (reg_addr == ALERT_HANDLER_ALERT_EN_10_OFFSET);
+ addr_hit[ 58] = (reg_addr == ALERT_HANDLER_ALERT_EN_11_OFFSET);
+ addr_hit[ 59] = (reg_addr == ALERT_HANDLER_ALERT_EN_12_OFFSET);
+ addr_hit[ 60] = (reg_addr == ALERT_HANDLER_ALERT_EN_13_OFFSET);
+ addr_hit[ 61] = (reg_addr == ALERT_HANDLER_ALERT_EN_14_OFFSET);
+ addr_hit[ 62] = (reg_addr == ALERT_HANDLER_ALERT_EN_15_OFFSET);
+ addr_hit[ 63] = (reg_addr == ALERT_HANDLER_ALERT_EN_16_OFFSET);
+ addr_hit[ 64] = (reg_addr == ALERT_HANDLER_ALERT_EN_17_OFFSET);
+ addr_hit[ 65] = (reg_addr == ALERT_HANDLER_ALERT_EN_18_OFFSET);
+ addr_hit[ 66] = (reg_addr == ALERT_HANDLER_ALERT_EN_19_OFFSET);
+ addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_EN_20_OFFSET);
+ addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_EN_21_OFFSET);
+ addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_EN_22_OFFSET);
+ addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_EN_23_OFFSET);
+ addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_EN_24_OFFSET);
+ addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_25_OFFSET);
+ addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_26_OFFSET);
+ addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_27_OFFSET);
+ addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_28_OFFSET);
+ addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_29_OFFSET);
+ addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_30_OFFSET);
+ addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_31_OFFSET);
+ addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_32_OFFSET);
+ addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_33_OFFSET);
+ addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_34_OFFSET);
+ addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_35_OFFSET);
+ addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_36_OFFSET);
+ addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_37_OFFSET);
+ addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_38_OFFSET);
+ addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_39_OFFSET);
+ addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_40_OFFSET);
+ addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_0_OFFSET);
+ addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_1_OFFSET);
+ addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_2_OFFSET);
+ addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_3_OFFSET);
+ addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_4_OFFSET);
+ addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_5_OFFSET);
+ addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_6_OFFSET);
+ addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_7_OFFSET);
+ addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_8_OFFSET);
+ addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_9_OFFSET);
+ addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_10_OFFSET);
+ addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_11_OFFSET);
+ addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_12_OFFSET);
+ addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_13_OFFSET);
+ addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_14_OFFSET);
+ addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_15_OFFSET);
+ addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_16_OFFSET);
+ addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_17_OFFSET);
+ addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_18_OFFSET);
+ addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_19_OFFSET);
+ addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_20_OFFSET);
+ addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_21_OFFSET);
+ addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_22_OFFSET);
+ addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_23_OFFSET);
+ addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_24_OFFSET);
+ addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_25_OFFSET);
+ addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_26_OFFSET);
+ addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_27_OFFSET);
+ addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_28_OFFSET);
+ addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_29_OFFSET);
+ addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_30_OFFSET);
+ addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_31_OFFSET);
+ addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_32_OFFSET);
+ addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_33_OFFSET);
+ addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_34_OFFSET);
+ addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_35_OFFSET);
+ addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_36_OFFSET);
+ addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_37_OFFSET);
+ addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_38_OFFSET);
+ addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_39_OFFSET);
+ addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_40_OFFSET);
+ addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET);
+ addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET);
+ addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET);
+ addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET);
+ addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET);
+ addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET);
+ addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET);
+ addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET);
+ addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET);
+ addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET);
+ addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET);
+ addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET);
+ addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET);
+ addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET);
+ addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET);
+ addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET);
+ addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET);
+ addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET);
+ addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET);
+ addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET);
+ addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET);
+ addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET);
+ addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET);
+ addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET);
+ addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET);
+ addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET);
+ addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET);
+ addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET);
+ addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET);
+ addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET);
+ addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET);
+ addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET);
+ addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET);
+ addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET);
+ addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET);
+ addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET);
+ addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET);
+ addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET);
+ addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET);
+ addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET);
+ addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET);
+ addr_hit[170] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET);
+ addr_hit[171] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET);
+ addr_hit[172] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET);
+ addr_hit[173] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET);
+ addr_hit[174] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET);
+ addr_hit[175] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_0_OFFSET);
+ addr_hit[176] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_1_OFFSET);
+ addr_hit[177] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_2_OFFSET);
+ addr_hit[178] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_3_OFFSET);
+ addr_hit[179] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_4_OFFSET);
+ addr_hit[180] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_0_OFFSET);
+ addr_hit[181] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_1_OFFSET);
+ addr_hit[182] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_2_OFFSET);
+ addr_hit[183] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_3_OFFSET);
+ addr_hit[184] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_4_OFFSET);
+ addr_hit[185] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET);
+ addr_hit[186] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET);
+ addr_hit[187] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET);
+ addr_hit[188] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET);
+ addr_hit[189] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET);
+ addr_hit[190] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET);
+ addr_hit[191] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_OFFSET);
+ addr_hit[192] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET);
+ addr_hit[193] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_OFFSET);
+ addr_hit[194] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET);
+ addr_hit[195] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET);
+ addr_hit[196] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET);
+ addr_hit[197] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET);
+ addr_hit[198] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET);
+ addr_hit[199] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET);
+ addr_hit[200] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET);
+ addr_hit[201] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET);
+ addr_hit[202] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET);
+ addr_hit[203] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET);
+ addr_hit[204] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_OFFSET);
+ addr_hit[205] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET);
+ addr_hit[206] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_OFFSET);
+ addr_hit[207] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET);
+ addr_hit[208] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET);
+ addr_hit[209] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET);
+ addr_hit[210] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET);
+ addr_hit[211] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET);
+ addr_hit[212] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET);
+ addr_hit[213] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET);
+ addr_hit[214] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET);
+ addr_hit[215] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET);
+ addr_hit[216] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET);
+ addr_hit[217] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_OFFSET);
+ addr_hit[218] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET);
+ addr_hit[219] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_OFFSET);
+ addr_hit[220] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET);
+ addr_hit[221] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET);
+ addr_hit[222] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET);
+ addr_hit[223] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET);
+ addr_hit[224] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET);
+ addr_hit[225] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET);
+ addr_hit[226] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET);
+ addr_hit[227] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET);
+ addr_hit[228] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET);
+ addr_hit[229] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET);
+ addr_hit[230] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_OFFSET);
+ addr_hit[231] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET);
+ addr_hit[232] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_OFFSET);
+ addr_hit[233] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET);
+ addr_hit[234] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET);
+ addr_hit[235] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET);
+ addr_hit[236] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET);
+ addr_hit[237] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET);
+ addr_hit[238] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET);
+ addr_hit[239] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET);
+ addr_hit[240] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET);
+ addr_hit[241] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -8865,7 +8989,11 @@
(addr_hit[234] & (|(ALERT_HANDLER_PERMIT[234] & ~reg_be))) |
(addr_hit[235] & (|(ALERT_HANDLER_PERMIT[235] & ~reg_be))) |
(addr_hit[236] & (|(ALERT_HANDLER_PERMIT[236] & ~reg_be))) |
- (addr_hit[237] & (|(ALERT_HANDLER_PERMIT[237] & ~reg_be)))));
+ (addr_hit[237] & (|(ALERT_HANDLER_PERMIT[237] & ~reg_be))) |
+ (addr_hit[238] & (|(ALERT_HANDLER_PERMIT[238] & ~reg_be))) |
+ (addr_hit[239] & (|(ALERT_HANDLER_PERMIT[239] & ~reg_be))) |
+ (addr_hit[240] & (|(ALERT_HANDLER_PERMIT[240] & ~reg_be))) |
+ (addr_hit[241] & (|(ALERT_HANDLER_PERMIT[241] & ~reg_be)))));
end
assign intr_state_classa_we = addr_hit[0] & reg_we & !reg_error;
@@ -9033,677 +9161,689 @@
assign alert_regwen_39_we = addr_hit[45] & reg_we & !reg_error;
assign alert_regwen_39_wd = reg_wdata[0];
- assign alert_en_0_we = addr_hit[46] & reg_we & !reg_error;
+ assign alert_regwen_40_we = addr_hit[46] & reg_we & !reg_error;
+ assign alert_regwen_40_wd = reg_wdata[0];
+
+ assign alert_en_0_we = addr_hit[47] & reg_we & !reg_error;
assign alert_en_0_wd = reg_wdata[0];
- assign alert_en_1_we = addr_hit[47] & reg_we & !reg_error;
+ assign alert_en_1_we = addr_hit[48] & reg_we & !reg_error;
assign alert_en_1_wd = reg_wdata[0];
- assign alert_en_2_we = addr_hit[48] & reg_we & !reg_error;
+ assign alert_en_2_we = addr_hit[49] & reg_we & !reg_error;
assign alert_en_2_wd = reg_wdata[0];
- assign alert_en_3_we = addr_hit[49] & reg_we & !reg_error;
+ assign alert_en_3_we = addr_hit[50] & reg_we & !reg_error;
assign alert_en_3_wd = reg_wdata[0];
- assign alert_en_4_we = addr_hit[50] & reg_we & !reg_error;
+ assign alert_en_4_we = addr_hit[51] & reg_we & !reg_error;
assign alert_en_4_wd = reg_wdata[0];
- assign alert_en_5_we = addr_hit[51] & reg_we & !reg_error;
+ assign alert_en_5_we = addr_hit[52] & reg_we & !reg_error;
assign alert_en_5_wd = reg_wdata[0];
- assign alert_en_6_we = addr_hit[52] & reg_we & !reg_error;
+ assign alert_en_6_we = addr_hit[53] & reg_we & !reg_error;
assign alert_en_6_wd = reg_wdata[0];
- assign alert_en_7_we = addr_hit[53] & reg_we & !reg_error;
+ assign alert_en_7_we = addr_hit[54] & reg_we & !reg_error;
assign alert_en_7_wd = reg_wdata[0];
- assign alert_en_8_we = addr_hit[54] & reg_we & !reg_error;
+ assign alert_en_8_we = addr_hit[55] & reg_we & !reg_error;
assign alert_en_8_wd = reg_wdata[0];
- assign alert_en_9_we = addr_hit[55] & reg_we & !reg_error;
+ assign alert_en_9_we = addr_hit[56] & reg_we & !reg_error;
assign alert_en_9_wd = reg_wdata[0];
- assign alert_en_10_we = addr_hit[56] & reg_we & !reg_error;
+ assign alert_en_10_we = addr_hit[57] & reg_we & !reg_error;
assign alert_en_10_wd = reg_wdata[0];
- assign alert_en_11_we = addr_hit[57] & reg_we & !reg_error;
+ assign alert_en_11_we = addr_hit[58] & reg_we & !reg_error;
assign alert_en_11_wd = reg_wdata[0];
- assign alert_en_12_we = addr_hit[58] & reg_we & !reg_error;
+ assign alert_en_12_we = addr_hit[59] & reg_we & !reg_error;
assign alert_en_12_wd = reg_wdata[0];
- assign alert_en_13_we = addr_hit[59] & reg_we & !reg_error;
+ assign alert_en_13_we = addr_hit[60] & reg_we & !reg_error;
assign alert_en_13_wd = reg_wdata[0];
- assign alert_en_14_we = addr_hit[60] & reg_we & !reg_error;
+ assign alert_en_14_we = addr_hit[61] & reg_we & !reg_error;
assign alert_en_14_wd = reg_wdata[0];
- assign alert_en_15_we = addr_hit[61] & reg_we & !reg_error;
+ assign alert_en_15_we = addr_hit[62] & reg_we & !reg_error;
assign alert_en_15_wd = reg_wdata[0];
- assign alert_en_16_we = addr_hit[62] & reg_we & !reg_error;
+ assign alert_en_16_we = addr_hit[63] & reg_we & !reg_error;
assign alert_en_16_wd = reg_wdata[0];
- assign alert_en_17_we = addr_hit[63] & reg_we & !reg_error;
+ assign alert_en_17_we = addr_hit[64] & reg_we & !reg_error;
assign alert_en_17_wd = reg_wdata[0];
- assign alert_en_18_we = addr_hit[64] & reg_we & !reg_error;
+ assign alert_en_18_we = addr_hit[65] & reg_we & !reg_error;
assign alert_en_18_wd = reg_wdata[0];
- assign alert_en_19_we = addr_hit[65] & reg_we & !reg_error;
+ assign alert_en_19_we = addr_hit[66] & reg_we & !reg_error;
assign alert_en_19_wd = reg_wdata[0];
- assign alert_en_20_we = addr_hit[66] & reg_we & !reg_error;
+ assign alert_en_20_we = addr_hit[67] & reg_we & !reg_error;
assign alert_en_20_wd = reg_wdata[0];
- assign alert_en_21_we = addr_hit[67] & reg_we & !reg_error;
+ assign alert_en_21_we = addr_hit[68] & reg_we & !reg_error;
assign alert_en_21_wd = reg_wdata[0];
- assign alert_en_22_we = addr_hit[68] & reg_we & !reg_error;
+ assign alert_en_22_we = addr_hit[69] & reg_we & !reg_error;
assign alert_en_22_wd = reg_wdata[0];
- assign alert_en_23_we = addr_hit[69] & reg_we & !reg_error;
+ assign alert_en_23_we = addr_hit[70] & reg_we & !reg_error;
assign alert_en_23_wd = reg_wdata[0];
- assign alert_en_24_we = addr_hit[70] & reg_we & !reg_error;
+ assign alert_en_24_we = addr_hit[71] & reg_we & !reg_error;
assign alert_en_24_wd = reg_wdata[0];
- assign alert_en_25_we = addr_hit[71] & reg_we & !reg_error;
+ assign alert_en_25_we = addr_hit[72] & reg_we & !reg_error;
assign alert_en_25_wd = reg_wdata[0];
- assign alert_en_26_we = addr_hit[72] & reg_we & !reg_error;
+ assign alert_en_26_we = addr_hit[73] & reg_we & !reg_error;
assign alert_en_26_wd = reg_wdata[0];
- assign alert_en_27_we = addr_hit[73] & reg_we & !reg_error;
+ assign alert_en_27_we = addr_hit[74] & reg_we & !reg_error;
assign alert_en_27_wd = reg_wdata[0];
- assign alert_en_28_we = addr_hit[74] & reg_we & !reg_error;
+ assign alert_en_28_we = addr_hit[75] & reg_we & !reg_error;
assign alert_en_28_wd = reg_wdata[0];
- assign alert_en_29_we = addr_hit[75] & reg_we & !reg_error;
+ assign alert_en_29_we = addr_hit[76] & reg_we & !reg_error;
assign alert_en_29_wd = reg_wdata[0];
- assign alert_en_30_we = addr_hit[76] & reg_we & !reg_error;
+ assign alert_en_30_we = addr_hit[77] & reg_we & !reg_error;
assign alert_en_30_wd = reg_wdata[0];
- assign alert_en_31_we = addr_hit[77] & reg_we & !reg_error;
+ assign alert_en_31_we = addr_hit[78] & reg_we & !reg_error;
assign alert_en_31_wd = reg_wdata[0];
- assign alert_en_32_we = addr_hit[78] & reg_we & !reg_error;
+ assign alert_en_32_we = addr_hit[79] & reg_we & !reg_error;
assign alert_en_32_wd = reg_wdata[0];
- assign alert_en_33_we = addr_hit[79] & reg_we & !reg_error;
+ assign alert_en_33_we = addr_hit[80] & reg_we & !reg_error;
assign alert_en_33_wd = reg_wdata[0];
- assign alert_en_34_we = addr_hit[80] & reg_we & !reg_error;
+ assign alert_en_34_we = addr_hit[81] & reg_we & !reg_error;
assign alert_en_34_wd = reg_wdata[0];
- assign alert_en_35_we = addr_hit[81] & reg_we & !reg_error;
+ assign alert_en_35_we = addr_hit[82] & reg_we & !reg_error;
assign alert_en_35_wd = reg_wdata[0];
- assign alert_en_36_we = addr_hit[82] & reg_we & !reg_error;
+ assign alert_en_36_we = addr_hit[83] & reg_we & !reg_error;
assign alert_en_36_wd = reg_wdata[0];
- assign alert_en_37_we = addr_hit[83] & reg_we & !reg_error;
+ assign alert_en_37_we = addr_hit[84] & reg_we & !reg_error;
assign alert_en_37_wd = reg_wdata[0];
- assign alert_en_38_we = addr_hit[84] & reg_we & !reg_error;
+ assign alert_en_38_we = addr_hit[85] & reg_we & !reg_error;
assign alert_en_38_wd = reg_wdata[0];
- assign alert_en_39_we = addr_hit[85] & reg_we & !reg_error;
+ assign alert_en_39_we = addr_hit[86] & reg_we & !reg_error;
assign alert_en_39_wd = reg_wdata[0];
- assign alert_class_0_we = addr_hit[86] & reg_we & !reg_error;
+ assign alert_en_40_we = addr_hit[87] & reg_we & !reg_error;
+ assign alert_en_40_wd = reg_wdata[0];
+
+ assign alert_class_0_we = addr_hit[88] & reg_we & !reg_error;
assign alert_class_0_wd = reg_wdata[1:0];
- assign alert_class_1_we = addr_hit[87] & reg_we & !reg_error;
+ assign alert_class_1_we = addr_hit[89] & reg_we & !reg_error;
assign alert_class_1_wd = reg_wdata[1:0];
- assign alert_class_2_we = addr_hit[88] & reg_we & !reg_error;
+ assign alert_class_2_we = addr_hit[90] & reg_we & !reg_error;
assign alert_class_2_wd = reg_wdata[1:0];
- assign alert_class_3_we = addr_hit[89] & reg_we & !reg_error;
+ assign alert_class_3_we = addr_hit[91] & reg_we & !reg_error;
assign alert_class_3_wd = reg_wdata[1:0];
- assign alert_class_4_we = addr_hit[90] & reg_we & !reg_error;
+ assign alert_class_4_we = addr_hit[92] & reg_we & !reg_error;
assign alert_class_4_wd = reg_wdata[1:0];
- assign alert_class_5_we = addr_hit[91] & reg_we & !reg_error;
+ assign alert_class_5_we = addr_hit[93] & reg_we & !reg_error;
assign alert_class_5_wd = reg_wdata[1:0];
- assign alert_class_6_we = addr_hit[92] & reg_we & !reg_error;
+ assign alert_class_6_we = addr_hit[94] & reg_we & !reg_error;
assign alert_class_6_wd = reg_wdata[1:0];
- assign alert_class_7_we = addr_hit[93] & reg_we & !reg_error;
+ assign alert_class_7_we = addr_hit[95] & reg_we & !reg_error;
assign alert_class_7_wd = reg_wdata[1:0];
- assign alert_class_8_we = addr_hit[94] & reg_we & !reg_error;
+ assign alert_class_8_we = addr_hit[96] & reg_we & !reg_error;
assign alert_class_8_wd = reg_wdata[1:0];
- assign alert_class_9_we = addr_hit[95] & reg_we & !reg_error;
+ assign alert_class_9_we = addr_hit[97] & reg_we & !reg_error;
assign alert_class_9_wd = reg_wdata[1:0];
- assign alert_class_10_we = addr_hit[96] & reg_we & !reg_error;
+ assign alert_class_10_we = addr_hit[98] & reg_we & !reg_error;
assign alert_class_10_wd = reg_wdata[1:0];
- assign alert_class_11_we = addr_hit[97] & reg_we & !reg_error;
+ assign alert_class_11_we = addr_hit[99] & reg_we & !reg_error;
assign alert_class_11_wd = reg_wdata[1:0];
- assign alert_class_12_we = addr_hit[98] & reg_we & !reg_error;
+ assign alert_class_12_we = addr_hit[100] & reg_we & !reg_error;
assign alert_class_12_wd = reg_wdata[1:0];
- assign alert_class_13_we = addr_hit[99] & reg_we & !reg_error;
+ assign alert_class_13_we = addr_hit[101] & reg_we & !reg_error;
assign alert_class_13_wd = reg_wdata[1:0];
- assign alert_class_14_we = addr_hit[100] & reg_we & !reg_error;
+ assign alert_class_14_we = addr_hit[102] & reg_we & !reg_error;
assign alert_class_14_wd = reg_wdata[1:0];
- assign alert_class_15_we = addr_hit[101] & reg_we & !reg_error;
+ assign alert_class_15_we = addr_hit[103] & reg_we & !reg_error;
assign alert_class_15_wd = reg_wdata[1:0];
- assign alert_class_16_we = addr_hit[102] & reg_we & !reg_error;
+ assign alert_class_16_we = addr_hit[104] & reg_we & !reg_error;
assign alert_class_16_wd = reg_wdata[1:0];
- assign alert_class_17_we = addr_hit[103] & reg_we & !reg_error;
+ assign alert_class_17_we = addr_hit[105] & reg_we & !reg_error;
assign alert_class_17_wd = reg_wdata[1:0];
- assign alert_class_18_we = addr_hit[104] & reg_we & !reg_error;
+ assign alert_class_18_we = addr_hit[106] & reg_we & !reg_error;
assign alert_class_18_wd = reg_wdata[1:0];
- assign alert_class_19_we = addr_hit[105] & reg_we & !reg_error;
+ assign alert_class_19_we = addr_hit[107] & reg_we & !reg_error;
assign alert_class_19_wd = reg_wdata[1:0];
- assign alert_class_20_we = addr_hit[106] & reg_we & !reg_error;
+ assign alert_class_20_we = addr_hit[108] & reg_we & !reg_error;
assign alert_class_20_wd = reg_wdata[1:0];
- assign alert_class_21_we = addr_hit[107] & reg_we & !reg_error;
+ assign alert_class_21_we = addr_hit[109] & reg_we & !reg_error;
assign alert_class_21_wd = reg_wdata[1:0];
- assign alert_class_22_we = addr_hit[108] & reg_we & !reg_error;
+ assign alert_class_22_we = addr_hit[110] & reg_we & !reg_error;
assign alert_class_22_wd = reg_wdata[1:0];
- assign alert_class_23_we = addr_hit[109] & reg_we & !reg_error;
+ assign alert_class_23_we = addr_hit[111] & reg_we & !reg_error;
assign alert_class_23_wd = reg_wdata[1:0];
- assign alert_class_24_we = addr_hit[110] & reg_we & !reg_error;
+ assign alert_class_24_we = addr_hit[112] & reg_we & !reg_error;
assign alert_class_24_wd = reg_wdata[1:0];
- assign alert_class_25_we = addr_hit[111] & reg_we & !reg_error;
+ assign alert_class_25_we = addr_hit[113] & reg_we & !reg_error;
assign alert_class_25_wd = reg_wdata[1:0];
- assign alert_class_26_we = addr_hit[112] & reg_we & !reg_error;
+ assign alert_class_26_we = addr_hit[114] & reg_we & !reg_error;
assign alert_class_26_wd = reg_wdata[1:0];
- assign alert_class_27_we = addr_hit[113] & reg_we & !reg_error;
+ assign alert_class_27_we = addr_hit[115] & reg_we & !reg_error;
assign alert_class_27_wd = reg_wdata[1:0];
- assign alert_class_28_we = addr_hit[114] & reg_we & !reg_error;
+ assign alert_class_28_we = addr_hit[116] & reg_we & !reg_error;
assign alert_class_28_wd = reg_wdata[1:0];
- assign alert_class_29_we = addr_hit[115] & reg_we & !reg_error;
+ assign alert_class_29_we = addr_hit[117] & reg_we & !reg_error;
assign alert_class_29_wd = reg_wdata[1:0];
- assign alert_class_30_we = addr_hit[116] & reg_we & !reg_error;
+ assign alert_class_30_we = addr_hit[118] & reg_we & !reg_error;
assign alert_class_30_wd = reg_wdata[1:0];
- assign alert_class_31_we = addr_hit[117] & reg_we & !reg_error;
+ assign alert_class_31_we = addr_hit[119] & reg_we & !reg_error;
assign alert_class_31_wd = reg_wdata[1:0];
- assign alert_class_32_we = addr_hit[118] & reg_we & !reg_error;
+ assign alert_class_32_we = addr_hit[120] & reg_we & !reg_error;
assign alert_class_32_wd = reg_wdata[1:0];
- assign alert_class_33_we = addr_hit[119] & reg_we & !reg_error;
+ assign alert_class_33_we = addr_hit[121] & reg_we & !reg_error;
assign alert_class_33_wd = reg_wdata[1:0];
- assign alert_class_34_we = addr_hit[120] & reg_we & !reg_error;
+ assign alert_class_34_we = addr_hit[122] & reg_we & !reg_error;
assign alert_class_34_wd = reg_wdata[1:0];
- assign alert_class_35_we = addr_hit[121] & reg_we & !reg_error;
+ assign alert_class_35_we = addr_hit[123] & reg_we & !reg_error;
assign alert_class_35_wd = reg_wdata[1:0];
- assign alert_class_36_we = addr_hit[122] & reg_we & !reg_error;
+ assign alert_class_36_we = addr_hit[124] & reg_we & !reg_error;
assign alert_class_36_wd = reg_wdata[1:0];
- assign alert_class_37_we = addr_hit[123] & reg_we & !reg_error;
+ assign alert_class_37_we = addr_hit[125] & reg_we & !reg_error;
assign alert_class_37_wd = reg_wdata[1:0];
- assign alert_class_38_we = addr_hit[124] & reg_we & !reg_error;
+ assign alert_class_38_we = addr_hit[126] & reg_we & !reg_error;
assign alert_class_38_wd = reg_wdata[1:0];
- assign alert_class_39_we = addr_hit[125] & reg_we & !reg_error;
+ assign alert_class_39_we = addr_hit[127] & reg_we & !reg_error;
assign alert_class_39_wd = reg_wdata[1:0];
- assign alert_cause_0_we = addr_hit[126] & reg_we & !reg_error;
+ assign alert_class_40_we = addr_hit[128] & reg_we & !reg_error;
+ assign alert_class_40_wd = reg_wdata[1:0];
+
+ assign alert_cause_0_we = addr_hit[129] & reg_we & !reg_error;
assign alert_cause_0_wd = reg_wdata[0];
- assign alert_cause_1_we = addr_hit[127] & reg_we & !reg_error;
+ assign alert_cause_1_we = addr_hit[130] & reg_we & !reg_error;
assign alert_cause_1_wd = reg_wdata[0];
- assign alert_cause_2_we = addr_hit[128] & reg_we & !reg_error;
+ assign alert_cause_2_we = addr_hit[131] & reg_we & !reg_error;
assign alert_cause_2_wd = reg_wdata[0];
- assign alert_cause_3_we = addr_hit[129] & reg_we & !reg_error;
+ assign alert_cause_3_we = addr_hit[132] & reg_we & !reg_error;
assign alert_cause_3_wd = reg_wdata[0];
- assign alert_cause_4_we = addr_hit[130] & reg_we & !reg_error;
+ assign alert_cause_4_we = addr_hit[133] & reg_we & !reg_error;
assign alert_cause_4_wd = reg_wdata[0];
- assign alert_cause_5_we = addr_hit[131] & reg_we & !reg_error;
+ assign alert_cause_5_we = addr_hit[134] & reg_we & !reg_error;
assign alert_cause_5_wd = reg_wdata[0];
- assign alert_cause_6_we = addr_hit[132] & reg_we & !reg_error;
+ assign alert_cause_6_we = addr_hit[135] & reg_we & !reg_error;
assign alert_cause_6_wd = reg_wdata[0];
- assign alert_cause_7_we = addr_hit[133] & reg_we & !reg_error;
+ assign alert_cause_7_we = addr_hit[136] & reg_we & !reg_error;
assign alert_cause_7_wd = reg_wdata[0];
- assign alert_cause_8_we = addr_hit[134] & reg_we & !reg_error;
+ assign alert_cause_8_we = addr_hit[137] & reg_we & !reg_error;
assign alert_cause_8_wd = reg_wdata[0];
- assign alert_cause_9_we = addr_hit[135] & reg_we & !reg_error;
+ assign alert_cause_9_we = addr_hit[138] & reg_we & !reg_error;
assign alert_cause_9_wd = reg_wdata[0];
- assign alert_cause_10_we = addr_hit[136] & reg_we & !reg_error;
+ assign alert_cause_10_we = addr_hit[139] & reg_we & !reg_error;
assign alert_cause_10_wd = reg_wdata[0];
- assign alert_cause_11_we = addr_hit[137] & reg_we & !reg_error;
+ assign alert_cause_11_we = addr_hit[140] & reg_we & !reg_error;
assign alert_cause_11_wd = reg_wdata[0];
- assign alert_cause_12_we = addr_hit[138] & reg_we & !reg_error;
+ assign alert_cause_12_we = addr_hit[141] & reg_we & !reg_error;
assign alert_cause_12_wd = reg_wdata[0];
- assign alert_cause_13_we = addr_hit[139] & reg_we & !reg_error;
+ assign alert_cause_13_we = addr_hit[142] & reg_we & !reg_error;
assign alert_cause_13_wd = reg_wdata[0];
- assign alert_cause_14_we = addr_hit[140] & reg_we & !reg_error;
+ assign alert_cause_14_we = addr_hit[143] & reg_we & !reg_error;
assign alert_cause_14_wd = reg_wdata[0];
- assign alert_cause_15_we = addr_hit[141] & reg_we & !reg_error;
+ assign alert_cause_15_we = addr_hit[144] & reg_we & !reg_error;
assign alert_cause_15_wd = reg_wdata[0];
- assign alert_cause_16_we = addr_hit[142] & reg_we & !reg_error;
+ assign alert_cause_16_we = addr_hit[145] & reg_we & !reg_error;
assign alert_cause_16_wd = reg_wdata[0];
- assign alert_cause_17_we = addr_hit[143] & reg_we & !reg_error;
+ assign alert_cause_17_we = addr_hit[146] & reg_we & !reg_error;
assign alert_cause_17_wd = reg_wdata[0];
- assign alert_cause_18_we = addr_hit[144] & reg_we & !reg_error;
+ assign alert_cause_18_we = addr_hit[147] & reg_we & !reg_error;
assign alert_cause_18_wd = reg_wdata[0];
- assign alert_cause_19_we = addr_hit[145] & reg_we & !reg_error;
+ assign alert_cause_19_we = addr_hit[148] & reg_we & !reg_error;
assign alert_cause_19_wd = reg_wdata[0];
- assign alert_cause_20_we = addr_hit[146] & reg_we & !reg_error;
+ assign alert_cause_20_we = addr_hit[149] & reg_we & !reg_error;
assign alert_cause_20_wd = reg_wdata[0];
- assign alert_cause_21_we = addr_hit[147] & reg_we & !reg_error;
+ assign alert_cause_21_we = addr_hit[150] & reg_we & !reg_error;
assign alert_cause_21_wd = reg_wdata[0];
- assign alert_cause_22_we = addr_hit[148] & reg_we & !reg_error;
+ assign alert_cause_22_we = addr_hit[151] & reg_we & !reg_error;
assign alert_cause_22_wd = reg_wdata[0];
- assign alert_cause_23_we = addr_hit[149] & reg_we & !reg_error;
+ assign alert_cause_23_we = addr_hit[152] & reg_we & !reg_error;
assign alert_cause_23_wd = reg_wdata[0];
- assign alert_cause_24_we = addr_hit[150] & reg_we & !reg_error;
+ assign alert_cause_24_we = addr_hit[153] & reg_we & !reg_error;
assign alert_cause_24_wd = reg_wdata[0];
- assign alert_cause_25_we = addr_hit[151] & reg_we & !reg_error;
+ assign alert_cause_25_we = addr_hit[154] & reg_we & !reg_error;
assign alert_cause_25_wd = reg_wdata[0];
- assign alert_cause_26_we = addr_hit[152] & reg_we & !reg_error;
+ assign alert_cause_26_we = addr_hit[155] & reg_we & !reg_error;
assign alert_cause_26_wd = reg_wdata[0];
- assign alert_cause_27_we = addr_hit[153] & reg_we & !reg_error;
+ assign alert_cause_27_we = addr_hit[156] & reg_we & !reg_error;
assign alert_cause_27_wd = reg_wdata[0];
- assign alert_cause_28_we = addr_hit[154] & reg_we & !reg_error;
+ assign alert_cause_28_we = addr_hit[157] & reg_we & !reg_error;
assign alert_cause_28_wd = reg_wdata[0];
- assign alert_cause_29_we = addr_hit[155] & reg_we & !reg_error;
+ assign alert_cause_29_we = addr_hit[158] & reg_we & !reg_error;
assign alert_cause_29_wd = reg_wdata[0];
- assign alert_cause_30_we = addr_hit[156] & reg_we & !reg_error;
+ assign alert_cause_30_we = addr_hit[159] & reg_we & !reg_error;
assign alert_cause_30_wd = reg_wdata[0];
- assign alert_cause_31_we = addr_hit[157] & reg_we & !reg_error;
+ assign alert_cause_31_we = addr_hit[160] & reg_we & !reg_error;
assign alert_cause_31_wd = reg_wdata[0];
- assign alert_cause_32_we = addr_hit[158] & reg_we & !reg_error;
+ assign alert_cause_32_we = addr_hit[161] & reg_we & !reg_error;
assign alert_cause_32_wd = reg_wdata[0];
- assign alert_cause_33_we = addr_hit[159] & reg_we & !reg_error;
+ assign alert_cause_33_we = addr_hit[162] & reg_we & !reg_error;
assign alert_cause_33_wd = reg_wdata[0];
- assign alert_cause_34_we = addr_hit[160] & reg_we & !reg_error;
+ assign alert_cause_34_we = addr_hit[163] & reg_we & !reg_error;
assign alert_cause_34_wd = reg_wdata[0];
- assign alert_cause_35_we = addr_hit[161] & reg_we & !reg_error;
+ assign alert_cause_35_we = addr_hit[164] & reg_we & !reg_error;
assign alert_cause_35_wd = reg_wdata[0];
- assign alert_cause_36_we = addr_hit[162] & reg_we & !reg_error;
+ assign alert_cause_36_we = addr_hit[165] & reg_we & !reg_error;
assign alert_cause_36_wd = reg_wdata[0];
- assign alert_cause_37_we = addr_hit[163] & reg_we & !reg_error;
+ assign alert_cause_37_we = addr_hit[166] & reg_we & !reg_error;
assign alert_cause_37_wd = reg_wdata[0];
- assign alert_cause_38_we = addr_hit[164] & reg_we & !reg_error;
+ assign alert_cause_38_we = addr_hit[167] & reg_we & !reg_error;
assign alert_cause_38_wd = reg_wdata[0];
- assign alert_cause_39_we = addr_hit[165] & reg_we & !reg_error;
+ assign alert_cause_39_we = addr_hit[168] & reg_we & !reg_error;
assign alert_cause_39_wd = reg_wdata[0];
- assign loc_alert_regwen_0_we = addr_hit[166] & reg_we & !reg_error;
+ assign alert_cause_40_we = addr_hit[169] & reg_we & !reg_error;
+ assign alert_cause_40_wd = reg_wdata[0];
+
+ assign loc_alert_regwen_0_we = addr_hit[170] & reg_we & !reg_error;
assign loc_alert_regwen_0_wd = reg_wdata[0];
- assign loc_alert_regwen_1_we = addr_hit[167] & reg_we & !reg_error;
+ assign loc_alert_regwen_1_we = addr_hit[171] & reg_we & !reg_error;
assign loc_alert_regwen_1_wd = reg_wdata[0];
- assign loc_alert_regwen_2_we = addr_hit[168] & reg_we & !reg_error;
+ assign loc_alert_regwen_2_we = addr_hit[172] & reg_we & !reg_error;
assign loc_alert_regwen_2_wd = reg_wdata[0];
- assign loc_alert_regwen_3_we = addr_hit[169] & reg_we & !reg_error;
+ assign loc_alert_regwen_3_we = addr_hit[173] & reg_we & !reg_error;
assign loc_alert_regwen_3_wd = reg_wdata[0];
- assign loc_alert_regwen_4_we = addr_hit[170] & reg_we & !reg_error;
+ assign loc_alert_regwen_4_we = addr_hit[174] & reg_we & !reg_error;
assign loc_alert_regwen_4_wd = reg_wdata[0];
- assign loc_alert_en_0_we = addr_hit[171] & reg_we & !reg_error;
+ assign loc_alert_en_0_we = addr_hit[175] & reg_we & !reg_error;
assign loc_alert_en_0_wd = reg_wdata[0];
- assign loc_alert_en_1_we = addr_hit[172] & reg_we & !reg_error;
+ assign loc_alert_en_1_we = addr_hit[176] & reg_we & !reg_error;
assign loc_alert_en_1_wd = reg_wdata[0];
- assign loc_alert_en_2_we = addr_hit[173] & reg_we & !reg_error;
+ assign loc_alert_en_2_we = addr_hit[177] & reg_we & !reg_error;
assign loc_alert_en_2_wd = reg_wdata[0];
- assign loc_alert_en_3_we = addr_hit[174] & reg_we & !reg_error;
+ assign loc_alert_en_3_we = addr_hit[178] & reg_we & !reg_error;
assign loc_alert_en_3_wd = reg_wdata[0];
- assign loc_alert_en_4_we = addr_hit[175] & reg_we & !reg_error;
+ assign loc_alert_en_4_we = addr_hit[179] & reg_we & !reg_error;
assign loc_alert_en_4_wd = reg_wdata[0];
- assign loc_alert_class_0_we = addr_hit[176] & reg_we & !reg_error;
+ assign loc_alert_class_0_we = addr_hit[180] & reg_we & !reg_error;
assign loc_alert_class_0_wd = reg_wdata[1:0];
- assign loc_alert_class_1_we = addr_hit[177] & reg_we & !reg_error;
+ assign loc_alert_class_1_we = addr_hit[181] & reg_we & !reg_error;
assign loc_alert_class_1_wd = reg_wdata[1:0];
- assign loc_alert_class_2_we = addr_hit[178] & reg_we & !reg_error;
+ assign loc_alert_class_2_we = addr_hit[182] & reg_we & !reg_error;
assign loc_alert_class_2_wd = reg_wdata[1:0];
- assign loc_alert_class_3_we = addr_hit[179] & reg_we & !reg_error;
+ assign loc_alert_class_3_we = addr_hit[183] & reg_we & !reg_error;
assign loc_alert_class_3_wd = reg_wdata[1:0];
- assign loc_alert_class_4_we = addr_hit[180] & reg_we & !reg_error;
+ assign loc_alert_class_4_we = addr_hit[184] & reg_we & !reg_error;
assign loc_alert_class_4_wd = reg_wdata[1:0];
- assign loc_alert_cause_0_we = addr_hit[181] & reg_we & !reg_error;
+ assign loc_alert_cause_0_we = addr_hit[185] & reg_we & !reg_error;
assign loc_alert_cause_0_wd = reg_wdata[0];
- assign loc_alert_cause_1_we = addr_hit[182] & reg_we & !reg_error;
+ assign loc_alert_cause_1_we = addr_hit[186] & reg_we & !reg_error;
assign loc_alert_cause_1_wd = reg_wdata[0];
- assign loc_alert_cause_2_we = addr_hit[183] & reg_we & !reg_error;
+ assign loc_alert_cause_2_we = addr_hit[187] & reg_we & !reg_error;
assign loc_alert_cause_2_wd = reg_wdata[0];
- assign loc_alert_cause_3_we = addr_hit[184] & reg_we & !reg_error;
+ assign loc_alert_cause_3_we = addr_hit[188] & reg_we & !reg_error;
assign loc_alert_cause_3_wd = reg_wdata[0];
- assign loc_alert_cause_4_we = addr_hit[185] & reg_we & !reg_error;
+ assign loc_alert_cause_4_we = addr_hit[189] & reg_we & !reg_error;
assign loc_alert_cause_4_wd = reg_wdata[0];
- assign classa_regwen_we = addr_hit[186] & reg_we & !reg_error;
+ assign classa_regwen_we = addr_hit[190] & reg_we & !reg_error;
assign classa_regwen_wd = reg_wdata[0];
- assign classa_ctrl_en_we = addr_hit[187] & reg_we & !reg_error;
+ assign classa_ctrl_en_we = addr_hit[191] & reg_we & !reg_error;
assign classa_ctrl_en_wd = reg_wdata[0];
- assign classa_ctrl_lock_we = addr_hit[187] & reg_we & !reg_error;
+ assign classa_ctrl_lock_we = addr_hit[191] & reg_we & !reg_error;
assign classa_ctrl_lock_wd = reg_wdata[1];
- assign classa_ctrl_en_e0_we = addr_hit[187] & reg_we & !reg_error;
+ assign classa_ctrl_en_e0_we = addr_hit[191] & reg_we & !reg_error;
assign classa_ctrl_en_e0_wd = reg_wdata[2];
- assign classa_ctrl_en_e1_we = addr_hit[187] & reg_we & !reg_error;
+ assign classa_ctrl_en_e1_we = addr_hit[191] & reg_we & !reg_error;
assign classa_ctrl_en_e1_wd = reg_wdata[3];
- assign classa_ctrl_en_e2_we = addr_hit[187] & reg_we & !reg_error;
+ assign classa_ctrl_en_e2_we = addr_hit[191] & reg_we & !reg_error;
assign classa_ctrl_en_e2_wd = reg_wdata[4];
- assign classa_ctrl_en_e3_we = addr_hit[187] & reg_we & !reg_error;
+ assign classa_ctrl_en_e3_we = addr_hit[191] & reg_we & !reg_error;
assign classa_ctrl_en_e3_wd = reg_wdata[5];
- assign classa_ctrl_map_e0_we = addr_hit[187] & reg_we & !reg_error;
+ assign classa_ctrl_map_e0_we = addr_hit[191] & reg_we & !reg_error;
assign classa_ctrl_map_e0_wd = reg_wdata[7:6];
- assign classa_ctrl_map_e1_we = addr_hit[187] & reg_we & !reg_error;
+ assign classa_ctrl_map_e1_we = addr_hit[191] & reg_we & !reg_error;
assign classa_ctrl_map_e1_wd = reg_wdata[9:8];
- assign classa_ctrl_map_e2_we = addr_hit[187] & reg_we & !reg_error;
+ assign classa_ctrl_map_e2_we = addr_hit[191] & reg_we & !reg_error;
assign classa_ctrl_map_e2_wd = reg_wdata[11:10];
- assign classa_ctrl_map_e3_we = addr_hit[187] & reg_we & !reg_error;
+ assign classa_ctrl_map_e3_we = addr_hit[191] & reg_we & !reg_error;
assign classa_ctrl_map_e3_wd = reg_wdata[13:12];
- assign classa_clr_regwen_we = addr_hit[188] & reg_we & !reg_error;
+ assign classa_clr_regwen_we = addr_hit[192] & reg_we & !reg_error;
assign classa_clr_regwen_wd = reg_wdata[0];
- assign classa_clr_we = addr_hit[189] & reg_we & !reg_error;
+ assign classa_clr_we = addr_hit[193] & reg_we & !reg_error;
assign classa_clr_wd = reg_wdata[0];
- assign classa_accum_cnt_re = addr_hit[190] & reg_re & !reg_error;
+ assign classa_accum_cnt_re = addr_hit[194] & reg_re & !reg_error;
- assign classa_accum_thresh_we = addr_hit[191] & reg_we & !reg_error;
+ assign classa_accum_thresh_we = addr_hit[195] & reg_we & !reg_error;
assign classa_accum_thresh_wd = reg_wdata[15:0];
- assign classa_timeout_cyc_we = addr_hit[192] & reg_we & !reg_error;
+ assign classa_timeout_cyc_we = addr_hit[196] & reg_we & !reg_error;
assign classa_timeout_cyc_wd = reg_wdata[31:0];
- assign classa_phase0_cyc_we = addr_hit[193] & reg_we & !reg_error;
+ assign classa_phase0_cyc_we = addr_hit[197] & reg_we & !reg_error;
assign classa_phase0_cyc_wd = reg_wdata[31:0];
- assign classa_phase1_cyc_we = addr_hit[194] & reg_we & !reg_error;
+ assign classa_phase1_cyc_we = addr_hit[198] & reg_we & !reg_error;
assign classa_phase1_cyc_wd = reg_wdata[31:0];
- assign classa_phase2_cyc_we = addr_hit[195] & reg_we & !reg_error;
+ assign classa_phase2_cyc_we = addr_hit[199] & reg_we & !reg_error;
assign classa_phase2_cyc_wd = reg_wdata[31:0];
- assign classa_phase3_cyc_we = addr_hit[196] & reg_we & !reg_error;
+ assign classa_phase3_cyc_we = addr_hit[200] & reg_we & !reg_error;
assign classa_phase3_cyc_wd = reg_wdata[31:0];
- assign classa_esc_cnt_re = addr_hit[197] & reg_re & !reg_error;
+ assign classa_esc_cnt_re = addr_hit[201] & reg_re & !reg_error;
- assign classa_state_re = addr_hit[198] & reg_re & !reg_error;
+ assign classa_state_re = addr_hit[202] & reg_re & !reg_error;
- assign classb_regwen_we = addr_hit[199] & reg_we & !reg_error;
+ assign classb_regwen_we = addr_hit[203] & reg_we & !reg_error;
assign classb_regwen_wd = reg_wdata[0];
- assign classb_ctrl_en_we = addr_hit[200] & reg_we & !reg_error;
+ assign classb_ctrl_en_we = addr_hit[204] & reg_we & !reg_error;
assign classb_ctrl_en_wd = reg_wdata[0];
- assign classb_ctrl_lock_we = addr_hit[200] & reg_we & !reg_error;
+ assign classb_ctrl_lock_we = addr_hit[204] & reg_we & !reg_error;
assign classb_ctrl_lock_wd = reg_wdata[1];
- assign classb_ctrl_en_e0_we = addr_hit[200] & reg_we & !reg_error;
+ assign classb_ctrl_en_e0_we = addr_hit[204] & reg_we & !reg_error;
assign classb_ctrl_en_e0_wd = reg_wdata[2];
- assign classb_ctrl_en_e1_we = addr_hit[200] & reg_we & !reg_error;
+ assign classb_ctrl_en_e1_we = addr_hit[204] & reg_we & !reg_error;
assign classb_ctrl_en_e1_wd = reg_wdata[3];
- assign classb_ctrl_en_e2_we = addr_hit[200] & reg_we & !reg_error;
+ assign classb_ctrl_en_e2_we = addr_hit[204] & reg_we & !reg_error;
assign classb_ctrl_en_e2_wd = reg_wdata[4];
- assign classb_ctrl_en_e3_we = addr_hit[200] & reg_we & !reg_error;
+ assign classb_ctrl_en_e3_we = addr_hit[204] & reg_we & !reg_error;
assign classb_ctrl_en_e3_wd = reg_wdata[5];
- assign classb_ctrl_map_e0_we = addr_hit[200] & reg_we & !reg_error;
+ assign classb_ctrl_map_e0_we = addr_hit[204] & reg_we & !reg_error;
assign classb_ctrl_map_e0_wd = reg_wdata[7:6];
- assign classb_ctrl_map_e1_we = addr_hit[200] & reg_we & !reg_error;
+ assign classb_ctrl_map_e1_we = addr_hit[204] & reg_we & !reg_error;
assign classb_ctrl_map_e1_wd = reg_wdata[9:8];
- assign classb_ctrl_map_e2_we = addr_hit[200] & reg_we & !reg_error;
+ assign classb_ctrl_map_e2_we = addr_hit[204] & reg_we & !reg_error;
assign classb_ctrl_map_e2_wd = reg_wdata[11:10];
- assign classb_ctrl_map_e3_we = addr_hit[200] & reg_we & !reg_error;
+ assign classb_ctrl_map_e3_we = addr_hit[204] & reg_we & !reg_error;
assign classb_ctrl_map_e3_wd = reg_wdata[13:12];
- assign classb_clr_regwen_we = addr_hit[201] & reg_we & !reg_error;
+ assign classb_clr_regwen_we = addr_hit[205] & reg_we & !reg_error;
assign classb_clr_regwen_wd = reg_wdata[0];
- assign classb_clr_we = addr_hit[202] & reg_we & !reg_error;
+ assign classb_clr_we = addr_hit[206] & reg_we & !reg_error;
assign classb_clr_wd = reg_wdata[0];
- assign classb_accum_cnt_re = addr_hit[203] & reg_re & !reg_error;
+ assign classb_accum_cnt_re = addr_hit[207] & reg_re & !reg_error;
- assign classb_accum_thresh_we = addr_hit[204] & reg_we & !reg_error;
+ assign classb_accum_thresh_we = addr_hit[208] & reg_we & !reg_error;
assign classb_accum_thresh_wd = reg_wdata[15:0];
- assign classb_timeout_cyc_we = addr_hit[205] & reg_we & !reg_error;
+ assign classb_timeout_cyc_we = addr_hit[209] & reg_we & !reg_error;
assign classb_timeout_cyc_wd = reg_wdata[31:0];
- assign classb_phase0_cyc_we = addr_hit[206] & reg_we & !reg_error;
+ assign classb_phase0_cyc_we = addr_hit[210] & reg_we & !reg_error;
assign classb_phase0_cyc_wd = reg_wdata[31:0];
- assign classb_phase1_cyc_we = addr_hit[207] & reg_we & !reg_error;
+ assign classb_phase1_cyc_we = addr_hit[211] & reg_we & !reg_error;
assign classb_phase1_cyc_wd = reg_wdata[31:0];
- assign classb_phase2_cyc_we = addr_hit[208] & reg_we & !reg_error;
+ assign classb_phase2_cyc_we = addr_hit[212] & reg_we & !reg_error;
assign classb_phase2_cyc_wd = reg_wdata[31:0];
- assign classb_phase3_cyc_we = addr_hit[209] & reg_we & !reg_error;
+ assign classb_phase3_cyc_we = addr_hit[213] & reg_we & !reg_error;
assign classb_phase3_cyc_wd = reg_wdata[31:0];
- assign classb_esc_cnt_re = addr_hit[210] & reg_re & !reg_error;
+ assign classb_esc_cnt_re = addr_hit[214] & reg_re & !reg_error;
- assign classb_state_re = addr_hit[211] & reg_re & !reg_error;
+ assign classb_state_re = addr_hit[215] & reg_re & !reg_error;
- assign classc_regwen_we = addr_hit[212] & reg_we & !reg_error;
+ assign classc_regwen_we = addr_hit[216] & reg_we & !reg_error;
assign classc_regwen_wd = reg_wdata[0];
- assign classc_ctrl_en_we = addr_hit[213] & reg_we & !reg_error;
+ assign classc_ctrl_en_we = addr_hit[217] & reg_we & !reg_error;
assign classc_ctrl_en_wd = reg_wdata[0];
- assign classc_ctrl_lock_we = addr_hit[213] & reg_we & !reg_error;
+ assign classc_ctrl_lock_we = addr_hit[217] & reg_we & !reg_error;
assign classc_ctrl_lock_wd = reg_wdata[1];
- assign classc_ctrl_en_e0_we = addr_hit[213] & reg_we & !reg_error;
+ assign classc_ctrl_en_e0_we = addr_hit[217] & reg_we & !reg_error;
assign classc_ctrl_en_e0_wd = reg_wdata[2];
- assign classc_ctrl_en_e1_we = addr_hit[213] & reg_we & !reg_error;
+ assign classc_ctrl_en_e1_we = addr_hit[217] & reg_we & !reg_error;
assign classc_ctrl_en_e1_wd = reg_wdata[3];
- assign classc_ctrl_en_e2_we = addr_hit[213] & reg_we & !reg_error;
+ assign classc_ctrl_en_e2_we = addr_hit[217] & reg_we & !reg_error;
assign classc_ctrl_en_e2_wd = reg_wdata[4];
- assign classc_ctrl_en_e3_we = addr_hit[213] & reg_we & !reg_error;
+ assign classc_ctrl_en_e3_we = addr_hit[217] & reg_we & !reg_error;
assign classc_ctrl_en_e3_wd = reg_wdata[5];
- assign classc_ctrl_map_e0_we = addr_hit[213] & reg_we & !reg_error;
+ assign classc_ctrl_map_e0_we = addr_hit[217] & reg_we & !reg_error;
assign classc_ctrl_map_e0_wd = reg_wdata[7:6];
- assign classc_ctrl_map_e1_we = addr_hit[213] & reg_we & !reg_error;
+ assign classc_ctrl_map_e1_we = addr_hit[217] & reg_we & !reg_error;
assign classc_ctrl_map_e1_wd = reg_wdata[9:8];
- assign classc_ctrl_map_e2_we = addr_hit[213] & reg_we & !reg_error;
+ assign classc_ctrl_map_e2_we = addr_hit[217] & reg_we & !reg_error;
assign classc_ctrl_map_e2_wd = reg_wdata[11:10];
- assign classc_ctrl_map_e3_we = addr_hit[213] & reg_we & !reg_error;
+ assign classc_ctrl_map_e3_we = addr_hit[217] & reg_we & !reg_error;
assign classc_ctrl_map_e3_wd = reg_wdata[13:12];
- assign classc_clr_regwen_we = addr_hit[214] & reg_we & !reg_error;
+ assign classc_clr_regwen_we = addr_hit[218] & reg_we & !reg_error;
assign classc_clr_regwen_wd = reg_wdata[0];
- assign classc_clr_we = addr_hit[215] & reg_we & !reg_error;
+ assign classc_clr_we = addr_hit[219] & reg_we & !reg_error;
assign classc_clr_wd = reg_wdata[0];
- assign classc_accum_cnt_re = addr_hit[216] & reg_re & !reg_error;
+ assign classc_accum_cnt_re = addr_hit[220] & reg_re & !reg_error;
- assign classc_accum_thresh_we = addr_hit[217] & reg_we & !reg_error;
+ assign classc_accum_thresh_we = addr_hit[221] & reg_we & !reg_error;
assign classc_accum_thresh_wd = reg_wdata[15:0];
- assign classc_timeout_cyc_we = addr_hit[218] & reg_we & !reg_error;
+ assign classc_timeout_cyc_we = addr_hit[222] & reg_we & !reg_error;
assign classc_timeout_cyc_wd = reg_wdata[31:0];
- assign classc_phase0_cyc_we = addr_hit[219] & reg_we & !reg_error;
+ assign classc_phase0_cyc_we = addr_hit[223] & reg_we & !reg_error;
assign classc_phase0_cyc_wd = reg_wdata[31:0];
- assign classc_phase1_cyc_we = addr_hit[220] & reg_we & !reg_error;
+ assign classc_phase1_cyc_we = addr_hit[224] & reg_we & !reg_error;
assign classc_phase1_cyc_wd = reg_wdata[31:0];
- assign classc_phase2_cyc_we = addr_hit[221] & reg_we & !reg_error;
+ assign classc_phase2_cyc_we = addr_hit[225] & reg_we & !reg_error;
assign classc_phase2_cyc_wd = reg_wdata[31:0];
- assign classc_phase3_cyc_we = addr_hit[222] & reg_we & !reg_error;
+ assign classc_phase3_cyc_we = addr_hit[226] & reg_we & !reg_error;
assign classc_phase3_cyc_wd = reg_wdata[31:0];
- assign classc_esc_cnt_re = addr_hit[223] & reg_re & !reg_error;
+ assign classc_esc_cnt_re = addr_hit[227] & reg_re & !reg_error;
- assign classc_state_re = addr_hit[224] & reg_re & !reg_error;
+ assign classc_state_re = addr_hit[228] & reg_re & !reg_error;
- assign classd_regwen_we = addr_hit[225] & reg_we & !reg_error;
+ assign classd_regwen_we = addr_hit[229] & reg_we & !reg_error;
assign classd_regwen_wd = reg_wdata[0];
- assign classd_ctrl_en_we = addr_hit[226] & reg_we & !reg_error;
+ assign classd_ctrl_en_we = addr_hit[230] & reg_we & !reg_error;
assign classd_ctrl_en_wd = reg_wdata[0];
- assign classd_ctrl_lock_we = addr_hit[226] & reg_we & !reg_error;
+ assign classd_ctrl_lock_we = addr_hit[230] & reg_we & !reg_error;
assign classd_ctrl_lock_wd = reg_wdata[1];
- assign classd_ctrl_en_e0_we = addr_hit[226] & reg_we & !reg_error;
+ assign classd_ctrl_en_e0_we = addr_hit[230] & reg_we & !reg_error;
assign classd_ctrl_en_e0_wd = reg_wdata[2];
- assign classd_ctrl_en_e1_we = addr_hit[226] & reg_we & !reg_error;
+ assign classd_ctrl_en_e1_we = addr_hit[230] & reg_we & !reg_error;
assign classd_ctrl_en_e1_wd = reg_wdata[3];
- assign classd_ctrl_en_e2_we = addr_hit[226] & reg_we & !reg_error;
+ assign classd_ctrl_en_e2_we = addr_hit[230] & reg_we & !reg_error;
assign classd_ctrl_en_e2_wd = reg_wdata[4];
- assign classd_ctrl_en_e3_we = addr_hit[226] & reg_we & !reg_error;
+ assign classd_ctrl_en_e3_we = addr_hit[230] & reg_we & !reg_error;
assign classd_ctrl_en_e3_wd = reg_wdata[5];
- assign classd_ctrl_map_e0_we = addr_hit[226] & reg_we & !reg_error;
+ assign classd_ctrl_map_e0_we = addr_hit[230] & reg_we & !reg_error;
assign classd_ctrl_map_e0_wd = reg_wdata[7:6];
- assign classd_ctrl_map_e1_we = addr_hit[226] & reg_we & !reg_error;
+ assign classd_ctrl_map_e1_we = addr_hit[230] & reg_we & !reg_error;
assign classd_ctrl_map_e1_wd = reg_wdata[9:8];
- assign classd_ctrl_map_e2_we = addr_hit[226] & reg_we & !reg_error;
+ assign classd_ctrl_map_e2_we = addr_hit[230] & reg_we & !reg_error;
assign classd_ctrl_map_e2_wd = reg_wdata[11:10];
- assign classd_ctrl_map_e3_we = addr_hit[226] & reg_we & !reg_error;
+ assign classd_ctrl_map_e3_we = addr_hit[230] & reg_we & !reg_error;
assign classd_ctrl_map_e3_wd = reg_wdata[13:12];
- assign classd_clr_regwen_we = addr_hit[227] & reg_we & !reg_error;
+ assign classd_clr_regwen_we = addr_hit[231] & reg_we & !reg_error;
assign classd_clr_regwen_wd = reg_wdata[0];
- assign classd_clr_we = addr_hit[228] & reg_we & !reg_error;
+ assign classd_clr_we = addr_hit[232] & reg_we & !reg_error;
assign classd_clr_wd = reg_wdata[0];
- assign classd_accum_cnt_re = addr_hit[229] & reg_re & !reg_error;
+ assign classd_accum_cnt_re = addr_hit[233] & reg_re & !reg_error;
- assign classd_accum_thresh_we = addr_hit[230] & reg_we & !reg_error;
+ assign classd_accum_thresh_we = addr_hit[234] & reg_we & !reg_error;
assign classd_accum_thresh_wd = reg_wdata[15:0];
- assign classd_timeout_cyc_we = addr_hit[231] & reg_we & !reg_error;
+ assign classd_timeout_cyc_we = addr_hit[235] & reg_we & !reg_error;
assign classd_timeout_cyc_wd = reg_wdata[31:0];
- assign classd_phase0_cyc_we = addr_hit[232] & reg_we & !reg_error;
+ assign classd_phase0_cyc_we = addr_hit[236] & reg_we & !reg_error;
assign classd_phase0_cyc_wd = reg_wdata[31:0];
- assign classd_phase1_cyc_we = addr_hit[233] & reg_we & !reg_error;
+ assign classd_phase1_cyc_we = addr_hit[237] & reg_we & !reg_error;
assign classd_phase1_cyc_wd = reg_wdata[31:0];
- assign classd_phase2_cyc_we = addr_hit[234] & reg_we & !reg_error;
+ assign classd_phase2_cyc_we = addr_hit[238] & reg_we & !reg_error;
assign classd_phase2_cyc_wd = reg_wdata[31:0];
- assign classd_phase3_cyc_we = addr_hit[235] & reg_we & !reg_error;
+ assign classd_phase3_cyc_we = addr_hit[239] & reg_we & !reg_error;
assign classd_phase3_cyc_wd = reg_wdata[31:0];
- assign classd_esc_cnt_re = addr_hit[236] & reg_re & !reg_error;
+ assign classd_esc_cnt_re = addr_hit[240] & reg_re & !reg_error;
- assign classd_state_re = addr_hit[237] & reg_re & !reg_error;
+ assign classd_state_re = addr_hit[241] & reg_re & !reg_error;
// Read data return
always_comb begin
@@ -9903,570 +10043,586 @@
end
addr_hit[46]: begin
- reg_rdata_next[0] = alert_en_0_qs;
+ reg_rdata_next[0] = alert_regwen_40_qs;
end
addr_hit[47]: begin
- reg_rdata_next[0] = alert_en_1_qs;
+ reg_rdata_next[0] = alert_en_0_qs;
end
addr_hit[48]: begin
- reg_rdata_next[0] = alert_en_2_qs;
+ reg_rdata_next[0] = alert_en_1_qs;
end
addr_hit[49]: begin
- reg_rdata_next[0] = alert_en_3_qs;
+ reg_rdata_next[0] = alert_en_2_qs;
end
addr_hit[50]: begin
- reg_rdata_next[0] = alert_en_4_qs;
+ reg_rdata_next[0] = alert_en_3_qs;
end
addr_hit[51]: begin
- reg_rdata_next[0] = alert_en_5_qs;
+ reg_rdata_next[0] = alert_en_4_qs;
end
addr_hit[52]: begin
- reg_rdata_next[0] = alert_en_6_qs;
+ reg_rdata_next[0] = alert_en_5_qs;
end
addr_hit[53]: begin
- reg_rdata_next[0] = alert_en_7_qs;
+ reg_rdata_next[0] = alert_en_6_qs;
end
addr_hit[54]: begin
- reg_rdata_next[0] = alert_en_8_qs;
+ reg_rdata_next[0] = alert_en_7_qs;
end
addr_hit[55]: begin
- reg_rdata_next[0] = alert_en_9_qs;
+ reg_rdata_next[0] = alert_en_8_qs;
end
addr_hit[56]: begin
- reg_rdata_next[0] = alert_en_10_qs;
+ reg_rdata_next[0] = alert_en_9_qs;
end
addr_hit[57]: begin
- reg_rdata_next[0] = alert_en_11_qs;
+ reg_rdata_next[0] = alert_en_10_qs;
end
addr_hit[58]: begin
- reg_rdata_next[0] = alert_en_12_qs;
+ reg_rdata_next[0] = alert_en_11_qs;
end
addr_hit[59]: begin
- reg_rdata_next[0] = alert_en_13_qs;
+ reg_rdata_next[0] = alert_en_12_qs;
end
addr_hit[60]: begin
- reg_rdata_next[0] = alert_en_14_qs;
+ reg_rdata_next[0] = alert_en_13_qs;
end
addr_hit[61]: begin
- reg_rdata_next[0] = alert_en_15_qs;
+ reg_rdata_next[0] = alert_en_14_qs;
end
addr_hit[62]: begin
- reg_rdata_next[0] = alert_en_16_qs;
+ reg_rdata_next[0] = alert_en_15_qs;
end
addr_hit[63]: begin
- reg_rdata_next[0] = alert_en_17_qs;
+ reg_rdata_next[0] = alert_en_16_qs;
end
addr_hit[64]: begin
- reg_rdata_next[0] = alert_en_18_qs;
+ reg_rdata_next[0] = alert_en_17_qs;
end
addr_hit[65]: begin
- reg_rdata_next[0] = alert_en_19_qs;
+ reg_rdata_next[0] = alert_en_18_qs;
end
addr_hit[66]: begin
- reg_rdata_next[0] = alert_en_20_qs;
+ reg_rdata_next[0] = alert_en_19_qs;
end
addr_hit[67]: begin
- reg_rdata_next[0] = alert_en_21_qs;
+ reg_rdata_next[0] = alert_en_20_qs;
end
addr_hit[68]: begin
- reg_rdata_next[0] = alert_en_22_qs;
+ reg_rdata_next[0] = alert_en_21_qs;
end
addr_hit[69]: begin
- reg_rdata_next[0] = alert_en_23_qs;
+ reg_rdata_next[0] = alert_en_22_qs;
end
addr_hit[70]: begin
- reg_rdata_next[0] = alert_en_24_qs;
+ reg_rdata_next[0] = alert_en_23_qs;
end
addr_hit[71]: begin
- reg_rdata_next[0] = alert_en_25_qs;
+ reg_rdata_next[0] = alert_en_24_qs;
end
addr_hit[72]: begin
- reg_rdata_next[0] = alert_en_26_qs;
+ reg_rdata_next[0] = alert_en_25_qs;
end
addr_hit[73]: begin
- reg_rdata_next[0] = alert_en_27_qs;
+ reg_rdata_next[0] = alert_en_26_qs;
end
addr_hit[74]: begin
- reg_rdata_next[0] = alert_en_28_qs;
+ reg_rdata_next[0] = alert_en_27_qs;
end
addr_hit[75]: begin
- reg_rdata_next[0] = alert_en_29_qs;
+ reg_rdata_next[0] = alert_en_28_qs;
end
addr_hit[76]: begin
- reg_rdata_next[0] = alert_en_30_qs;
+ reg_rdata_next[0] = alert_en_29_qs;
end
addr_hit[77]: begin
- reg_rdata_next[0] = alert_en_31_qs;
+ reg_rdata_next[0] = alert_en_30_qs;
end
addr_hit[78]: begin
- reg_rdata_next[0] = alert_en_32_qs;
+ reg_rdata_next[0] = alert_en_31_qs;
end
addr_hit[79]: begin
- reg_rdata_next[0] = alert_en_33_qs;
+ reg_rdata_next[0] = alert_en_32_qs;
end
addr_hit[80]: begin
- reg_rdata_next[0] = alert_en_34_qs;
+ reg_rdata_next[0] = alert_en_33_qs;
end
addr_hit[81]: begin
- reg_rdata_next[0] = alert_en_35_qs;
+ reg_rdata_next[0] = alert_en_34_qs;
end
addr_hit[82]: begin
- reg_rdata_next[0] = alert_en_36_qs;
+ reg_rdata_next[0] = alert_en_35_qs;
end
addr_hit[83]: begin
- reg_rdata_next[0] = alert_en_37_qs;
+ reg_rdata_next[0] = alert_en_36_qs;
end
addr_hit[84]: begin
- reg_rdata_next[0] = alert_en_38_qs;
+ reg_rdata_next[0] = alert_en_37_qs;
end
addr_hit[85]: begin
- reg_rdata_next[0] = alert_en_39_qs;
+ reg_rdata_next[0] = alert_en_38_qs;
end
addr_hit[86]: begin
- reg_rdata_next[1:0] = alert_class_0_qs;
+ reg_rdata_next[0] = alert_en_39_qs;
end
addr_hit[87]: begin
- reg_rdata_next[1:0] = alert_class_1_qs;
+ reg_rdata_next[0] = alert_en_40_qs;
end
addr_hit[88]: begin
- reg_rdata_next[1:0] = alert_class_2_qs;
+ reg_rdata_next[1:0] = alert_class_0_qs;
end
addr_hit[89]: begin
- reg_rdata_next[1:0] = alert_class_3_qs;
+ reg_rdata_next[1:0] = alert_class_1_qs;
end
addr_hit[90]: begin
- reg_rdata_next[1:0] = alert_class_4_qs;
+ reg_rdata_next[1:0] = alert_class_2_qs;
end
addr_hit[91]: begin
- reg_rdata_next[1:0] = alert_class_5_qs;
+ reg_rdata_next[1:0] = alert_class_3_qs;
end
addr_hit[92]: begin
- reg_rdata_next[1:0] = alert_class_6_qs;
+ reg_rdata_next[1:0] = alert_class_4_qs;
end
addr_hit[93]: begin
- reg_rdata_next[1:0] = alert_class_7_qs;
+ reg_rdata_next[1:0] = alert_class_5_qs;
end
addr_hit[94]: begin
- reg_rdata_next[1:0] = alert_class_8_qs;
+ reg_rdata_next[1:0] = alert_class_6_qs;
end
addr_hit[95]: begin
- reg_rdata_next[1:0] = alert_class_9_qs;
+ reg_rdata_next[1:0] = alert_class_7_qs;
end
addr_hit[96]: begin
- reg_rdata_next[1:0] = alert_class_10_qs;
+ reg_rdata_next[1:0] = alert_class_8_qs;
end
addr_hit[97]: begin
- reg_rdata_next[1:0] = alert_class_11_qs;
+ reg_rdata_next[1:0] = alert_class_9_qs;
end
addr_hit[98]: begin
- reg_rdata_next[1:0] = alert_class_12_qs;
+ reg_rdata_next[1:0] = alert_class_10_qs;
end
addr_hit[99]: begin
- reg_rdata_next[1:0] = alert_class_13_qs;
+ reg_rdata_next[1:0] = alert_class_11_qs;
end
addr_hit[100]: begin
- reg_rdata_next[1:0] = alert_class_14_qs;
+ reg_rdata_next[1:0] = alert_class_12_qs;
end
addr_hit[101]: begin
- reg_rdata_next[1:0] = alert_class_15_qs;
+ reg_rdata_next[1:0] = alert_class_13_qs;
end
addr_hit[102]: begin
- reg_rdata_next[1:0] = alert_class_16_qs;
+ reg_rdata_next[1:0] = alert_class_14_qs;
end
addr_hit[103]: begin
- reg_rdata_next[1:0] = alert_class_17_qs;
+ reg_rdata_next[1:0] = alert_class_15_qs;
end
addr_hit[104]: begin
- reg_rdata_next[1:0] = alert_class_18_qs;
+ reg_rdata_next[1:0] = alert_class_16_qs;
end
addr_hit[105]: begin
- reg_rdata_next[1:0] = alert_class_19_qs;
+ reg_rdata_next[1:0] = alert_class_17_qs;
end
addr_hit[106]: begin
- reg_rdata_next[1:0] = alert_class_20_qs;
+ reg_rdata_next[1:0] = alert_class_18_qs;
end
addr_hit[107]: begin
- reg_rdata_next[1:0] = alert_class_21_qs;
+ reg_rdata_next[1:0] = alert_class_19_qs;
end
addr_hit[108]: begin
- reg_rdata_next[1:0] = alert_class_22_qs;
+ reg_rdata_next[1:0] = alert_class_20_qs;
end
addr_hit[109]: begin
- reg_rdata_next[1:0] = alert_class_23_qs;
+ reg_rdata_next[1:0] = alert_class_21_qs;
end
addr_hit[110]: begin
- reg_rdata_next[1:0] = alert_class_24_qs;
+ reg_rdata_next[1:0] = alert_class_22_qs;
end
addr_hit[111]: begin
- reg_rdata_next[1:0] = alert_class_25_qs;
+ reg_rdata_next[1:0] = alert_class_23_qs;
end
addr_hit[112]: begin
- reg_rdata_next[1:0] = alert_class_26_qs;
+ reg_rdata_next[1:0] = alert_class_24_qs;
end
addr_hit[113]: begin
- reg_rdata_next[1:0] = alert_class_27_qs;
+ reg_rdata_next[1:0] = alert_class_25_qs;
end
addr_hit[114]: begin
- reg_rdata_next[1:0] = alert_class_28_qs;
+ reg_rdata_next[1:0] = alert_class_26_qs;
end
addr_hit[115]: begin
- reg_rdata_next[1:0] = alert_class_29_qs;
+ reg_rdata_next[1:0] = alert_class_27_qs;
end
addr_hit[116]: begin
- reg_rdata_next[1:0] = alert_class_30_qs;
+ reg_rdata_next[1:0] = alert_class_28_qs;
end
addr_hit[117]: begin
- reg_rdata_next[1:0] = alert_class_31_qs;
+ reg_rdata_next[1:0] = alert_class_29_qs;
end
addr_hit[118]: begin
- reg_rdata_next[1:0] = alert_class_32_qs;
+ reg_rdata_next[1:0] = alert_class_30_qs;
end
addr_hit[119]: begin
- reg_rdata_next[1:0] = alert_class_33_qs;
+ reg_rdata_next[1:0] = alert_class_31_qs;
end
addr_hit[120]: begin
- reg_rdata_next[1:0] = alert_class_34_qs;
+ reg_rdata_next[1:0] = alert_class_32_qs;
end
addr_hit[121]: begin
- reg_rdata_next[1:0] = alert_class_35_qs;
+ reg_rdata_next[1:0] = alert_class_33_qs;
end
addr_hit[122]: begin
- reg_rdata_next[1:0] = alert_class_36_qs;
+ reg_rdata_next[1:0] = alert_class_34_qs;
end
addr_hit[123]: begin
- reg_rdata_next[1:0] = alert_class_37_qs;
+ reg_rdata_next[1:0] = alert_class_35_qs;
end
addr_hit[124]: begin
- reg_rdata_next[1:0] = alert_class_38_qs;
+ reg_rdata_next[1:0] = alert_class_36_qs;
end
addr_hit[125]: begin
- reg_rdata_next[1:0] = alert_class_39_qs;
+ reg_rdata_next[1:0] = alert_class_37_qs;
end
addr_hit[126]: begin
- reg_rdata_next[0] = alert_cause_0_qs;
+ reg_rdata_next[1:0] = alert_class_38_qs;
end
addr_hit[127]: begin
- reg_rdata_next[0] = alert_cause_1_qs;
+ reg_rdata_next[1:0] = alert_class_39_qs;
end
addr_hit[128]: begin
- reg_rdata_next[0] = alert_cause_2_qs;
+ reg_rdata_next[1:0] = alert_class_40_qs;
end
addr_hit[129]: begin
- reg_rdata_next[0] = alert_cause_3_qs;
+ reg_rdata_next[0] = alert_cause_0_qs;
end
addr_hit[130]: begin
- reg_rdata_next[0] = alert_cause_4_qs;
+ reg_rdata_next[0] = alert_cause_1_qs;
end
addr_hit[131]: begin
- reg_rdata_next[0] = alert_cause_5_qs;
+ reg_rdata_next[0] = alert_cause_2_qs;
end
addr_hit[132]: begin
- reg_rdata_next[0] = alert_cause_6_qs;
+ reg_rdata_next[0] = alert_cause_3_qs;
end
addr_hit[133]: begin
- reg_rdata_next[0] = alert_cause_7_qs;
+ reg_rdata_next[0] = alert_cause_4_qs;
end
addr_hit[134]: begin
- reg_rdata_next[0] = alert_cause_8_qs;
+ reg_rdata_next[0] = alert_cause_5_qs;
end
addr_hit[135]: begin
- reg_rdata_next[0] = alert_cause_9_qs;
+ reg_rdata_next[0] = alert_cause_6_qs;
end
addr_hit[136]: begin
- reg_rdata_next[0] = alert_cause_10_qs;
+ reg_rdata_next[0] = alert_cause_7_qs;
end
addr_hit[137]: begin
- reg_rdata_next[0] = alert_cause_11_qs;
+ reg_rdata_next[0] = alert_cause_8_qs;
end
addr_hit[138]: begin
- reg_rdata_next[0] = alert_cause_12_qs;
+ reg_rdata_next[0] = alert_cause_9_qs;
end
addr_hit[139]: begin
- reg_rdata_next[0] = alert_cause_13_qs;
+ reg_rdata_next[0] = alert_cause_10_qs;
end
addr_hit[140]: begin
- reg_rdata_next[0] = alert_cause_14_qs;
+ reg_rdata_next[0] = alert_cause_11_qs;
end
addr_hit[141]: begin
- reg_rdata_next[0] = alert_cause_15_qs;
+ reg_rdata_next[0] = alert_cause_12_qs;
end
addr_hit[142]: begin
- reg_rdata_next[0] = alert_cause_16_qs;
+ reg_rdata_next[0] = alert_cause_13_qs;
end
addr_hit[143]: begin
- reg_rdata_next[0] = alert_cause_17_qs;
+ reg_rdata_next[0] = alert_cause_14_qs;
end
addr_hit[144]: begin
- reg_rdata_next[0] = alert_cause_18_qs;
+ reg_rdata_next[0] = alert_cause_15_qs;
end
addr_hit[145]: begin
- reg_rdata_next[0] = alert_cause_19_qs;
+ reg_rdata_next[0] = alert_cause_16_qs;
end
addr_hit[146]: begin
- reg_rdata_next[0] = alert_cause_20_qs;
+ reg_rdata_next[0] = alert_cause_17_qs;
end
addr_hit[147]: begin
- reg_rdata_next[0] = alert_cause_21_qs;
+ reg_rdata_next[0] = alert_cause_18_qs;
end
addr_hit[148]: begin
- reg_rdata_next[0] = alert_cause_22_qs;
+ reg_rdata_next[0] = alert_cause_19_qs;
end
addr_hit[149]: begin
- reg_rdata_next[0] = alert_cause_23_qs;
+ reg_rdata_next[0] = alert_cause_20_qs;
end
addr_hit[150]: begin
- reg_rdata_next[0] = alert_cause_24_qs;
+ reg_rdata_next[0] = alert_cause_21_qs;
end
addr_hit[151]: begin
- reg_rdata_next[0] = alert_cause_25_qs;
+ reg_rdata_next[0] = alert_cause_22_qs;
end
addr_hit[152]: begin
- reg_rdata_next[0] = alert_cause_26_qs;
+ reg_rdata_next[0] = alert_cause_23_qs;
end
addr_hit[153]: begin
- reg_rdata_next[0] = alert_cause_27_qs;
+ reg_rdata_next[0] = alert_cause_24_qs;
end
addr_hit[154]: begin
- reg_rdata_next[0] = alert_cause_28_qs;
+ reg_rdata_next[0] = alert_cause_25_qs;
end
addr_hit[155]: begin
- reg_rdata_next[0] = alert_cause_29_qs;
+ reg_rdata_next[0] = alert_cause_26_qs;
end
addr_hit[156]: begin
- reg_rdata_next[0] = alert_cause_30_qs;
+ reg_rdata_next[0] = alert_cause_27_qs;
end
addr_hit[157]: begin
- reg_rdata_next[0] = alert_cause_31_qs;
+ reg_rdata_next[0] = alert_cause_28_qs;
end
addr_hit[158]: begin
- reg_rdata_next[0] = alert_cause_32_qs;
+ reg_rdata_next[0] = alert_cause_29_qs;
end
addr_hit[159]: begin
- reg_rdata_next[0] = alert_cause_33_qs;
+ reg_rdata_next[0] = alert_cause_30_qs;
end
addr_hit[160]: begin
- reg_rdata_next[0] = alert_cause_34_qs;
+ reg_rdata_next[0] = alert_cause_31_qs;
end
addr_hit[161]: begin
- reg_rdata_next[0] = alert_cause_35_qs;
+ reg_rdata_next[0] = alert_cause_32_qs;
end
addr_hit[162]: begin
- reg_rdata_next[0] = alert_cause_36_qs;
+ reg_rdata_next[0] = alert_cause_33_qs;
end
addr_hit[163]: begin
- reg_rdata_next[0] = alert_cause_37_qs;
+ reg_rdata_next[0] = alert_cause_34_qs;
end
addr_hit[164]: begin
- reg_rdata_next[0] = alert_cause_38_qs;
+ reg_rdata_next[0] = alert_cause_35_qs;
end
addr_hit[165]: begin
- reg_rdata_next[0] = alert_cause_39_qs;
+ reg_rdata_next[0] = alert_cause_36_qs;
end
addr_hit[166]: begin
- reg_rdata_next[0] = loc_alert_regwen_0_qs;
+ reg_rdata_next[0] = alert_cause_37_qs;
end
addr_hit[167]: begin
- reg_rdata_next[0] = loc_alert_regwen_1_qs;
+ reg_rdata_next[0] = alert_cause_38_qs;
end
addr_hit[168]: begin
- reg_rdata_next[0] = loc_alert_regwen_2_qs;
+ reg_rdata_next[0] = alert_cause_39_qs;
end
addr_hit[169]: begin
- reg_rdata_next[0] = loc_alert_regwen_3_qs;
+ reg_rdata_next[0] = alert_cause_40_qs;
end
addr_hit[170]: begin
- reg_rdata_next[0] = loc_alert_regwen_4_qs;
+ reg_rdata_next[0] = loc_alert_regwen_0_qs;
end
addr_hit[171]: begin
- reg_rdata_next[0] = loc_alert_en_0_qs;
+ reg_rdata_next[0] = loc_alert_regwen_1_qs;
end
addr_hit[172]: begin
- reg_rdata_next[0] = loc_alert_en_1_qs;
+ reg_rdata_next[0] = loc_alert_regwen_2_qs;
end
addr_hit[173]: begin
- reg_rdata_next[0] = loc_alert_en_2_qs;
+ reg_rdata_next[0] = loc_alert_regwen_3_qs;
end
addr_hit[174]: begin
- reg_rdata_next[0] = loc_alert_en_3_qs;
+ reg_rdata_next[0] = loc_alert_regwen_4_qs;
end
addr_hit[175]: begin
- reg_rdata_next[0] = loc_alert_en_4_qs;
+ reg_rdata_next[0] = loc_alert_en_0_qs;
end
addr_hit[176]: begin
- reg_rdata_next[1:0] = loc_alert_class_0_qs;
+ reg_rdata_next[0] = loc_alert_en_1_qs;
end
addr_hit[177]: begin
- reg_rdata_next[1:0] = loc_alert_class_1_qs;
+ reg_rdata_next[0] = loc_alert_en_2_qs;
end
addr_hit[178]: begin
- reg_rdata_next[1:0] = loc_alert_class_2_qs;
+ reg_rdata_next[0] = loc_alert_en_3_qs;
end
addr_hit[179]: begin
- reg_rdata_next[1:0] = loc_alert_class_3_qs;
+ reg_rdata_next[0] = loc_alert_en_4_qs;
end
addr_hit[180]: begin
- reg_rdata_next[1:0] = loc_alert_class_4_qs;
+ reg_rdata_next[1:0] = loc_alert_class_0_qs;
end
addr_hit[181]: begin
- reg_rdata_next[0] = loc_alert_cause_0_qs;
+ reg_rdata_next[1:0] = loc_alert_class_1_qs;
end
addr_hit[182]: begin
- reg_rdata_next[0] = loc_alert_cause_1_qs;
+ reg_rdata_next[1:0] = loc_alert_class_2_qs;
end
addr_hit[183]: begin
- reg_rdata_next[0] = loc_alert_cause_2_qs;
+ reg_rdata_next[1:0] = loc_alert_class_3_qs;
end
addr_hit[184]: begin
- reg_rdata_next[0] = loc_alert_cause_3_qs;
+ reg_rdata_next[1:0] = loc_alert_class_4_qs;
end
addr_hit[185]: begin
- reg_rdata_next[0] = loc_alert_cause_4_qs;
+ reg_rdata_next[0] = loc_alert_cause_0_qs;
end
addr_hit[186]: begin
- reg_rdata_next[0] = classa_regwen_qs;
+ reg_rdata_next[0] = loc_alert_cause_1_qs;
end
addr_hit[187]: begin
+ reg_rdata_next[0] = loc_alert_cause_2_qs;
+ end
+
+ addr_hit[188]: begin
+ reg_rdata_next[0] = loc_alert_cause_3_qs;
+ end
+
+ addr_hit[189]: begin
+ reg_rdata_next[0] = loc_alert_cause_4_qs;
+ end
+
+ addr_hit[190]: begin
+ reg_rdata_next[0] = classa_regwen_qs;
+ end
+
+ addr_hit[191]: begin
reg_rdata_next[0] = classa_ctrl_en_qs;
reg_rdata_next[1] = classa_ctrl_lock_qs;
reg_rdata_next[2] = classa_ctrl_en_e0_qs;
@@ -10479,55 +10635,55 @@
reg_rdata_next[13:12] = classa_ctrl_map_e3_qs;
end
- addr_hit[188]: begin
+ addr_hit[192]: begin
reg_rdata_next[0] = classa_clr_regwen_qs;
end
- addr_hit[189]: begin
+ addr_hit[193]: begin
reg_rdata_next[0] = '0;
end
- addr_hit[190]: begin
+ addr_hit[194]: begin
reg_rdata_next[15:0] = classa_accum_cnt_qs;
end
- addr_hit[191]: begin
+ addr_hit[195]: begin
reg_rdata_next[15:0] = classa_accum_thresh_qs;
end
- addr_hit[192]: begin
+ addr_hit[196]: begin
reg_rdata_next[31:0] = classa_timeout_cyc_qs;
end
- addr_hit[193]: begin
+ addr_hit[197]: begin
reg_rdata_next[31:0] = classa_phase0_cyc_qs;
end
- addr_hit[194]: begin
+ addr_hit[198]: begin
reg_rdata_next[31:0] = classa_phase1_cyc_qs;
end
- addr_hit[195]: begin
+ addr_hit[199]: begin
reg_rdata_next[31:0] = classa_phase2_cyc_qs;
end
- addr_hit[196]: begin
+ addr_hit[200]: begin
reg_rdata_next[31:0] = classa_phase3_cyc_qs;
end
- addr_hit[197]: begin
+ addr_hit[201]: begin
reg_rdata_next[31:0] = classa_esc_cnt_qs;
end
- addr_hit[198]: begin
+ addr_hit[202]: begin
reg_rdata_next[2:0] = classa_state_qs;
end
- addr_hit[199]: begin
+ addr_hit[203]: begin
reg_rdata_next[0] = classb_regwen_qs;
end
- addr_hit[200]: begin
+ addr_hit[204]: begin
reg_rdata_next[0] = classb_ctrl_en_qs;
reg_rdata_next[1] = classb_ctrl_lock_qs;
reg_rdata_next[2] = classb_ctrl_en_e0_qs;
@@ -10540,55 +10696,55 @@
reg_rdata_next[13:12] = classb_ctrl_map_e3_qs;
end
- addr_hit[201]: begin
+ addr_hit[205]: begin
reg_rdata_next[0] = classb_clr_regwen_qs;
end
- addr_hit[202]: begin
+ addr_hit[206]: begin
reg_rdata_next[0] = '0;
end
- addr_hit[203]: begin
+ addr_hit[207]: begin
reg_rdata_next[15:0] = classb_accum_cnt_qs;
end
- addr_hit[204]: begin
+ addr_hit[208]: begin
reg_rdata_next[15:0] = classb_accum_thresh_qs;
end
- addr_hit[205]: begin
+ addr_hit[209]: begin
reg_rdata_next[31:0] = classb_timeout_cyc_qs;
end
- addr_hit[206]: begin
+ addr_hit[210]: begin
reg_rdata_next[31:0] = classb_phase0_cyc_qs;
end
- addr_hit[207]: begin
+ addr_hit[211]: begin
reg_rdata_next[31:0] = classb_phase1_cyc_qs;
end
- addr_hit[208]: begin
+ addr_hit[212]: begin
reg_rdata_next[31:0] = classb_phase2_cyc_qs;
end
- addr_hit[209]: begin
+ addr_hit[213]: begin
reg_rdata_next[31:0] = classb_phase3_cyc_qs;
end
- addr_hit[210]: begin
+ addr_hit[214]: begin
reg_rdata_next[31:0] = classb_esc_cnt_qs;
end
- addr_hit[211]: begin
+ addr_hit[215]: begin
reg_rdata_next[2:0] = classb_state_qs;
end
- addr_hit[212]: begin
+ addr_hit[216]: begin
reg_rdata_next[0] = classc_regwen_qs;
end
- addr_hit[213]: begin
+ addr_hit[217]: begin
reg_rdata_next[0] = classc_ctrl_en_qs;
reg_rdata_next[1] = classc_ctrl_lock_qs;
reg_rdata_next[2] = classc_ctrl_en_e0_qs;
@@ -10601,55 +10757,55 @@
reg_rdata_next[13:12] = classc_ctrl_map_e3_qs;
end
- addr_hit[214]: begin
+ addr_hit[218]: begin
reg_rdata_next[0] = classc_clr_regwen_qs;
end
- addr_hit[215]: begin
+ addr_hit[219]: begin
reg_rdata_next[0] = '0;
end
- addr_hit[216]: begin
+ addr_hit[220]: begin
reg_rdata_next[15:0] = classc_accum_cnt_qs;
end
- addr_hit[217]: begin
+ addr_hit[221]: begin
reg_rdata_next[15:0] = classc_accum_thresh_qs;
end
- addr_hit[218]: begin
+ addr_hit[222]: begin
reg_rdata_next[31:0] = classc_timeout_cyc_qs;
end
- addr_hit[219]: begin
+ addr_hit[223]: begin
reg_rdata_next[31:0] = classc_phase0_cyc_qs;
end
- addr_hit[220]: begin
+ addr_hit[224]: begin
reg_rdata_next[31:0] = classc_phase1_cyc_qs;
end
- addr_hit[221]: begin
+ addr_hit[225]: begin
reg_rdata_next[31:0] = classc_phase2_cyc_qs;
end
- addr_hit[222]: begin
+ addr_hit[226]: begin
reg_rdata_next[31:0] = classc_phase3_cyc_qs;
end
- addr_hit[223]: begin
+ addr_hit[227]: begin
reg_rdata_next[31:0] = classc_esc_cnt_qs;
end
- addr_hit[224]: begin
+ addr_hit[228]: begin
reg_rdata_next[2:0] = classc_state_qs;
end
- addr_hit[225]: begin
+ addr_hit[229]: begin
reg_rdata_next[0] = classd_regwen_qs;
end
- addr_hit[226]: begin
+ addr_hit[230]: begin
reg_rdata_next[0] = classd_ctrl_en_qs;
reg_rdata_next[1] = classd_ctrl_lock_qs;
reg_rdata_next[2] = classd_ctrl_en_e0_qs;
@@ -10662,47 +10818,47 @@
reg_rdata_next[13:12] = classd_ctrl_map_e3_qs;
end
- addr_hit[227]: begin
+ addr_hit[231]: begin
reg_rdata_next[0] = classd_clr_regwen_qs;
end
- addr_hit[228]: begin
+ addr_hit[232]: begin
reg_rdata_next[0] = '0;
end
- addr_hit[229]: begin
+ addr_hit[233]: begin
reg_rdata_next[15:0] = classd_accum_cnt_qs;
end
- addr_hit[230]: begin
+ addr_hit[234]: begin
reg_rdata_next[15:0] = classd_accum_thresh_qs;
end
- addr_hit[231]: begin
+ addr_hit[235]: begin
reg_rdata_next[31:0] = classd_timeout_cyc_qs;
end
- addr_hit[232]: begin
+ addr_hit[236]: begin
reg_rdata_next[31:0] = classd_phase0_cyc_qs;
end
- addr_hit[233]: begin
+ addr_hit[237]: begin
reg_rdata_next[31:0] = classd_phase1_cyc_qs;
end
- addr_hit[234]: begin
+ addr_hit[238]: begin
reg_rdata_next[31:0] = classd_phase2_cyc_qs;
end
- addr_hit[235]: begin
+ addr_hit[239]: begin
reg_rdata_next[31:0] = classd_phase3_cyc_qs;
end
- addr_hit[236]: begin
+ addr_hit[240]: begin
reg_rdata_next[31:0] = classd_esc_cnt_qs;
end
- addr_hit[237]: begin
+ addr_hit[241]: begin
reg_rdata_next[2:0] = classd_state_qs;
end
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index b606f60..3e63245 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -1418,7 +1418,9 @@
.rst_ni (rstmgr_aon_resets.rst_i2c2_n[rstmgr_pkg::Domain0Sel])
);
- pattgen u_pattgen (
+ pattgen #(
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[2:2])
+ ) u_pattgen (
// Output
.cio_pda0_tx_o (cio_pattgen_pda0_tx_d2p),
@@ -1433,6 +1435,9 @@
// Interrupt
.intr_done_ch0_o (intr_pattgen_done_ch0),
.intr_done_ch1_o (intr_pattgen_done_ch1),
+ // [2]: fatal_fault
+ .alert_tx_o ( alert_tx[2:2] ),
+ .alert_rx_i ( alert_rx[2:2] ),
// Inter-module signals
.tl_i(pattgen_tl_req),
@@ -1526,7 +1531,7 @@
);
otp_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[3:2]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[4:3]),
.MemInitFile(OtpCtrlMemInitFile),
.RndCnstLfsrSeed(RndCnstOtpCtrlLfsrSeed),
.RndCnstLfsrPerm(RndCnstOtpCtrlLfsrPerm)
@@ -1535,10 +1540,10 @@
// Interrupt
.intr_otp_operation_done_o (intr_otp_ctrl_otp_operation_done),
.intr_otp_error_o (intr_otp_ctrl_otp_error),
- // [2]: fatal_macro_error
- // [3]: fatal_check_error
- .alert_tx_o ( alert_tx[3:2] ),
- .alert_rx_i ( alert_rx[3:2] ),
+ // [3]: fatal_macro_error
+ // [4]: fatal_check_error
+ .alert_tx_o ( alert_tx[4:3] ),
+ .alert_rx_i ( alert_rx[4:3] ),
// Inter-module signals
.otp_ast_pwr_seq_o(otp_ctrl_otp_ast_pwr_seq_o),
@@ -1579,16 +1584,16 @@
);
lc_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[6:4]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[7:5]),
.RndCnstLcKeymgrDivInvalid(RndCnstLcCtrlLcKeymgrDivInvalid),
.RndCnstLcKeymgrDivTestDevRma(RndCnstLcCtrlLcKeymgrDivTestDevRma),
.RndCnstLcKeymgrDivProduction(RndCnstLcCtrlLcKeymgrDivProduction)
) u_lc_ctrl (
- // [4]: fatal_prog_error
- // [5]: fatal_state_error
- // [6]: fatal_bus_integ_error
- .alert_tx_o ( alert_tx[6:4] ),
- .alert_rx_i ( alert_rx[6:4] ),
+ // [5]: fatal_prog_error
+ // [6]: fatal_state_error
+ // [7]: fatal_bus_integ_error
+ .alert_tx_o ( alert_tx[7:5] ),
+ .alert_rx_i ( alert_rx[7:5] ),
// Inter-module signals
.jtag_i(pinmux_aon_lc_jtag_req),
@@ -1911,25 +1916,25 @@
);
sensor_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[17:7])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[18:8])
) u_sensor_ctrl_aon (
// Output
.cio_ast_debug_out_o (cio_sensor_ctrl_aon_ast_debug_out_d2p),
.cio_ast_debug_out_en_o (cio_sensor_ctrl_aon_ast_debug_out_en_d2p),
- // [7]: recov_as
- // [8]: recov_cg
- // [9]: recov_gd
- // [10]: recov_ts_hi
- // [11]: recov_ts_lo
- // [12]: recov_fla
- // [13]: recov_otp
- // [14]: recov_ot0
- // [15]: recov_ot1
- // [16]: recov_ot2
- // [17]: recov_ot3
- .alert_tx_o ( alert_tx[17:7] ),
- .alert_rx_i ( alert_rx[17:7] ),
+ // [8]: recov_as
+ // [9]: recov_cg
+ // [10]: recov_gd
+ // [11]: recov_ts_hi
+ // [12]: recov_ts_lo
+ // [13]: recov_fla
+ // [14]: recov_otp
+ // [15]: recov_ot0
+ // [16]: recov_ot1
+ // [17]: recov_ot2
+ // [18]: recov_ot3
+ .alert_tx_o ( alert_tx[18:8] ),
+ .alert_rx_i ( alert_rx[18:8] ),
// Inter-module signals
.ast_alert_i(sensor_ctrl_ast_alert_req_i),
@@ -1946,16 +1951,16 @@
);
sram_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[19:18]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[20:19]),
.RndCnstSramKey(RndCnstSramCtrlRetAonSramKey),
.RndCnstSramNonce(RndCnstSramCtrlRetAonSramNonce),
.RndCnstSramLfsrPerm(RndCnstSramCtrlRetAonSramLfsrPerm),
.InstrExec(SramCtrlRetAonInstrExec)
) u_sram_ctrl_ret_aon (
- // [18]: fatal_intg_error
- // [19]: fatal_parity_error
- .alert_tx_o ( alert_tx[19:18] ),
- .alert_rx_i ( alert_rx[19:18] ),
+ // [19]: fatal_intg_error
+ // [20]: fatal_parity_error
+ .alert_tx_o ( alert_tx[20:19] ),
+ .alert_rx_i ( alert_rx[20:19] ),
// Inter-module signals
.sram_otp_key_o(otp_ctrl_sram_otp_key_req[1]),
@@ -1980,7 +1985,7 @@
);
flash_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[23:20]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[24:21]),
.RndCnstAddrKey(RndCnstFlashCtrlAddrKey),
.RndCnstDataKey(RndCnstFlashCtrlDataKey),
.RndCnstLfsrSeed(RndCnstFlashCtrlLfsrSeed),
@@ -2003,12 +2008,12 @@
.intr_rd_lvl_o (intr_flash_ctrl_rd_lvl),
.intr_op_done_o (intr_flash_ctrl_op_done),
.intr_err_o (intr_flash_ctrl_err),
- // [20]: recov_err
- // [21]: recov_mp_err
- // [22]: recov_ecc_err
- // [23]: fatal_intg_err
- .alert_tx_o ( alert_tx[23:20] ),
- .alert_rx_i ( alert_rx[23:20] ),
+ // [21]: recov_err
+ // [22]: recov_mp_err
+ // [23]: recov_ecc_err
+ // [24]: fatal_intg_err
+ .alert_tx_o ( alert_tx[24:21] ),
+ .alert_rx_i ( alert_rx[24:21] ),
// Inter-module signals
.flash_o(flash_ctrl_flash_req),
@@ -2054,7 +2059,7 @@
);
aes #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[25:24]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[26:25]),
.AES192Enable(1'b1),
.Masking(AesMasking),
.SBoxImpl(AesSBoxImpl),
@@ -2067,10 +2072,10 @@
.RndCnstMaskingLfsrSeed(RndCnstAesMaskingLfsrSeed),
.RndCnstMskgChunkLfsrPerm(RndCnstAesMskgChunkLfsrPerm)
) u_aes (
- // [24]: recov_ctrl_update_err
- // [25]: fatal_fault
- .alert_tx_o ( alert_tx[25:24] ),
- .alert_rx_i ( alert_rx[25:24] ),
+ // [25]: recov_ctrl_update_err
+ // [26]: fatal_fault
+ .alert_tx_o ( alert_tx[26:25] ),
+ .alert_rx_i ( alert_rx[26:25] ),
// Inter-module signals
.idle_o(clkmgr_aon_idle[0]),
@@ -2088,16 +2093,16 @@
);
hmac #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[26:26])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[27:27])
) u_hmac (
// Interrupt
.intr_hmac_done_o (intr_hmac_hmac_done),
.intr_fifo_empty_o (intr_hmac_fifo_empty),
.intr_hmac_err_o (intr_hmac_hmac_err),
- // [26]: fatal_fault
- .alert_tx_o ( alert_tx[26:26] ),
- .alert_rx_i ( alert_rx[26:26] ),
+ // [27]: fatal_fault
+ .alert_tx_o ( alert_tx[27:27] ),
+ .alert_rx_i ( alert_rx[27:27] ),
// Inter-module signals
.idle_o(clkmgr_aon_idle[1]),
@@ -2110,7 +2115,7 @@
);
kmac #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[27:27]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[28:28]),
.EnMasking(KmacEnMasking),
.ReuseShare(KmacReuseShare)
) u_kmac (
@@ -2119,9 +2124,9 @@
.intr_kmac_done_o (intr_kmac_kmac_done),
.intr_fifo_empty_o (intr_kmac_fifo_empty),
.intr_kmac_err_o (intr_kmac_kmac_err),
- // [27]: fatal_fault
- .alert_tx_o ( alert_tx[27:27] ),
- .alert_rx_i ( alert_rx[27:27] ),
+ // [28]: fatal_fault
+ .alert_tx_o ( alert_tx[28:28] ),
+ .alert_rx_i ( alert_rx[28:28] ),
// Inter-module signals
.keymgr_key_i(keymgr_kmac_key),
@@ -2141,7 +2146,7 @@
);
keymgr #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[29:28]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[30:29]),
.RndCnstLfsrSeed(RndCnstKeymgrLfsrSeed),
.RndCnstLfsrPerm(RndCnstKeymgrLfsrPerm),
.RndCnstRandPerm(RndCnstKeymgrRandPerm),
@@ -2159,10 +2164,10 @@
// Interrupt
.intr_op_done_o (intr_keymgr_op_done),
- // [28]: fatal_fault_err
- // [29]: recov_operation_err
- .alert_tx_o ( alert_tx[29:28] ),
- .alert_rx_i ( alert_rx[29:28] ),
+ // [29]: fatal_fault_err
+ // [30]: recov_operation_err
+ .alert_tx_o ( alert_tx[30:29] ),
+ .alert_rx_i ( alert_rx[30:29] ),
// Inter-module signals
.edn_o(edn0_edn_req[0]),
@@ -2189,7 +2194,7 @@
);
csrng #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[30:30]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[31:31]),
.SBoxImpl(CsrngSBoxImpl)
) u_csrng (
@@ -2198,9 +2203,9 @@
.intr_cs_entropy_req_o (intr_csrng_cs_entropy_req),
.intr_cs_hw_inst_exc_o (intr_csrng_cs_hw_inst_exc),
.intr_cs_fatal_err_o (intr_csrng_cs_fatal_err),
- // [30]: fatal_alert
- .alert_tx_o ( alert_tx[30:30] ),
- .alert_rx_i ( alert_rx[30:30] ),
+ // [31]: fatal_alert
+ .alert_tx_o ( alert_tx[31:31] ),
+ .alert_rx_i ( alert_rx[31:31] ),
// Inter-module signals
.csrng_cmd_i(csrng_csrng_cmd_req),
@@ -2220,7 +2225,7 @@
);
entropy_src #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[32:31]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[33:32]),
.Stub(EntropySrcStub)
) u_entropy_src (
@@ -2229,10 +2234,10 @@
.intr_es_health_test_failed_o (intr_entropy_src_es_health_test_failed),
.intr_es_observe_fifo_ready_o (intr_entropy_src_es_observe_fifo_ready),
.intr_es_fatal_err_o (intr_entropy_src_es_fatal_err),
- // [31]: recov_alert
- // [32]: fatal_alert
- .alert_tx_o ( alert_tx[32:31] ),
- .alert_rx_i ( alert_rx[32:31] ),
+ // [32]: recov_alert
+ // [33]: fatal_alert
+ .alert_tx_o ( alert_tx[33:32] ),
+ .alert_rx_i ( alert_rx[33:32] ),
// Inter-module signals
.entropy_src_hw_if_i(csrng_entropy_src_hw_if_req),
@@ -2255,15 +2260,15 @@
);
edn #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[33:33])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[34:34])
) u_edn0 (
// Interrupt
.intr_edn_cmd_req_done_o (intr_edn0_edn_cmd_req_done),
.intr_edn_fatal_err_o (intr_edn0_edn_fatal_err),
- // [33]: fatal_alert
- .alert_tx_o ( alert_tx[33:33] ),
- .alert_rx_i ( alert_rx[33:33] ),
+ // [34]: fatal_alert
+ .alert_tx_o ( alert_tx[34:34] ),
+ .alert_rx_i ( alert_rx[34:34] ),
// Inter-module signals
.csrng_cmd_o(csrng_csrng_cmd_req[0]),
@@ -2279,15 +2284,15 @@
);
edn #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[34:34])
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[35:35])
) u_edn1 (
// Interrupt
.intr_edn_cmd_req_done_o (intr_edn1_edn_cmd_req_done),
.intr_edn_fatal_err_o (intr_edn1_edn_fatal_err),
- // [34]: fatal_alert
- .alert_tx_o ( alert_tx[34:34] ),
- .alert_rx_i ( alert_rx[34:34] ),
+ // [35]: fatal_alert
+ .alert_tx_o ( alert_tx[35:35] ),
+ .alert_rx_i ( alert_rx[35:35] ),
// Inter-module signals
.csrng_cmd_o(csrng_csrng_cmd_req[1]),
@@ -2303,16 +2308,16 @@
);
sram_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[36:35]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[37:36]),
.RndCnstSramKey(RndCnstSramCtrlMainSramKey),
.RndCnstSramNonce(RndCnstSramCtrlMainSramNonce),
.RndCnstSramLfsrPerm(RndCnstSramCtrlMainSramLfsrPerm),
.InstrExec(SramCtrlMainInstrExec)
) u_sram_ctrl_main (
- // [35]: fatal_intg_error
- // [36]: fatal_parity_error
- .alert_tx_o ( alert_tx[36:35] ),
- .alert_rx_i ( alert_rx[36:35] ),
+ // [36]: fatal_intg_error
+ // [37]: fatal_parity_error
+ .alert_tx_o ( alert_tx[37:36] ),
+ .alert_rx_i ( alert_rx[37:36] ),
// Inter-module signals
.sram_otp_key_o(otp_ctrl_sram_otp_key_req[0]),
@@ -2337,7 +2342,7 @@
);
otbn #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[38:37]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[39:38]),
.Stub(OtbnStub),
.RegFile(OtbnRegFile),
.RndCnstUrndLfsrSeed(RndCnstOtbnUrndLfsrSeed),
@@ -2346,10 +2351,10 @@
// Interrupt
.intr_done_o (intr_otbn_done),
- // [37]: fatal
- // [38]: recov
- .alert_tx_o ( alert_tx[38:37] ),
- .alert_rx_i ( alert_rx[38:37] ),
+ // [38]: fatal
+ // [39]: recov
+ .alert_tx_o ( alert_tx[39:38] ),
+ .alert_rx_i ( alert_rx[39:38] ),
// Inter-module signals
.edn_rnd_o(edn1_edn_req[0]),
@@ -2369,14 +2374,14 @@
);
rom_ctrl #(
- .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[39:39]),
+ .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[40:40]),
.BootRomInitFile(RomCtrlBootRomInitFile),
.RndCnstScrNonce(RndCnstRomCtrlScrNonce),
.RndCnstScrKey(RndCnstRomCtrlScrKey)
) u_rom_ctrl (
- // [39]: fatal
- .alert_tx_o ( alert_tx[39:39] ),
- .alert_rx_i ( alert_rx[39:39] ),
+ // [40]: fatal
+ .alert_tx_o ( alert_tx[40:40] ),
+ .alert_rx_i ( alert_rx[40:40] ),
// Inter-module signals
.rom_cfg_i(ast_rom_cfg),
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
index 7589f8b..55b650b 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
@@ -202,9 +202,10 @@
* `top_earlgrey_alert_peripheral_t`.
*/
const top_earlgrey_alert_peripheral_t
- top_earlgrey_alert_for_peripheral[40] = {
+ top_earlgrey_alert_for_peripheral[41] = {
[kTopEarlgreyAlertIdSpiHost0FatalFault] = kTopEarlgreyAlertPeripheralSpiHost0,
[kTopEarlgreyAlertIdSpiHost1FatalFault] = kTopEarlgreyAlertPeripheralSpiHost1,
+ [kTopEarlgreyAlertIdPattgenFatalFault] = kTopEarlgreyAlertPeripheralPattgen,
[kTopEarlgreyAlertIdOtpCtrlFatalMacroError] = kTopEarlgreyAlertPeripheralOtpCtrl,
[kTopEarlgreyAlertIdOtpCtrlFatalCheckError] = kTopEarlgreyAlertPeripheralOtpCtrl,
[kTopEarlgreyAlertIdLcCtrlFatalProgError] = kTopEarlgreyAlertPeripheralLcCtrl,
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index b9abb04..fc2c686 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -1090,23 +1090,24 @@
typedef enum top_earlgrey_alert_peripheral {
kTopEarlgreyAlertPeripheralSpiHost0 = 0, /**< spi_host0 */
kTopEarlgreyAlertPeripheralSpiHost1 = 1, /**< spi_host1 */
- kTopEarlgreyAlertPeripheralOtpCtrl = 2, /**< otp_ctrl */
- kTopEarlgreyAlertPeripheralLcCtrl = 3, /**< lc_ctrl */
- kTopEarlgreyAlertPeripheralSensorCtrlAon = 4, /**< sensor_ctrl_aon */
- kTopEarlgreyAlertPeripheralSramCtrlRetAon = 5, /**< sram_ctrl_ret_aon */
- kTopEarlgreyAlertPeripheralFlashCtrl = 6, /**< flash_ctrl */
- kTopEarlgreyAlertPeripheralAes = 7, /**< aes */
- kTopEarlgreyAlertPeripheralHmac = 8, /**< hmac */
- kTopEarlgreyAlertPeripheralKmac = 9, /**< kmac */
- kTopEarlgreyAlertPeripheralKeymgr = 10, /**< keymgr */
- kTopEarlgreyAlertPeripheralCsrng = 11, /**< csrng */
- kTopEarlgreyAlertPeripheralEntropySrc = 12, /**< entropy_src */
- kTopEarlgreyAlertPeripheralEdn0 = 13, /**< edn0 */
- kTopEarlgreyAlertPeripheralEdn1 = 14, /**< edn1 */
- kTopEarlgreyAlertPeripheralSramCtrlMain = 15, /**< sram_ctrl_main */
- kTopEarlgreyAlertPeripheralOtbn = 16, /**< otbn */
- kTopEarlgreyAlertPeripheralRomCtrl = 17, /**< rom_ctrl */
- kTopEarlgreyAlertPeripheralLast = 17, /**< \internal Final Alert peripheral */
+ kTopEarlgreyAlertPeripheralPattgen = 2, /**< pattgen */
+ kTopEarlgreyAlertPeripheralOtpCtrl = 3, /**< otp_ctrl */
+ kTopEarlgreyAlertPeripheralLcCtrl = 4, /**< lc_ctrl */
+ kTopEarlgreyAlertPeripheralSensorCtrlAon = 5, /**< sensor_ctrl_aon */
+ kTopEarlgreyAlertPeripheralSramCtrlRetAon = 6, /**< sram_ctrl_ret_aon */
+ kTopEarlgreyAlertPeripheralFlashCtrl = 7, /**< flash_ctrl */
+ kTopEarlgreyAlertPeripheralAes = 8, /**< aes */
+ kTopEarlgreyAlertPeripheralHmac = 9, /**< hmac */
+ kTopEarlgreyAlertPeripheralKmac = 10, /**< kmac */
+ kTopEarlgreyAlertPeripheralKeymgr = 11, /**< keymgr */
+ kTopEarlgreyAlertPeripheralCsrng = 12, /**< csrng */
+ kTopEarlgreyAlertPeripheralEntropySrc = 13, /**< entropy_src */
+ kTopEarlgreyAlertPeripheralEdn0 = 14, /**< edn0 */
+ kTopEarlgreyAlertPeripheralEdn1 = 15, /**< edn1 */
+ kTopEarlgreyAlertPeripheralSramCtrlMain = 16, /**< sram_ctrl_main */
+ kTopEarlgreyAlertPeripheralOtbn = 17, /**< otbn */
+ kTopEarlgreyAlertPeripheralRomCtrl = 18, /**< rom_ctrl */
+ kTopEarlgreyAlertPeripheralLast = 18, /**< \internal Final Alert peripheral */
} top_earlgrey_alert_peripheral_t;
/**
@@ -1118,45 +1119,46 @@
typedef enum top_earlgrey_alert_id {
kTopEarlgreyAlertIdSpiHost0FatalFault = 0, /**< spi_host0_fatal_fault */
kTopEarlgreyAlertIdSpiHost1FatalFault = 1, /**< spi_host1_fatal_fault */
- kTopEarlgreyAlertIdOtpCtrlFatalMacroError = 2, /**< otp_ctrl_fatal_macro_error */
- kTopEarlgreyAlertIdOtpCtrlFatalCheckError = 3, /**< otp_ctrl_fatal_check_error */
- kTopEarlgreyAlertIdLcCtrlFatalProgError = 4, /**< lc_ctrl_fatal_prog_error */
- kTopEarlgreyAlertIdLcCtrlFatalStateError = 5, /**< lc_ctrl_fatal_state_error */
- kTopEarlgreyAlertIdLcCtrlFatalBusIntegError = 6, /**< lc_ctrl_fatal_bus_integ_error */
- kTopEarlgreyAlertIdSensorCtrlAonRecovAs = 7, /**< sensor_ctrl_aon_recov_as */
- kTopEarlgreyAlertIdSensorCtrlAonRecovCg = 8, /**< sensor_ctrl_aon_recov_cg */
- kTopEarlgreyAlertIdSensorCtrlAonRecovGd = 9, /**< sensor_ctrl_aon_recov_gd */
- kTopEarlgreyAlertIdSensorCtrlAonRecovTsHi = 10, /**< sensor_ctrl_aon_recov_ts_hi */
- kTopEarlgreyAlertIdSensorCtrlAonRecovTsLo = 11, /**< sensor_ctrl_aon_recov_ts_lo */
- kTopEarlgreyAlertIdSensorCtrlAonRecovFla = 12, /**< sensor_ctrl_aon_recov_fla */
- kTopEarlgreyAlertIdSensorCtrlAonRecovOtp = 13, /**< sensor_ctrl_aon_recov_otp */
- kTopEarlgreyAlertIdSensorCtrlAonRecovOt0 = 14, /**< sensor_ctrl_aon_recov_ot0 */
- kTopEarlgreyAlertIdSensorCtrlAonRecovOt1 = 15, /**< sensor_ctrl_aon_recov_ot1 */
- kTopEarlgreyAlertIdSensorCtrlAonRecovOt2 = 16, /**< sensor_ctrl_aon_recov_ot2 */
- kTopEarlgreyAlertIdSensorCtrlAonRecovOt3 = 17, /**< sensor_ctrl_aon_recov_ot3 */
- kTopEarlgreyAlertIdSramCtrlRetAonFatalIntgError = 18, /**< sram_ctrl_ret_aon_fatal_intg_error */
- kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError = 19, /**< sram_ctrl_ret_aon_fatal_parity_error */
- kTopEarlgreyAlertIdFlashCtrlRecovErr = 20, /**< flash_ctrl_recov_err */
- kTopEarlgreyAlertIdFlashCtrlRecovMpErr = 21, /**< flash_ctrl_recov_mp_err */
- kTopEarlgreyAlertIdFlashCtrlRecovEccErr = 22, /**< flash_ctrl_recov_ecc_err */
- kTopEarlgreyAlertIdFlashCtrlFatalIntgErr = 23, /**< flash_ctrl_fatal_intg_err */
- kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 24, /**< aes_recov_ctrl_update_err */
- kTopEarlgreyAlertIdAesFatalFault = 25, /**< aes_fatal_fault */
- kTopEarlgreyAlertIdHmacFatalFault = 26, /**< hmac_fatal_fault */
- kTopEarlgreyAlertIdKmacFatalFault = 27, /**< kmac_fatal_fault */
- kTopEarlgreyAlertIdKeymgrFatalFaultErr = 28, /**< keymgr_fatal_fault_err */
- kTopEarlgreyAlertIdKeymgrRecovOperationErr = 29, /**< keymgr_recov_operation_err */
- kTopEarlgreyAlertIdCsrngFatalAlert = 30, /**< csrng_fatal_alert */
- kTopEarlgreyAlertIdEntropySrcRecovAlert = 31, /**< entropy_src_recov_alert */
- kTopEarlgreyAlertIdEntropySrcFatalAlert = 32, /**< entropy_src_fatal_alert */
- kTopEarlgreyAlertIdEdn0FatalAlert = 33, /**< edn0_fatal_alert */
- kTopEarlgreyAlertIdEdn1FatalAlert = 34, /**< edn1_fatal_alert */
- kTopEarlgreyAlertIdSramCtrlMainFatalIntgError = 35, /**< sram_ctrl_main_fatal_intg_error */
- kTopEarlgreyAlertIdSramCtrlMainFatalParityError = 36, /**< sram_ctrl_main_fatal_parity_error */
- kTopEarlgreyAlertIdOtbnFatal = 37, /**< otbn_fatal */
- kTopEarlgreyAlertIdOtbnRecov = 38, /**< otbn_recov */
- kTopEarlgreyAlertIdRomCtrlFatal = 39, /**< rom_ctrl_fatal */
- kTopEarlgreyAlertIdLast = 39, /**< \internal The Last Valid Alert ID. */
+ kTopEarlgreyAlertIdPattgenFatalFault = 2, /**< pattgen_fatal_fault */
+ kTopEarlgreyAlertIdOtpCtrlFatalMacroError = 3, /**< otp_ctrl_fatal_macro_error */
+ kTopEarlgreyAlertIdOtpCtrlFatalCheckError = 4, /**< otp_ctrl_fatal_check_error */
+ kTopEarlgreyAlertIdLcCtrlFatalProgError = 5, /**< lc_ctrl_fatal_prog_error */
+ kTopEarlgreyAlertIdLcCtrlFatalStateError = 6, /**< lc_ctrl_fatal_state_error */
+ kTopEarlgreyAlertIdLcCtrlFatalBusIntegError = 7, /**< lc_ctrl_fatal_bus_integ_error */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovAs = 8, /**< sensor_ctrl_aon_recov_as */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovCg = 9, /**< sensor_ctrl_aon_recov_cg */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovGd = 10, /**< sensor_ctrl_aon_recov_gd */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovTsHi = 11, /**< sensor_ctrl_aon_recov_ts_hi */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovTsLo = 12, /**< sensor_ctrl_aon_recov_ts_lo */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovFla = 13, /**< sensor_ctrl_aon_recov_fla */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovOtp = 14, /**< sensor_ctrl_aon_recov_otp */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovOt0 = 15, /**< sensor_ctrl_aon_recov_ot0 */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovOt1 = 16, /**< sensor_ctrl_aon_recov_ot1 */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovOt2 = 17, /**< sensor_ctrl_aon_recov_ot2 */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovOt3 = 18, /**< sensor_ctrl_aon_recov_ot3 */
+ kTopEarlgreyAlertIdSramCtrlRetAonFatalIntgError = 19, /**< sram_ctrl_ret_aon_fatal_intg_error */
+ kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError = 20, /**< sram_ctrl_ret_aon_fatal_parity_error */
+ kTopEarlgreyAlertIdFlashCtrlRecovErr = 21, /**< flash_ctrl_recov_err */
+ kTopEarlgreyAlertIdFlashCtrlRecovMpErr = 22, /**< flash_ctrl_recov_mp_err */
+ kTopEarlgreyAlertIdFlashCtrlRecovEccErr = 23, /**< flash_ctrl_recov_ecc_err */
+ kTopEarlgreyAlertIdFlashCtrlFatalIntgErr = 24, /**< flash_ctrl_fatal_intg_err */
+ kTopEarlgreyAlertIdAesRecovCtrlUpdateErr = 25, /**< aes_recov_ctrl_update_err */
+ kTopEarlgreyAlertIdAesFatalFault = 26, /**< aes_fatal_fault */
+ kTopEarlgreyAlertIdHmacFatalFault = 27, /**< hmac_fatal_fault */
+ kTopEarlgreyAlertIdKmacFatalFault = 28, /**< kmac_fatal_fault */
+ kTopEarlgreyAlertIdKeymgrFatalFaultErr = 29, /**< keymgr_fatal_fault_err */
+ kTopEarlgreyAlertIdKeymgrRecovOperationErr = 30, /**< keymgr_recov_operation_err */
+ kTopEarlgreyAlertIdCsrngFatalAlert = 31, /**< csrng_fatal_alert */
+ kTopEarlgreyAlertIdEntropySrcRecovAlert = 32, /**< entropy_src_recov_alert */
+ kTopEarlgreyAlertIdEntropySrcFatalAlert = 33, /**< entropy_src_fatal_alert */
+ kTopEarlgreyAlertIdEdn0FatalAlert = 34, /**< edn0_fatal_alert */
+ kTopEarlgreyAlertIdEdn1FatalAlert = 35, /**< edn1_fatal_alert */
+ kTopEarlgreyAlertIdSramCtrlMainFatalIntgError = 36, /**< sram_ctrl_main_fatal_intg_error */
+ kTopEarlgreyAlertIdSramCtrlMainFatalParityError = 37, /**< sram_ctrl_main_fatal_parity_error */
+ kTopEarlgreyAlertIdOtbnFatal = 38, /**< otbn_fatal */
+ kTopEarlgreyAlertIdOtbnRecov = 39, /**< otbn_recov */
+ kTopEarlgreyAlertIdRomCtrlFatal = 40, /**< rom_ctrl_fatal */
+ kTopEarlgreyAlertIdLast = 40, /**< \internal The Last Valid Alert ID. */
} top_earlgrey_alert_id_t;
/**
@@ -1166,7 +1168,7 @@
* `top_earlgrey_alert_peripheral_t`.
*/
extern const top_earlgrey_alert_peripheral_t
- top_earlgrey_alert_for_peripheral[40];
+ top_earlgrey_alert_for_peripheral[41];
#define PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET 2
