[top] Auto generate files
Signed-off-by: Timothy Chen <timothytim@google.com>
[top] Auto generate files
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index b0c53c0..27054da 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -27,7 +27,7 @@
{
hier_paths:
{
- top: clkmgr_clocks.
+ top: clkmgr_aon_clocks.
ext: ""
}
srcs:
@@ -127,8 +127,8 @@
clocks:
{
clk_io_div4_secure: io_div4
- clk_main_secure: main
clk_aon_secure: aon
+ clk_main_secure: main
}
}
{
@@ -170,7 +170,7 @@
{
hier_paths:
{
- top: rstmgr_resets.
+ top: rstmgr_aon_resets.
ext: ""
}
nodes:
@@ -446,13 +446,13 @@
}
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40000000
clock_group: secure
clock_connections:
{
- clk_i: clkmgr_clocks.clk_io_div4_secure
+ clk_i: clkmgr_aon_clocks.clk_io_div4_secure
}
domain: "0"
size: 0x1000
@@ -605,13 +605,13 @@
}
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40010000
clock_group: secure
clock_connections:
{
- clk_i: clkmgr_clocks.clk_io_div4_secure
+ clk_i: clkmgr_aon_clocks.clk_io_div4_secure
}
domain: "0"
size: 0x1000
@@ -764,13 +764,13 @@
}
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40020000
clock_group: secure
clock_connections:
{
- clk_i: clkmgr_clocks.clk_io_div4_secure
+ clk_i: clkmgr_aon_clocks.clk_io_div4_secure
}
domain: "0"
size: 0x1000
@@ -923,13 +923,13 @@
}
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40030000
clock_group: secure
clock_connections:
{
- clk_i: clkmgr_clocks.clk_io_div4_secure
+ clk_i: clkmgr_aon_clocks.clk_io_div4_secure
}
domain: "0"
size: 0x1000
@@ -1083,12 +1083,12 @@
clock_group: peri
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40040000
clock_connections:
{
- clk_i: clkmgr_clocks.clk_io_div4_peri
+ clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
domain: "0"
size: 0x1000
@@ -1151,12 +1151,12 @@
clock_group: peri
reset_connections:
{
- rst_ni: rstmgr_resets.rst_spi_device_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_spi_device_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40050000
clock_connections:
{
- clk_i: clkmgr_clocks.clk_io_div4_peri
+ clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
domain: "0"
size: 0x1000
@@ -1296,12 +1296,12 @@
clock_group: peri
reset_connections:
{
- rst_ni: rstmgr_resets.rst_i2c0_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_i2c0_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40080000
clock_connections:
{
- clk_i: clkmgr_clocks.clk_io_div4_peri
+ clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
domain: "0"
size: 0x1000
@@ -1549,12 +1549,12 @@
clock_group: peri
reset_connections:
{
- rst_ni: rstmgr_resets.rst_i2c1_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_i2c1_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40090000
clock_connections:
{
- clk_i: clkmgr_clocks.clk_io_div4_peri
+ clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
domain: "0"
size: 0x1000
@@ -1802,12 +1802,12 @@
clock_group: peri
reset_connections:
{
- rst_ni: rstmgr_resets.rst_i2c2_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_i2c2_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x400A0000
clock_connections:
{
- clk_i: clkmgr_clocks.clk_io_div4_peri
+ clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
domain: "0"
size: 0x1000
@@ -2055,12 +2055,12 @@
clock_group: peri
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x400E0000
clock_connections:
{
- clk_i: clkmgr_clocks.clk_io_div4_peri
+ clk_i: clkmgr_aon_clocks.clk_io_div4_peri
}
domain: "0"
size: 0x1000
@@ -2150,12 +2150,12 @@
clock_group: timers
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x40100000
clock_connections:
{
- clk_i: clkmgr_clocks.clk_io_div4_timers
+ clk_i: clkmgr_aon_clocks.clk_io_div4_timers
}
domain: "0"
size: 0x1000
@@ -2195,2020 +2195,6 @@
]
}
{
- name: sensor_ctrl
- type: sensor_ctrl
- clock_srcs:
- {
- clk_i: io_div4
- }
- clock_group: secure
- clock_reset_export:
- [
- ast
- ]
- reset_connections:
- {
- rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]
- }
- domain: Aon
- base_addr: 0x40110000
- top_only: "true"
- clock_connections:
- {
- clk_i: clkmgr_clocks.clk_io_div4_secure
- }
- size: 0x1000
- bus_device: tlul
- bus_host: none
- available_input_list: []
- available_output_list: []
- available_inout_list: []
- param_list: []
- interrupt_list: []
- alert_list:
- [
- {
- name: recov_as
- width: 1
- bits: "0"
- bitinfo:
- [
- 1
- 1
- 0
- ]
- type: alert
- async: 0
- }
- {
- name: recov_cg
- width: 1
- bits: "1"
- bitinfo:
- [
- 2
- 1
- 1
- ]
- type: alert
- async: 0
- }
- {
- name: recov_gd
- width: 1
- bits: "2"
- bitinfo:
- [
- 4
- 1
- 2
- ]
- type: alert
- async: 0
- }
- {
- name: recov_ts_hi
- width: 1
- bits: "3"
- bitinfo:
- [
- 8
- 1
- 3
- ]
- type: alert
- async: 0
- }
- {
- name: recov_ts_lo
- width: 1
- bits: "4"
- bitinfo:
- [
- 16
- 1
- 4
- ]
- type: alert
- async: 0
- }
- {
- name: recov_ls
- width: 1
- bits: "5"
- bitinfo:
- [
- 32
- 1
- 5
- ]
- type: alert
- async: 0
- }
- {
- name: recov_ot
- width: 1
- bits: "6"
- bitinfo:
- [
- 64
- 1
- 6
- ]
- type: alert
- async: 0
- }
- ]
- wakeup_list: []
- reset_request_list: []
- scan: "false"
- scan_reset: "false"
- inter_signal_list:
- [
- {
- struct: ast_alert
- type: req_rsp
- name: ast_alert
- act: rsp
- package: ast_wrapper_pkg
- inst_name: sensor_ctrl
- width: 1
- default: ""
- external: true
- top_signame: sensor_ctrl_ast_alert
- index: -1
- }
- {
- struct: ast_status
- type: uni
- name: ast_status
- act: rcv
- package: ast_wrapper_pkg
- inst_name: sensor_ctrl
- width: 1
- default: ""
- external: true
- top_signame: sensor_ctrl_ast_status
- index: -1
- }
- {
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- name: tl
- inst_name: sensor_ctrl
- width: 1
- default: ""
- top_signame: sensor_ctrl_tl
- index: -1
- }
- ]
- }
- {
- name: otp_ctrl
- type: otp_ctrl
- clock_srcs:
- {
- clk_i: io_div4
- clk_edn_i: main
- }
- clock_group: timers
- reset_connections:
- {
- rst_ni: rstmgr_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]
- rst_edn_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
- }
- base_addr: 0x40130000
- clock_connections:
- {
- clk_i: clkmgr_clocks.clk_io_div4_timers
- clk_edn_i: clkmgr_clocks.clk_main_timers
- }
- domain: "0"
- size: 0x4000
- bus_device: tlul
- bus_host: none
- available_input_list: []
- available_output_list: []
- available_inout_list: []
- param_list:
- [
- {
- name: RndCnstLfsrSeed
- desc: Compile-time random bits for initial LFSR seed
- type: otp_ctrl_pkg::lfsr_seed_t
- randcount: "40"
- randtype: data
- local: "false"
- default: 0xf45def7861
- expose: "false"
- name_top: RndCnstOtpCtrlLfsrSeed
- randwidth: 40
- }
- {
- name: RndCnstLfsrPerm
- desc: Compile-time random permutation for LFSR output
- type: otp_ctrl_pkg::lfsr_perm_t
- randcount: "40"
- randtype: perm
- local: "false"
- default: 0x5d294061e29a7c404f4593035a19097666e37072064153623855022d39e0
- expose: "false"
- name_top: RndCnstOtpCtrlLfsrPerm
- randwidth: 240
- }
- ]
- interrupt_list:
- [
- {
- name: otp_operation_done
- width: 1
- bits: "0"
- bitinfo:
- [
- 1
- 1
- 0
- ]
- type: interrupt
- }
- {
- name: otp_error
- width: 1
- bits: "1"
- bitinfo:
- [
- 2
- 1
- 1
- ]
- type: interrupt
- }
- ]
- alert_list:
- [
- {
- name: fatal_macro_error
- width: 1
- bits: "0"
- bitinfo:
- [
- 1
- 1
- 0
- ]
- type: alert
- async: 0
- }
- {
- name: fatal_check_error
- width: 1
- bits: "1"
- bitinfo:
- [
- 2
- 1
- 1
- ]
- type: alert
- async: 0
- }
- ]
- wakeup_list: []
- reset_request_list: []
- scan: "false"
- scan_reset: "false"
- inter_signal_list:
- [
- {
- struct: otp_ast_req
- type: uni
- name: otp_ast_pwr_seq
- act: req
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- width: 1
- external: true
- top_signame: otp_ctrl_otp_ast_pwr_seq
- index: -1
- }
- {
- struct: otp_ast_rsp
- type: uni
- name: otp_ast_pwr_seq_h
- act: rcv
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- width: 1
- external: true
- top_signame: otp_ctrl_otp_ast_pwr_seq_h
- index: -1
- }
- {
- struct: edn
- type: req_rsp
- name: edn
- act: req
- package: edn_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: pwr_otp
- type: req_rsp
- name: pwr_otp
- act: rsp
- default: "'0"
- package: pwrmgr_pkg
- inst_name: otp_ctrl
- width: 1
- top_signame: pwrmgr_pwr_otp
- index: -1
- }
- {
- struct: lc_otp_program
- type: req_rsp
- name: lc_otp_program
- act: rsp
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- width: 1
- top_signame: lc_ctrl_lc_otp_program
- index: -1
- }
- {
- struct: lc_otp_token
- type: req_rsp
- name: lc_otp_token
- act: rsp
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- width: 1
- top_signame: lc_ctrl_lc_otp_token
- index: -1
- }
- {
- struct: otp_lc_data
- type: uni
- name: otp_lc_data
- act: req
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- width: 1
- top_type: broadcast
- top_signame: otp_ctrl_otp_lc_data
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_escalate_en
- act: rcv
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: otp_ctrl
- width: 1
- top_signame: lc_ctrl_lc_escalate_en
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_creator_seed_sw_rw_en
- act: rcv
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: otp_ctrl
- width: 1
- top_signame: lc_ctrl_lc_creator_seed_sw_rw_en
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_seed_hw_rd_en
- act: rcv
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: otp_ctrl
- width: 1
- top_signame: lc_ctrl_lc_seed_hw_rd_en
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_dft_en
- act: rcv
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: otp_ctrl
- width: 1
- top_signame: lc_ctrl_lc_dft_en
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_check_byp_en
- act: rcv
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: otp_ctrl
- width: 1
- top_signame: lc_ctrl_lc_check_byp_en
- index: -1
- }
- {
- struct: otp_keymgr_key
- type: uni
- name: otp_keymgr_key
- act: req
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- width: 1
- top_type: broadcast
- top_signame: otp_ctrl_otp_keymgr_key
- index: -1
- }
- {
- struct: flash_otp_key
- type: req_rsp
- name: flash_otp_key
- act: rsp
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- width: 1
- top_signame: flash_ctrl_otp
- index: -1
- }
- {
- struct: sram_otp_key
- width: 2
- type: req_rsp
- name: sram_otp_key
- act: rsp
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- top_signame: otp_ctrl_sram_otp_key
- index: -1
- }
- {
- struct: otbn_otp_key
- type: req_rsp
- name: otbn_otp_key
- act: rsp
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: otp_ctrl
- index: -1
- }
- {
- struct: otp_hw_cfg
- type: uni
- name: otp_hw_cfg
- act: req
- default: "'0"
- package: otp_ctrl_part_pkg
- inst_name: otp_ctrl
- width: 1
- top_type: broadcast
- top_signame: otp_ctrl_otp_hw_cfg
- index: -1
- }
- {
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- name: tl
- inst_name: otp_ctrl
- width: 1
- default: ""
- top_signame: otp_ctrl_tl
- index: -1
- }
- ]
- }
- {
- name: lc_ctrl
- type: lc_ctrl
- clock_srcs:
- {
- clk_i: io_div4
- }
- clock_group: timers
- reset_connections:
- {
- rst_ni: rstmgr_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]
- }
- base_addr: 0x40140000
- clock_connections:
- {
- clk_i: clkmgr_clocks.clk_io_div4_timers
- }
- domain: "0"
- size: 0x1000
- bus_device: tlul
- bus_host: none
- available_input_list: []
- available_output_list: []
- available_inout_list: []
- param_list:
- [
- {
- name: RndCnstLcKeymgrDivInvalid
- desc: Compile-time random bits for lc state group diversification value
- type: lc_ctrl_pkg::lc_keymgr_div_t
- randcount: "64"
- randtype: data
- local: "false"
- default: 0xf4c3471c5def7861
- expose: "false"
- name_top: RndCnstLcCtrlLcKeymgrDivInvalid
- randwidth: 64
- }
- {
- name: RndCnstLcKeymgrDivTestDevRma
- desc: Compile-time random bits for lc state group diversification value
- type: lc_ctrl_pkg::lc_keymgr_div_t
- randcount: "64"
- randtype: data
- local: "false"
- default: 0x83d0550b80e84eb1
- expose: "false"
- name_top: RndCnstLcCtrlLcKeymgrDivTestDevRma
- randwidth: 64
- }
- {
- name: RndCnstLcKeymgrDivProduction
- desc: Compile-time random bits for lc state group diversification value
- type: lc_ctrl_pkg::lc_keymgr_div_t
- randcount: "64"
- randtype: data
- local: "false"
- default: 0x2d73930d4cac3785
- expose: "false"
- name_top: RndCnstLcCtrlLcKeymgrDivProduction
- randwidth: 64
- }
- ]
- interrupt_list: []
- alert_list:
- [
- {
- name: fatal_prog_error
- width: 1
- bits: "0"
- bitinfo:
- [
- 1
- 1
- 0
- ]
- type: alert
- async: 0
- }
- {
- name: fatal_state_error
- width: 1
- bits: "1"
- bitinfo:
- [
- 2
- 1
- 1
- ]
- type: alert
- async: 0
- }
- ]
- wakeup_list: []
- reset_request_list: []
- scan: "true"
- scan_reset: "false"
- inter_signal_list:
- [
- {
- struct: jtag
- type: req_rsp
- name: jtag
- act: rsp
- package: jtag_pkg
- inst_name: lc_ctrl
- index: -1
- }
- {
- struct: esc_tx
- type: uni
- name: esc_wipe_secrets_tx
- act: rcv
- package: prim_esc_pkg
- inst_name: lc_ctrl
- width: 1
- default: ""
- top_signame: alert_handler_esc_tx
- index: 1
- }
- {
- struct: esc_rx
- type: uni
- name: esc_wipe_secrets_rx
- act: req
- package: prim_esc_pkg
- inst_name: lc_ctrl
- width: 1
- default: ""
- top_signame: alert_handler_esc_rx
- index: 1
- }
- {
- struct: esc_tx
- type: uni
- name: esc_scrap_state_tx
- act: rcv
- package: prim_esc_pkg
- inst_name: lc_ctrl
- width: 1
- default: ""
- top_signame: alert_handler_esc_tx
- index: 2
- }
- {
- struct: esc_rx
- type: uni
- name: esc_scrap_state_rx
- act: req
- package: prim_esc_pkg
- inst_name: lc_ctrl
- width: 1
- default: ""
- top_signame: alert_handler_esc_rx
- index: 2
- }
- {
- struct: pwr_lc
- type: req_rsp
- name: pwr_lc
- act: rsp
- package: pwrmgr_pkg
- inst_name: lc_ctrl
- width: 1
- default: ""
- top_signame: pwrmgr_pwr_lc
- index: -1
- }
- {
- struct: otp_lc_data
- type: uni
- name: otp_lc_data
- act: rcv
- default: otp_ctrl_pkg::OTP_LC_DATA_DEFAULT
- package: otp_ctrl_pkg
- inst_name: lc_ctrl
- width: 1
- top_signame: otp_ctrl_otp_lc_data
- index: -1
- }
- {
- struct: lc_otp_program
- type: req_rsp
- name: lc_otp_program
- act: req
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: lc_ctrl
- width: 1
- top_signame: lc_ctrl_lc_otp_program
- index: -1
- }
- {
- struct: lc_otp_token
- type: req_rsp
- name: lc_otp_token
- act: req
- default: "'0"
- package: otp_ctrl_pkg
- inst_name: lc_ctrl
- width: 1
- top_signame: lc_ctrl_lc_otp_token
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_dft_en
- act: req
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: lc_ctrl
- width: 1
- top_type: broadcast
- top_signame: lc_ctrl_lc_dft_en
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_nvm_debug_en
- act: req
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: lc_ctrl
- width: 1
- top_type: broadcast
- top_signame: lc_ctrl_lc_nvm_debug_en
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_hw_debug_en
- act: req
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: lc_ctrl
- width: 1
- top_type: broadcast
- top_signame: lc_ctrl_lc_hw_debug_en
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_cpu_en
- act: req
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: lc_ctrl
- width: 1
- top_type: broadcast
- top_signame: lc_ctrl_lc_cpu_en
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_keymgr_en
- act: req
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: lc_ctrl
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_escalate_en
- act: req
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: lc_ctrl
- width: 1
- top_type: broadcast
- top_signame: lc_ctrl_lc_escalate_en
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_clk_byp_req
- act: req
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: lc_ctrl
- width: 1
- top_type: broadcast
- top_signame: lc_ctrl_lc_clk_byp_req
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_clk_byp_ack
- act: rcv
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: lc_ctrl
- width: 1
- top_type: broadcast
- top_signame: lc_ctrl_lc_clk_byp_ack
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_flash_rma_req
- act: req
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: lc_ctrl
- width: 1
- top_signame: flash_ctrl_rma_req
- index: -1
- }
- {
- struct: lc_flash_rma_seed
- type: uni
- name: lc_flash_rma_seed
- act: req
- default: "'0"
- package: lc_ctrl_pkg
- inst_name: lc_ctrl
- width: 1
- top_signame: flash_ctrl_rma_seed
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_flash_rma_ack
- act: rcv
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: lc_ctrl
- width: 1
- top_signame: flash_ctrl_rma_ack
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_check_byp_en
- act: req
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: lc_ctrl
- width: 1
- top_type: broadcast
- top_signame: lc_ctrl_lc_check_byp_en
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_creator_seed_sw_rw_en
- act: req
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: lc_ctrl
- width: 1
- top_type: broadcast
- top_signame: lc_ctrl_lc_creator_seed_sw_rw_en
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_owner_seed_sw_rw_en
- act: req
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: lc_ctrl
- width: 1
- top_type: broadcast
- top_signame: lc_ctrl_lc_owner_seed_sw_rw_en
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_iso_part_sw_rd_en
- act: req
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: lc_ctrl
- width: 1
- top_type: broadcast
- top_signame: lc_ctrl_lc_iso_part_sw_rd_en
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_iso_part_sw_wr_en
- act: req
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: lc_ctrl
- width: 1
- top_type: broadcast
- top_signame: lc_ctrl_lc_iso_part_sw_wr_en
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_seed_hw_rd_en
- act: req
- default: lc_ctrl_pkg::Off
- package: lc_ctrl_pkg
- inst_name: lc_ctrl
- width: 1
- top_type: broadcast
- top_signame: lc_ctrl_lc_seed_hw_rd_en
- index: -1
- }
- {
- struct: lc_keymgr_div
- type: uni
- name: lc_keymgr_div
- act: req
- default: "'0"
- package: lc_ctrl_pkg
- inst_name: lc_ctrl
- width: 1
- top_type: broadcast
- top_signame: lc_ctrl_lc_keymgr_div
- index: -1
- }
- {
- struct: otp_hw_cfg
- type: uni
- name: otp_hw_cfg
- act: rcv
- default: "'0"
- package: otp_ctrl_part_pkg
- inst_name: lc_ctrl
- width: 1
- top_signame: otp_ctrl_otp_hw_cfg
- index: -1
- }
- {
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- name: tl
- inst_name: lc_ctrl
- width: 1
- default: ""
- top_signame: lc_ctrl_tl
- index: -1
- }
- ]
- }
- {
- name: alert_handler
- type: alert_handler
- clock_srcs:
- {
- clk_i: io_div4
- }
- clock_group: timers
- reset_connections:
- {
- rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
- }
- base_addr: 0x40150000
- generated: "true"
- localparam:
- {
- EscCntDw: 32
- AccuCntDw: 16
- LfsrSeed: 0x7FFFFFFF
- }
- clock_connections:
- {
- clk_i: clkmgr_clocks.clk_io_div4_timers
- }
- domain: "0"
- size: 0x1000
- bus_device: tlul
- bus_host: none
- available_input_list: []
- available_output_list: []
- available_inout_list: []
- param_list:
- [
- {
- name: RndCnstLfsrSeed
- desc: Compile-time random bits for initial LFSR seed
- type: alert_pkg::lfsr_seed_t
- randcount: "32"
- randtype: data
- local: "false"
- default: 0x5def7861
- expose: "false"
- name_top: RndCnstAlertHandlerLfsrSeed
- randwidth: 32
- }
- {
- name: RndCnstLfsrPerm
- desc: Compile-time random permutation for LFSR output
- type: alert_pkg::lfsr_perm_t
- randcount: "32"
- randtype: perm
- local: "false"
- default: 0x5f00c4cafd73fc4ac479a61068375f38956d84b3
- expose: "false"
- name_top: RndCnstAlertHandlerLfsrPerm
- randwidth: 160
- }
- ]
- interrupt_list:
- [
- {
- name: classa
- width: 1
- bits: "0"
- bitinfo:
- [
- 1
- 1
- 0
- ]
- type: interrupt
- }
- {
- name: classb
- width: 1
- bits: "1"
- bitinfo:
- [
- 2
- 1
- 1
- ]
- type: interrupt
- }
- {
- name: classc
- width: 1
- bits: "2"
- bitinfo:
- [
- 4
- 1
- 2
- ]
- type: interrupt
- }
- {
- name: classd
- width: 1
- bits: "3"
- bitinfo:
- [
- 8
- 1
- 3
- ]
- type: interrupt
- }
- ]
- alert_list: []
- wakeup_list: []
- reset_request_list: []
- scan: "false"
- scan_reset: "false"
- inter_signal_list:
- [
- {
- struct: alert_crashdump
- type: uni
- name: crashdump
- act: req
- package: alert_pkg
- inst_name: alert_handler
- width: 1
- default: ""
- top_type: broadcast
- top_signame: alert_handler_crashdump
- index: -1
- }
- {
- struct: logic
- type: uni
- name: entropy
- default: " 1'b0"
- act: rcv
- inst_name: alert_handler
- index: -1
- }
- {
- struct: esc_rx
- type: uni
- name: esc_rx
- act: rcv
- width: 4
- package: prim_esc_pkg
- inst_name: alert_handler
- default: ""
- top_type: one-to-N
- top_signame: alert_handler_esc_rx
- index: -1
- }
- {
- struct: esc_tx
- type: uni
- name: esc_tx
- act: req
- width: 4
- package: prim_esc_pkg
- inst_name: alert_handler
- default: ""
- top_type: one-to-N
- top_signame: alert_handler_esc_tx
- index: -1
- }
- {
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- name: tl
- inst_name: alert_handler
- width: 1
- default: ""
- top_signame: alert_handler_tl
- index: -1
- }
- ]
- }
- {
- name: nmi_gen
- type: nmi_gen
- clock_srcs:
- {
- clk_i: io_div4
- }
- clock_group: timers
- reset_connections:
- {
- rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
- }
- base_addr: 0x40160000
- clock_connections:
- {
- clk_i: clkmgr_clocks.clk_io_div4_timers
- }
- domain: "0"
- size: 0x1000
- bus_device: tlul
- bus_host: none
- available_input_list: []
- available_output_list: []
- available_inout_list: []
- param_list: []
- interrupt_list:
- [
- {
- name: esc0
- width: 1
- bits: "0"
- bitinfo:
- [
- 1
- 1
- 0
- ]
- type: interrupt
- }
- {
- name: esc1
- width: 1
- bits: "1"
- bitinfo:
- [
- 2
- 1
- 1
- ]
- type: interrupt
- }
- {
- name: esc2
- width: 1
- bits: "2"
- bitinfo:
- [
- 4
- 1
- 2
- ]
- type: interrupt
- }
- ]
- alert_list: []
- wakeup_list: []
- reset_request_list:
- [
- {
- name: nmi_rst_req
- }
- ]
- scan: "false"
- scan_reset: "false"
- inter_signal_list:
- [
- {
- struct: logic
- type: uni
- name: nmi_rst_req
- act: req
- package: ""
- default: 1'b0
- inst_name: nmi_gen
- width: 1
- top_signame: pwrmgr_rstreqs
- index: -1
- }
- {
- struct: esc_tx
- type: uni
- name: esc_tx
- act: rcv
- package: prim_esc_pkg
- default: "{3{prim_esc_pkg::ESC_TX_DEFAULT}}"
- inst_name: nmi_gen
- index: -1
- }
- {
- struct: esc_rx
- type: uni
- name: esc_rx
- act: req
- package: prim_esc_pkg
- inst_name: nmi_gen
- index: -1
- }
- {
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- name: tl
- inst_name: nmi_gen
- width: 1
- default: ""
- top_signame: nmi_gen_tl
- index: -1
- }
- ]
- }
- {
- name: pwrmgr
- type: pwrmgr
- clock_srcs:
- {
- clk_i: io_div4
- clk_slow_i: aon
- }
- clock_group: powerup
- reset_connections:
- {
- rst_ni: rstmgr_resets.rst_por_n[rstmgr_pkg::DomainAonSel]
- rst_slow_ni: rstmgr_resets.rst_por_aon_n[rstmgr_pkg::DomainAonSel]
- }
- domain: Aon
- base_addr: 0x40400000
- generated: "true"
- clock_connections:
- {
- clk_i: clkmgr_clocks.clk_io_div4_powerup
- clk_slow_i: clkmgr_clocks.clk_aon_powerup
- }
- size: 0x1000
- bus_device: tlul
- bus_host: none
- available_input_list: []
- available_output_list: []
- available_inout_list: []
- param_list: []
- interrupt_list:
- [
- {
- name: wakeup
- width: 1
- bits: "0"
- bitinfo:
- [
- 1
- 1
- 0
- ]
- type: interrupt
- }
- ]
- alert_list: []
- wakeup_list: []
- reset_request_list: []
- scan: "false"
- scan_reset: "false"
- inter_signal_list:
- [
- {
- struct: pwr_ast
- type: req_rsp
- name: pwr_ast
- act: req
- package: pwrmgr_pkg
- inst_name: pwrmgr
- width: 1
- default: ""
- external: true
- top_signame: pwrmgr_pwr_ast
- index: -1
- }
- {
- struct: pwr_rst
- type: req_rsp
- name: pwr_rst
- act: req
- package: pwrmgr_pkg
- inst_name: pwrmgr
- width: 1
- default: ""
- top_signame: pwrmgr_pwr_rst
- index: -1
- }
- {
- struct: pwr_clk
- type: req_rsp
- name: pwr_clk
- act: req
- package: pwrmgr_pkg
- inst_name: pwrmgr
- width: 1
- default: ""
- top_signame: pwrmgr_pwr_clk
- index: -1
- }
- {
- struct: pwr_otp
- type: req_rsp
- name: pwr_otp
- act: req
- package: pwrmgr_pkg
- inst_name: pwrmgr
- width: 1
- default: ""
- top_signame: pwrmgr_pwr_otp
- index: -1
- }
- {
- struct: pwr_lc
- type: req_rsp
- name: pwr_lc
- act: req
- package: pwrmgr_pkg
- inst_name: pwrmgr
- width: 1
- default: ""
- top_signame: pwrmgr_pwr_lc
- index: -1
- }
- {
- struct: pwr_flash
- type: req_rsp
- name: pwr_flash
- act: req
- package: pwrmgr_pkg
- inst_name: pwrmgr
- width: 1
- default: ""
- top_signame: pwrmgr_pwr_flash
- index: -1
- }
- {
- struct: esc_tx
- type: uni
- name: esc_rst_tx
- act: rcv
- package: prim_esc_pkg
- inst_name: pwrmgr
- width: 1
- default: ""
- top_signame: alert_handler_esc_tx
- index: 3
- }
- {
- struct: esc_rx
- type: uni
- name: esc_rst_rx
- act: req
- package: prim_esc_pkg
- inst_name: pwrmgr
- width: 1
- default: ""
- top_signame: alert_handler_esc_rx
- index: 3
- }
- {
- struct: pwr_cpu
- type: uni
- name: pwr_cpu
- act: rcv
- package: pwrmgr_pkg
- inst_name: pwrmgr
- width: 1
- default: ""
- top_signame: pwrmgr_pwr_cpu
- index: -1
- }
- {
- struct: logic
- width: 1
- type: uni
- name: wakeups
- act: rcv
- package: ""
- inst_name: pwrmgr
- default: ""
- top_type: broadcast
- top_signame: pwrmgr_wakeups
- index: -1
- }
- {
- struct: logic
- width: 1
- type: uni
- name: rstreqs
- act: rcv
- package: ""
- inst_name: pwrmgr
- default: ""
- top_type: broadcast
- top_signame: pwrmgr_rstreqs
- index: -1
- }
- {
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- name: tl
- inst_name: pwrmgr
- width: 1
- default: ""
- top_signame: pwrmgr_tl
- index: -1
- }
- ]
- }
- {
- name: rstmgr
- type: rstmgr
- clock_srcs:
- {
- clk_i: io_div4
- clk_aon_i: aon
- clk_main_i: main
- clk_io_i: io
- clk_usb_i: usb
- clk_io_div2_i: io_div2
- clk_io_div4_i: io_div4
- }
- clock_group: powerup
- reset_connections:
- {
- rst_ni: rst_ni
- }
- domain: Aon
- base_addr: 0x40410000
- generated: "true"
- clock_connections:
- {
- clk_i: clkmgr_clocks.clk_io_div4_powerup
- clk_aon_i: clkmgr_clocks.clk_aon_powerup
- clk_main_i: clkmgr_clocks.clk_main_powerup
- clk_io_i: clkmgr_clocks.clk_io_powerup
- clk_usb_i: clkmgr_clocks.clk_usb_powerup
- clk_io_div2_i: clkmgr_clocks.clk_io_div2_powerup
- clk_io_div4_i: clkmgr_clocks.clk_io_div4_powerup
- }
- size: 0x1000
- bus_device: tlul
- bus_host: none
- available_input_list: []
- available_output_list: []
- available_inout_list: []
- param_list: []
- interrupt_list: []
- alert_list: []
- wakeup_list: []
- reset_request_list: []
- scan: "true"
- scan_reset: "true"
- inter_signal_list:
- [
- {
- struct: pwr_rst
- type: req_rsp
- name: pwr
- act: rsp
- inst_name: rstmgr
- width: 1
- default: ""
- package: pwrmgr_pkg
- top_signame: pwrmgr_pwr_rst
- index: -1
- }
- {
- struct: rstmgr_out
- type: uni
- name: resets
- act: req
- package: rstmgr_pkg
- inst_name: rstmgr
- width: 1
- default: ""
- top_signame: rstmgr_resets
- index: -1
- }
- {
- struct: rstmgr_ast
- type: uni
- name: ast
- act: rcv
- package: rstmgr_pkg
- inst_name: rstmgr
- width: 1
- default: ""
- external: true
- top_signame: rstmgr_ast
- index: -1
- }
- {
- struct: rstmgr_cpu
- type: uni
- name: cpu
- act: rcv
- package: rstmgr_pkg
- inst_name: rstmgr
- width: 1
- default: ""
- top_signame: rstmgr_cpu
- index: -1
- }
- {
- struct: alert_crashdump
- type: uni
- name: alert_dump
- act: rcv
- package: alert_pkg
- inst_name: rstmgr
- width: 1
- default: ""
- top_signame: alert_handler_crashdump
- index: -1
- }
- {
- struct: crashdump
- type: uni
- name: cpu_dump
- act: rcv
- package: rv_core_ibex_pkg
- inst_name: rstmgr
- width: 1
- default: ""
- top_signame: rv_core_ibex_crashdump
- index: -1
- }
- {
- struct: rstmgr_ast_out
- type: uni
- name: resets_ast
- act: req
- package: rstmgr_pkg
- inst_name: rstmgr
- width: 1
- default: ""
- external: true
- top_signame: rsts_ast
- index: -1
- }
- {
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- name: tl
- inst_name: rstmgr
- width: 1
- default: ""
- top_signame: rstmgr_tl
- index: -1
- }
- ]
- }
- {
- name: clkmgr
- type: clkmgr
- clock_srcs:
- {
- clk_i: io_div4
- }
- clock_group: powerup
- reset_connections:
- {
- rst_ni: rstmgr_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]
- rst_main_ni: rstmgr_resets.rst_por_n[rstmgr_pkg::DomainAonSel]
- rst_io_ni: rstmgr_resets.rst_por_io_n[rstmgr_pkg::DomainAonSel]
- rst_usb_ni: rstmgr_resets.rst_por_usb_n[rstmgr_pkg::DomainAonSel]
- rst_io_div2_ni: rstmgr_resets.rst_por_io_div2_n[rstmgr_pkg::DomainAonSel]
- rst_io_div4_ni: rstmgr_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]
- }
- domain: Aon
- base_addr: 0x40420000
- generated: "true"
- clock_connections:
- {
- clk_i: clkmgr_clocks.clk_io_div4_powerup
- }
- size: 0x1000
- bus_device: tlul
- bus_host: none
- available_input_list: []
- available_output_list: []
- available_inout_list: []
- param_list: []
- interrupt_list: []
- alert_list: []
- wakeup_list: []
- reset_request_list: []
- scan: "true"
- scan_reset: "false"
- inter_signal_list:
- [
- {
- struct: clkmgr_out
- type: uni
- name: clocks
- act: req
- package: clkmgr_pkg
- inst_name: clkmgr
- width: 1
- default: ""
- top_signame: clkmgr_clocks
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: ast_clk_bypass_ack
- act: rcv
- package: lc_ctrl_pkg
- inst_name: clkmgr
- index: -1
- }
- {
- struct: lc_tx
- type: uni
- name: lc_clk_bypass_ack
- act: req
- package: lc_ctrl_pkg
- inst_name: clkmgr
- width: 1
- default: ""
- top_signame: lc_ctrl_lc_clk_byp_ack
- index: -1
- }
- {
- struct: logic
- type: uni
- name: clk_main
- act: rcv
- package: ""
- inst_name: clkmgr
- width: 1
- default: ""
- external: true
- top_signame: clk_main
- index: -1
- }
- {
- struct: logic
- type: uni
- name: clk_io
- act: rcv
- package: ""
- inst_name: clkmgr
- width: 1
- default: ""
- external: true
- top_signame: clk_io
- index: -1
- }
- {
- struct: logic
- type: uni
- name: clk_usb
- act: rcv
- package: ""
- inst_name: clkmgr
- width: 1
- default: ""
- external: true
- top_signame: clk_usb
- index: -1
- }
- {
- struct: logic
- type: uni
- name: clk_aon
- act: rcv
- package: ""
- inst_name: clkmgr
- width: 1
- default: ""
- external: true
- top_signame: clk_aon
- index: -1
- }
- {
- struct: clkmgr_ast_out
- type: uni
- name: clocks_ast
- act: req
- package: clkmgr_pkg
- inst_name: clkmgr
- width: 1
- default: ""
- external: true
- top_signame: clks_ast
- index: -1
- }
- {
- struct: pwr_clk
- type: req_rsp
- name: pwr
- act: rsp
- inst_name: clkmgr
- width: 1
- default: ""
- package: pwrmgr_pkg
- top_signame: pwrmgr_pwr_clk
- index: -1
- }
- {
- struct: logic
- type: uni
- name: idle
- act: rcv
- package: ""
- width: 4
- inst_name: clkmgr
- default: ""
- top_type: one-to-N
- top_signame: clkmgr_idle
- index: -1
- }
- {
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- name: tl
- inst_name: clkmgr
- width: 1
- default: ""
- top_signame: clkmgr_tl
- index: -1
- }
- ]
- }
- {
- name: pinmux
- type: pinmux
- clock: main
- clock_srcs:
- {
- clk_i: main
- clk_aon_i: aon
- }
- clock_group: secure
- reset_connections:
- {
- rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::DomainAonSel]
- rst_aon_ni: rstmgr_resets.rst_sys_aon_n[rstmgr_pkg::DomainAonSel]
- }
- domain: Aon
- base_addr: 0x40460000
- generated: "true"
- clock_connections:
- {
- clk_i: clkmgr_clocks.clk_main_secure
- clk_aon_i: clkmgr_clocks.clk_aon_secure
- }
- size: 0x1000
- bus_device: tlul
- bus_host: none
- available_input_list: []
- available_output_list: []
- available_inout_list: []
- param_list: []
- interrupt_list: []
- alert_list: []
- wakeup_list:
- [
- {
- name: aon_wkup_req
- width: "1"
- }
- ]
- reset_request_list: []
- scan: "false"
- scan_reset: "false"
- inter_signal_list:
- [
- {
- struct: lc_strap
- type: req_rsp
- name: lc_pinmux_strap
- act: rsp
- package: pinmux_pkg
- default: "'0"
- inst_name: pinmux
- index: -1
- }
- {
- struct: dft_strap_test
- type: uni
- name: dft_strap_test
- act: req
- package: pinmux_pkg
- default: "'0"
- inst_name: pinmux
- index: -1
- }
- {
- struct: io_pok
- type: uni
- name: io_pok
- act: rcv
- package: pinmux_pkg
- default: "{pinmux_pkg::NIOPokSignals{1'b1}}"
- inst_name: pinmux
- index: -1
- }
- {
- struct: logic
- type: uni
- name: sleep_en
- act: rcv
- package: ""
- default: 1'b0
- inst_name: pinmux
- index: -1
- }
- {
- struct: logic
- type: uni
- name: aon_wkup_req
- act: req
- package: ""
- default: 1'b0
- inst_name: pinmux
- width: 1
- top_signame: pwrmgr_wakeups
- index: -1
- }
- {
- struct: logic
- type: uni
- name: usb_wkup_req
- act: req
- package: ""
- default: 1'b0
- inst_name: pinmux
- index: -1
- }
- {
- name: usb_out_of_rst
- type: uni
- act: rcv
- package: ""
- struct: logic
- width: 1
- inst_name: pinmux
- default: ""
- top_signame: usbdev_usb_out_of_rst
- index: -1
- }
- {
- name: usb_aon_wake_en
- type: uni
- act: rcv
- package: ""
- struct: logic
- width: 1
- inst_name: pinmux
- default: ""
- top_signame: usbdev_usb_aon_wake_en
- index: -1
- }
- {
- name: usb_aon_wake_ack
- type: uni
- act: rcv
- package: ""
- struct: logic
- width: 1
- inst_name: pinmux
- default: ""
- top_signame: usbdev_usb_aon_wake_ack
- index: -1
- }
- {
- name: usb_suspend
- type: uni
- act: rcv
- package: ""
- struct: logic
- width: 1
- inst_name: pinmux
- default: ""
- top_signame: usbdev_usb_suspend
- index: -1
- }
- {
- name: usb_state_debug
- type: uni
- act: req
- package: usbdev_pkg
- struct: awk_state
- inst_name: pinmux
- width: 1
- default: ""
- top_type: broadcast
- top_signame: pinmux_usb_state_debug
- index: -1
- }
- {
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- name: tl
- inst_name: pinmux
- width: 1
- default: ""
- top_signame: pinmux_tl
- index: -1
- }
- ]
- }
- {
- name: padctrl
- type: padctrl
- clock: main
- clock_srcs:
- {
- clk_i: main
- }
- clock_group: secure
- reset_connections:
- {
- rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::DomainAonSel]
- }
- domain: Aon
- base_addr: 0x40470000
- generated: "true"
- clock_connections:
- {
- clk_i: clkmgr_clocks.clk_main_secure
- }
- size: 0x1000
- bus_device: tlul
- bus_host: none
- available_input_list: []
- available_output_list: []
- available_inout_list: []
- param_list: []
- interrupt_list: []
- alert_list: []
- wakeup_list: []
- reset_request_list: []
- scan: "false"
- scan_reset: "false"
- inter_signal_list:
- [
- {
- struct: tl
- package: tlul_pkg
- type: req_rsp
- act: rsp
- name: tl
- inst_name: padctrl
- width: 1
- default: ""
- top_signame: padctrl_tl
- index: -1
- }
- ]
- }
- {
name: usbdev
type: usbdev
clock_srcs:
@@ -4224,16 +2210,16 @@
]
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
- rst_aon_ni: rstmgr_resets.rst_sys_aon_n[rstmgr_pkg::Domain0Sel]
- rst_usb_48mhz_ni: rstmgr_resets.rst_usb_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
+ rst_aon_ni: rstmgr_aon_resets.rst_sys_aon_n[rstmgr_pkg::Domain0Sel]
+ rst_usb_48mhz_ni: rstmgr_aon_resets.rst_usb_n[rstmgr_pkg::Domain0Sel]
}
- base_addr: 0x40500000
+ base_addr: 0x40110000
clock_connections:
{
- clk_i: clkmgr_clocks.clk_io_div4_peri
- clk_aon_i: clkmgr_clocks.clk_aon_peri
- clk_usb_48mhz_i: clkmgr_clocks.clk_usb_peri
+ clk_i: clkmgr_aon_clocks.clk_io_div4_peri
+ clk_aon_i: clkmgr_aon_clocks.clk_aon_peri
+ clk_usb_48mhz_i: clkmgr_aon_clocks.clk_usb_peri
}
domain: "0"
size: 0x1000
@@ -4595,7 +2581,7 @@
inst_name: usbdev
width: 1
default: ""
- top_signame: pinmux_usb_state_debug
+ top_signame: pinmux_aon_usb_state_debug
index: -1
}
{
@@ -4613,7 +2599,2021 @@
]
}
{
- name: sram_ctrl_ret
+ name: otp_ctrl
+ type: otp_ctrl
+ clock_srcs:
+ {
+ clk_i: io_div4
+ clk_edn_i: main
+ }
+ clock_group: timers
+ reset_connections:
+ {
+ rst_ni: rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]
+ rst_edn_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ }
+ base_addr: 0x40130000
+ clock_connections:
+ {
+ clk_i: clkmgr_aon_clocks.clk_io_div4_timers
+ clk_edn_i: clkmgr_aon_clocks.clk_main_timers
+ }
+ domain: "0"
+ size: 0x4000
+ bus_device: tlul
+ bus_host: none
+ available_input_list: []
+ available_output_list: []
+ available_inout_list: []
+ param_list:
+ [
+ {
+ name: RndCnstLfsrSeed
+ desc: Compile-time random bits for initial LFSR seed
+ type: otp_ctrl_pkg::lfsr_seed_t
+ randcount: "40"
+ randtype: data
+ local: "false"
+ default: 0xf45def7861
+ expose: "false"
+ name_top: RndCnstOtpCtrlLfsrSeed
+ randwidth: 40
+ }
+ {
+ name: RndCnstLfsrPerm
+ desc: Compile-time random permutation for LFSR output
+ type: otp_ctrl_pkg::lfsr_perm_t
+ randcount: "40"
+ randtype: perm
+ local: "false"
+ default: 0x5d294061e29a7c404f4593035a19097666e37072064153623855022d39e0
+ expose: "false"
+ name_top: RndCnstOtpCtrlLfsrPerm
+ randwidth: 240
+ }
+ ]
+ interrupt_list:
+ [
+ {
+ name: otp_operation_done
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: interrupt
+ }
+ {
+ name: otp_error
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: interrupt
+ }
+ ]
+ alert_list:
+ [
+ {
+ name: fatal_macro_error
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: alert
+ async: 0
+ }
+ {
+ name: fatal_check_error
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: alert
+ async: 0
+ }
+ ]
+ wakeup_list: []
+ reset_request_list: []
+ scan: "false"
+ scan_reset: "false"
+ inter_signal_list:
+ [
+ {
+ struct: otp_ast_req
+ type: uni
+ name: otp_ast_pwr_seq
+ act: req
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ width: 1
+ external: true
+ top_signame: otp_ctrl_otp_ast_pwr_seq
+ index: -1
+ }
+ {
+ struct: otp_ast_rsp
+ type: uni
+ name: otp_ast_pwr_seq_h
+ act: rcv
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ width: 1
+ external: true
+ top_signame: otp_ctrl_otp_ast_pwr_seq_h
+ index: -1
+ }
+ {
+ struct: edn
+ type: req_rsp
+ name: edn
+ act: req
+ package: edn_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: pwr_otp
+ type: req_rsp
+ name: pwr_otp
+ act: rsp
+ default: "'0"
+ package: pwrmgr_pkg
+ inst_name: otp_ctrl
+ width: 1
+ top_signame: pwrmgr_aon_pwr_otp
+ index: -1
+ }
+ {
+ struct: lc_otp_program
+ type: req_rsp
+ name: lc_otp_program
+ act: rsp
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ width: 1
+ top_signame: lc_ctrl_lc_otp_program
+ index: -1
+ }
+ {
+ struct: lc_otp_token
+ type: req_rsp
+ name: lc_otp_token
+ act: rsp
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ width: 1
+ top_signame: lc_ctrl_lc_otp_token
+ index: -1
+ }
+ {
+ struct: otp_lc_data
+ type: uni
+ name: otp_lc_data
+ act: req
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ width: 1
+ top_type: broadcast
+ top_signame: otp_ctrl_otp_lc_data
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_escalate_en
+ act: rcv
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: otp_ctrl
+ width: 1
+ top_signame: lc_ctrl_lc_escalate_en
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_creator_seed_sw_rw_en
+ act: rcv
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: otp_ctrl
+ width: 1
+ top_signame: lc_ctrl_lc_creator_seed_sw_rw_en
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_seed_hw_rd_en
+ act: rcv
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: otp_ctrl
+ width: 1
+ top_signame: lc_ctrl_lc_seed_hw_rd_en
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_dft_en
+ act: rcv
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: otp_ctrl
+ width: 1
+ top_signame: lc_ctrl_lc_dft_en
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_check_byp_en
+ act: rcv
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: otp_ctrl
+ width: 1
+ top_signame: lc_ctrl_lc_check_byp_en
+ index: -1
+ }
+ {
+ struct: otp_keymgr_key
+ type: uni
+ name: otp_keymgr_key
+ act: req
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ width: 1
+ top_type: broadcast
+ top_signame: otp_ctrl_otp_keymgr_key
+ index: -1
+ }
+ {
+ struct: flash_otp_key
+ type: req_rsp
+ name: flash_otp_key
+ act: rsp
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ width: 1
+ top_signame: flash_ctrl_otp
+ index: -1
+ }
+ {
+ struct: sram_otp_key
+ width: 2
+ type: req_rsp
+ name: sram_otp_key
+ act: rsp
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ top_signame: otp_ctrl_sram_otp_key
+ index: -1
+ }
+ {
+ struct: otbn_otp_key
+ type: req_rsp
+ name: otbn_otp_key
+ act: rsp
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: otp_ctrl
+ index: -1
+ }
+ {
+ struct: otp_hw_cfg
+ type: uni
+ name: otp_hw_cfg
+ act: req
+ default: "'0"
+ package: otp_ctrl_part_pkg
+ inst_name: otp_ctrl
+ width: 1
+ top_type: broadcast
+ top_signame: otp_ctrl_otp_hw_cfg
+ index: -1
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: otp_ctrl
+ width: 1
+ default: ""
+ top_signame: otp_ctrl_tl
+ index: -1
+ }
+ ]
+ }
+ {
+ name: lc_ctrl
+ type: lc_ctrl
+ clock_srcs:
+ {
+ clk_i: io_div4
+ }
+ clock_group: timers
+ reset_connections:
+ {
+ rst_ni: rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]
+ }
+ base_addr: 0x40140000
+ clock_connections:
+ {
+ clk_i: clkmgr_aon_clocks.clk_io_div4_timers
+ }
+ domain: "0"
+ size: 0x1000
+ bus_device: tlul
+ bus_host: none
+ available_input_list: []
+ available_output_list: []
+ available_inout_list: []
+ param_list:
+ [
+ {
+ name: RndCnstLcKeymgrDivInvalid
+ desc: Compile-time random bits for lc state group diversification value
+ type: lc_ctrl_pkg::lc_keymgr_div_t
+ randcount: "64"
+ randtype: data
+ local: "false"
+ default: 0xf4c3471c5def7861
+ expose: "false"
+ name_top: RndCnstLcCtrlLcKeymgrDivInvalid
+ randwidth: 64
+ }
+ {
+ name: RndCnstLcKeymgrDivTestDevRma
+ desc: Compile-time random bits for lc state group diversification value
+ type: lc_ctrl_pkg::lc_keymgr_div_t
+ randcount: "64"
+ randtype: data
+ local: "false"
+ default: 0x83d0550b80e84eb1
+ expose: "false"
+ name_top: RndCnstLcCtrlLcKeymgrDivTestDevRma
+ randwidth: 64
+ }
+ {
+ name: RndCnstLcKeymgrDivProduction
+ desc: Compile-time random bits for lc state group diversification value
+ type: lc_ctrl_pkg::lc_keymgr_div_t
+ randcount: "64"
+ randtype: data
+ local: "false"
+ default: 0x2d73930d4cac3785
+ expose: "false"
+ name_top: RndCnstLcCtrlLcKeymgrDivProduction
+ randwidth: 64
+ }
+ ]
+ interrupt_list: []
+ alert_list:
+ [
+ {
+ name: fatal_prog_error
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: alert
+ async: 0
+ }
+ {
+ name: fatal_state_error
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: alert
+ async: 0
+ }
+ ]
+ wakeup_list: []
+ reset_request_list: []
+ scan: "true"
+ scan_reset: "false"
+ inter_signal_list:
+ [
+ {
+ struct: jtag
+ type: req_rsp
+ name: jtag
+ act: rsp
+ package: jtag_pkg
+ inst_name: lc_ctrl
+ index: -1
+ }
+ {
+ struct: esc_tx
+ type: uni
+ name: esc_wipe_secrets_tx
+ act: rcv
+ package: prim_esc_pkg
+ inst_name: lc_ctrl
+ width: 1
+ default: ""
+ top_signame: alert_handler_esc_tx
+ index: 1
+ }
+ {
+ struct: esc_rx
+ type: uni
+ name: esc_wipe_secrets_rx
+ act: req
+ package: prim_esc_pkg
+ inst_name: lc_ctrl
+ width: 1
+ default: ""
+ top_signame: alert_handler_esc_rx
+ index: 1
+ }
+ {
+ struct: esc_tx
+ type: uni
+ name: esc_scrap_state_tx
+ act: rcv
+ package: prim_esc_pkg
+ inst_name: lc_ctrl
+ width: 1
+ default: ""
+ top_signame: alert_handler_esc_tx
+ index: 2
+ }
+ {
+ struct: esc_rx
+ type: uni
+ name: esc_scrap_state_rx
+ act: req
+ package: prim_esc_pkg
+ inst_name: lc_ctrl
+ width: 1
+ default: ""
+ top_signame: alert_handler_esc_rx
+ index: 2
+ }
+ {
+ struct: pwr_lc
+ type: req_rsp
+ name: pwr_lc
+ act: rsp
+ package: pwrmgr_pkg
+ inst_name: lc_ctrl
+ width: 1
+ default: ""
+ top_signame: pwrmgr_aon_pwr_lc
+ index: -1
+ }
+ {
+ struct: otp_lc_data
+ type: uni
+ name: otp_lc_data
+ act: rcv
+ default: otp_ctrl_pkg::OTP_LC_DATA_DEFAULT
+ package: otp_ctrl_pkg
+ inst_name: lc_ctrl
+ width: 1
+ top_signame: otp_ctrl_otp_lc_data
+ index: -1
+ }
+ {
+ struct: lc_otp_program
+ type: req_rsp
+ name: lc_otp_program
+ act: req
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: lc_ctrl
+ width: 1
+ top_signame: lc_ctrl_lc_otp_program
+ index: -1
+ }
+ {
+ struct: lc_otp_token
+ type: req_rsp
+ name: lc_otp_token
+ act: req
+ default: "'0"
+ package: otp_ctrl_pkg
+ inst_name: lc_ctrl
+ width: 1
+ top_signame: lc_ctrl_lc_otp_token
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_dft_en
+ act: req
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: lc_ctrl
+ width: 1
+ top_type: broadcast
+ top_signame: lc_ctrl_lc_dft_en
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_nvm_debug_en
+ act: req
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: lc_ctrl
+ width: 1
+ top_type: broadcast
+ top_signame: lc_ctrl_lc_nvm_debug_en
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_hw_debug_en
+ act: req
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: lc_ctrl
+ width: 1
+ top_type: broadcast
+ top_signame: lc_ctrl_lc_hw_debug_en
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_cpu_en
+ act: req
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: lc_ctrl
+ width: 1
+ top_type: broadcast
+ top_signame: lc_ctrl_lc_cpu_en
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_keymgr_en
+ act: req
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: lc_ctrl
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_escalate_en
+ act: req
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: lc_ctrl
+ width: 1
+ top_type: broadcast
+ top_signame: lc_ctrl_lc_escalate_en
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_clk_byp_req
+ act: req
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: lc_ctrl
+ width: 1
+ top_type: broadcast
+ top_signame: lc_ctrl_lc_clk_byp_req
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_clk_byp_ack
+ act: rcv
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: lc_ctrl
+ width: 1
+ top_type: broadcast
+ top_signame: lc_ctrl_lc_clk_byp_ack
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_flash_rma_req
+ act: req
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: lc_ctrl
+ width: 1
+ top_signame: flash_ctrl_rma_req
+ index: -1
+ }
+ {
+ struct: lc_flash_rma_seed
+ type: uni
+ name: lc_flash_rma_seed
+ act: req
+ default: "'0"
+ package: lc_ctrl_pkg
+ inst_name: lc_ctrl
+ width: 1
+ top_signame: flash_ctrl_rma_seed
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_flash_rma_ack
+ act: rcv
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: lc_ctrl
+ width: 1
+ top_signame: flash_ctrl_rma_ack
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_check_byp_en
+ act: req
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: lc_ctrl
+ width: 1
+ top_type: broadcast
+ top_signame: lc_ctrl_lc_check_byp_en
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_creator_seed_sw_rw_en
+ act: req
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: lc_ctrl
+ width: 1
+ top_type: broadcast
+ top_signame: lc_ctrl_lc_creator_seed_sw_rw_en
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_owner_seed_sw_rw_en
+ act: req
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: lc_ctrl
+ width: 1
+ top_type: broadcast
+ top_signame: lc_ctrl_lc_owner_seed_sw_rw_en
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_iso_part_sw_rd_en
+ act: req
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: lc_ctrl
+ width: 1
+ top_type: broadcast
+ top_signame: lc_ctrl_lc_iso_part_sw_rd_en
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_iso_part_sw_wr_en
+ act: req
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: lc_ctrl
+ width: 1
+ top_type: broadcast
+ top_signame: lc_ctrl_lc_iso_part_sw_wr_en
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_seed_hw_rd_en
+ act: req
+ default: lc_ctrl_pkg::Off
+ package: lc_ctrl_pkg
+ inst_name: lc_ctrl
+ width: 1
+ top_type: broadcast
+ top_signame: lc_ctrl_lc_seed_hw_rd_en
+ index: -1
+ }
+ {
+ struct: lc_keymgr_div
+ type: uni
+ name: lc_keymgr_div
+ act: req
+ default: "'0"
+ package: lc_ctrl_pkg
+ inst_name: lc_ctrl
+ width: 1
+ top_type: broadcast
+ top_signame: lc_ctrl_lc_keymgr_div
+ index: -1
+ }
+ {
+ struct: otp_hw_cfg
+ type: uni
+ name: otp_hw_cfg
+ act: rcv
+ default: "'0"
+ package: otp_ctrl_part_pkg
+ inst_name: lc_ctrl
+ width: 1
+ top_signame: otp_ctrl_otp_hw_cfg
+ index: -1
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: lc_ctrl
+ width: 1
+ default: ""
+ top_signame: lc_ctrl_tl
+ index: -1
+ }
+ ]
+ }
+ {
+ name: alert_handler
+ type: alert_handler
+ clock_srcs:
+ {
+ clk_i: io_div4
+ }
+ clock_group: timers
+ reset_connections:
+ {
+ rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
+ }
+ base_addr: 0x40150000
+ generated: "true"
+ localparam:
+ {
+ EscCntDw: 32
+ AccuCntDw: 16
+ LfsrSeed: 0x7FFFFFFF
+ }
+ clock_connections:
+ {
+ clk_i: clkmgr_aon_clocks.clk_io_div4_timers
+ }
+ domain: "0"
+ size: 0x1000
+ bus_device: tlul
+ bus_host: none
+ available_input_list: []
+ available_output_list: []
+ available_inout_list: []
+ param_list:
+ [
+ {
+ name: RndCnstLfsrSeed
+ desc: Compile-time random bits for initial LFSR seed
+ type: alert_pkg::lfsr_seed_t
+ randcount: "32"
+ randtype: data
+ local: "false"
+ default: 0x5def7861
+ expose: "false"
+ name_top: RndCnstAlertHandlerLfsrSeed
+ randwidth: 32
+ }
+ {
+ name: RndCnstLfsrPerm
+ desc: Compile-time random permutation for LFSR output
+ type: alert_pkg::lfsr_perm_t
+ randcount: "32"
+ randtype: perm
+ local: "false"
+ default: 0x5f00c4cafd73fc4ac479a61068375f38956d84b3
+ expose: "false"
+ name_top: RndCnstAlertHandlerLfsrPerm
+ randwidth: 160
+ }
+ ]
+ interrupt_list:
+ [
+ {
+ name: classa
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: interrupt
+ }
+ {
+ name: classb
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: interrupt
+ }
+ {
+ name: classc
+ width: 1
+ bits: "2"
+ bitinfo:
+ [
+ 4
+ 1
+ 2
+ ]
+ type: interrupt
+ }
+ {
+ name: classd
+ width: 1
+ bits: "3"
+ bitinfo:
+ [
+ 8
+ 1
+ 3
+ ]
+ type: interrupt
+ }
+ ]
+ alert_list: []
+ wakeup_list: []
+ reset_request_list: []
+ scan: "false"
+ scan_reset: "false"
+ inter_signal_list:
+ [
+ {
+ struct: alert_crashdump
+ type: uni
+ name: crashdump
+ act: req
+ package: alert_pkg
+ inst_name: alert_handler
+ width: 1
+ default: ""
+ top_type: broadcast
+ top_signame: alert_handler_crashdump
+ index: -1
+ }
+ {
+ struct: logic
+ type: uni
+ name: entropy
+ default: " 1'b0"
+ act: rcv
+ inst_name: alert_handler
+ index: -1
+ }
+ {
+ struct: esc_rx
+ type: uni
+ name: esc_rx
+ act: rcv
+ width: 4
+ package: prim_esc_pkg
+ inst_name: alert_handler
+ default: ""
+ top_type: one-to-N
+ top_signame: alert_handler_esc_rx
+ index: -1
+ }
+ {
+ struct: esc_tx
+ type: uni
+ name: esc_tx
+ act: req
+ width: 4
+ package: prim_esc_pkg
+ inst_name: alert_handler
+ default: ""
+ top_type: one-to-N
+ top_signame: alert_handler_esc_tx
+ index: -1
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: alert_handler
+ width: 1
+ default: ""
+ top_signame: alert_handler_tl
+ index: -1
+ }
+ ]
+ }
+ {
+ name: nmi_gen
+ type: nmi_gen
+ clock_srcs:
+ {
+ clk_i: io_div4
+ }
+ clock_group: timers
+ reset_connections:
+ {
+ rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
+ }
+ base_addr: 0x40160000
+ clock_connections:
+ {
+ clk_i: clkmgr_aon_clocks.clk_io_div4_timers
+ }
+ domain: "0"
+ size: 0x1000
+ bus_device: tlul
+ bus_host: none
+ available_input_list: []
+ available_output_list: []
+ available_inout_list: []
+ param_list: []
+ interrupt_list:
+ [
+ {
+ name: esc0
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: interrupt
+ }
+ {
+ name: esc1
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: interrupt
+ }
+ {
+ name: esc2
+ width: 1
+ bits: "2"
+ bitinfo:
+ [
+ 4
+ 1
+ 2
+ ]
+ type: interrupt
+ }
+ ]
+ alert_list: []
+ wakeup_list: []
+ reset_request_list:
+ [
+ {
+ name: nmi_rst_req
+ }
+ ]
+ scan: "false"
+ scan_reset: "false"
+ inter_signal_list:
+ [
+ {
+ struct: logic
+ type: uni
+ name: nmi_rst_req
+ act: req
+ package: ""
+ default: 1'b0
+ inst_name: nmi_gen
+ width: 1
+ top_signame: pwrmgr_aon_rstreqs
+ index: -1
+ }
+ {
+ struct: esc_tx
+ type: uni
+ name: esc_tx
+ act: rcv
+ package: prim_esc_pkg
+ default: "{3{prim_esc_pkg::ESC_TX_DEFAULT}}"
+ inst_name: nmi_gen
+ index: -1
+ }
+ {
+ struct: esc_rx
+ type: uni
+ name: esc_rx
+ act: req
+ package: prim_esc_pkg
+ inst_name: nmi_gen
+ index: -1
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: nmi_gen
+ width: 1
+ default: ""
+ top_signame: nmi_gen_tl
+ index: -1
+ }
+ ]
+ }
+ {
+ name: pwrmgr_aon
+ type: pwrmgr
+ clock_srcs:
+ {
+ clk_i: io_div4
+ clk_slow_i: aon
+ }
+ clock_group: powerup
+ reset_connections:
+ {
+ rst_ni: rstmgr_aon_resets.rst_por_n[rstmgr_pkg::DomainAonSel]
+ rst_slow_ni: rstmgr_aon_resets.rst_por_aon_n[rstmgr_pkg::DomainAonSel]
+ }
+ domain: Aon
+ base_addr: 0x40400000
+ generated: "true"
+ clock_connections:
+ {
+ clk_i: clkmgr_aon_clocks.clk_io_div4_powerup
+ clk_slow_i: clkmgr_aon_clocks.clk_aon_powerup
+ }
+ size: 0x1000
+ bus_device: tlul
+ bus_host: none
+ available_input_list: []
+ available_output_list: []
+ available_inout_list: []
+ param_list: []
+ interrupt_list:
+ [
+ {
+ name: wakeup
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: interrupt
+ }
+ ]
+ alert_list: []
+ wakeup_list: []
+ reset_request_list: []
+ scan: "false"
+ scan_reset: "false"
+ inter_signal_list:
+ [
+ {
+ struct: pwr_ast
+ type: req_rsp
+ name: pwr_ast
+ act: req
+ package: pwrmgr_pkg
+ inst_name: pwrmgr_aon
+ width: 1
+ default: ""
+ external: true
+ top_signame: pwrmgr_ast
+ index: -1
+ }
+ {
+ struct: pwr_rst
+ type: req_rsp
+ name: pwr_rst
+ act: req
+ package: pwrmgr_pkg
+ inst_name: pwrmgr_aon
+ width: 1
+ default: ""
+ top_signame: pwrmgr_aon_pwr_rst
+ index: -1
+ }
+ {
+ struct: pwr_clk
+ type: req_rsp
+ name: pwr_clk
+ act: req
+ package: pwrmgr_pkg
+ inst_name: pwrmgr_aon
+ width: 1
+ default: ""
+ top_signame: pwrmgr_aon_pwr_clk
+ index: -1
+ }
+ {
+ struct: pwr_otp
+ type: req_rsp
+ name: pwr_otp
+ act: req
+ package: pwrmgr_pkg
+ inst_name: pwrmgr_aon
+ width: 1
+ default: ""
+ top_signame: pwrmgr_aon_pwr_otp
+ index: -1
+ }
+ {
+ struct: pwr_lc
+ type: req_rsp
+ name: pwr_lc
+ act: req
+ package: pwrmgr_pkg
+ inst_name: pwrmgr_aon
+ width: 1
+ default: ""
+ top_signame: pwrmgr_aon_pwr_lc
+ index: -1
+ }
+ {
+ struct: pwr_flash
+ type: req_rsp
+ name: pwr_flash
+ act: req
+ package: pwrmgr_pkg
+ inst_name: pwrmgr_aon
+ width: 1
+ default: ""
+ top_signame: pwrmgr_aon_pwr_flash
+ index: -1
+ }
+ {
+ struct: esc_tx
+ type: uni
+ name: esc_rst_tx
+ act: rcv
+ package: prim_esc_pkg
+ inst_name: pwrmgr_aon
+ width: 1
+ default: ""
+ top_signame: alert_handler_esc_tx
+ index: 3
+ }
+ {
+ struct: esc_rx
+ type: uni
+ name: esc_rst_rx
+ act: req
+ package: prim_esc_pkg
+ inst_name: pwrmgr_aon
+ width: 1
+ default: ""
+ top_signame: alert_handler_esc_rx
+ index: 3
+ }
+ {
+ struct: pwr_cpu
+ type: uni
+ name: pwr_cpu
+ act: rcv
+ package: pwrmgr_pkg
+ inst_name: pwrmgr_aon
+ width: 1
+ default: ""
+ top_signame: pwrmgr_aon_pwr_cpu
+ index: -1
+ }
+ {
+ struct: logic
+ width: 1
+ type: uni
+ name: wakeups
+ act: rcv
+ package: ""
+ inst_name: pwrmgr_aon
+ default: ""
+ top_type: broadcast
+ top_signame: pwrmgr_aon_wakeups
+ index: -1
+ }
+ {
+ struct: logic
+ width: 1
+ type: uni
+ name: rstreqs
+ act: rcv
+ package: ""
+ inst_name: pwrmgr_aon
+ default: ""
+ top_type: broadcast
+ top_signame: pwrmgr_aon_rstreqs
+ index: -1
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: pwrmgr_aon
+ width: 1
+ default: ""
+ top_signame: pwrmgr_aon_tl
+ index: -1
+ }
+ ]
+ }
+ {
+ name: rstmgr_aon
+ type: rstmgr
+ clock_srcs:
+ {
+ clk_i: io_div4
+ clk_aon_i: aon
+ clk_main_i: main
+ clk_io_i: io
+ clk_usb_i: usb
+ clk_io_div2_i: io_div2
+ clk_io_div4_i: io_div4
+ }
+ clock_group: powerup
+ reset_connections:
+ {
+ rst_ni: rst_ni
+ }
+ domain: Aon
+ base_addr: 0x40410000
+ generated: "true"
+ clock_connections:
+ {
+ clk_i: clkmgr_aon_clocks.clk_io_div4_powerup
+ clk_aon_i: clkmgr_aon_clocks.clk_aon_powerup
+ clk_main_i: clkmgr_aon_clocks.clk_main_powerup
+ clk_io_i: clkmgr_aon_clocks.clk_io_powerup
+ clk_usb_i: clkmgr_aon_clocks.clk_usb_powerup
+ clk_io_div2_i: clkmgr_aon_clocks.clk_io_div2_powerup
+ clk_io_div4_i: clkmgr_aon_clocks.clk_io_div4_powerup
+ }
+ size: 0x1000
+ bus_device: tlul
+ bus_host: none
+ available_input_list: []
+ available_output_list: []
+ available_inout_list: []
+ param_list: []
+ interrupt_list: []
+ alert_list: []
+ wakeup_list: []
+ reset_request_list: []
+ scan: "true"
+ scan_reset: "true"
+ inter_signal_list:
+ [
+ {
+ struct: pwr_rst
+ type: req_rsp
+ name: pwr
+ act: rsp
+ inst_name: rstmgr_aon
+ width: 1
+ default: ""
+ package: pwrmgr_pkg
+ top_signame: pwrmgr_aon_pwr_rst
+ index: -1
+ }
+ {
+ struct: rstmgr_out
+ type: uni
+ name: resets
+ act: req
+ package: rstmgr_pkg
+ inst_name: rstmgr_aon
+ width: 1
+ default: ""
+ top_signame: rstmgr_aon_resets
+ index: -1
+ }
+ {
+ struct: rstmgr_ast
+ type: uni
+ name: ast
+ act: rcv
+ package: rstmgr_pkg
+ inst_name: rstmgr_aon
+ width: 1
+ default: ""
+ external: true
+ top_signame: rstmgr_ast
+ index: -1
+ }
+ {
+ struct: rstmgr_cpu
+ type: uni
+ name: cpu
+ act: rcv
+ package: rstmgr_pkg
+ inst_name: rstmgr_aon
+ width: 1
+ default: ""
+ top_signame: rstmgr_aon_cpu
+ index: -1
+ }
+ {
+ struct: alert_crashdump
+ type: uni
+ name: alert_dump
+ act: rcv
+ package: alert_pkg
+ inst_name: rstmgr_aon
+ width: 1
+ default: ""
+ top_signame: alert_handler_crashdump
+ index: -1
+ }
+ {
+ struct: crashdump
+ type: uni
+ name: cpu_dump
+ act: rcv
+ package: rv_core_ibex_pkg
+ inst_name: rstmgr_aon
+ width: 1
+ default: ""
+ top_signame: rv_core_ibex_crashdump
+ index: -1
+ }
+ {
+ struct: rstmgr_ast_out
+ type: uni
+ name: resets_ast
+ act: req
+ package: rstmgr_pkg
+ inst_name: rstmgr_aon
+ width: 1
+ default: ""
+ external: true
+ top_signame: rsts_ast
+ index: -1
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: rstmgr_aon
+ width: 1
+ default: ""
+ top_signame: rstmgr_aon_tl
+ index: -1
+ }
+ ]
+ }
+ {
+ name: clkmgr_aon
+ type: clkmgr
+ clock_srcs:
+ {
+ clk_i: io_div4
+ }
+ clock_group: powerup
+ reset_connections:
+ {
+ rst_ni: rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]
+ rst_main_ni: rstmgr_aon_resets.rst_por_n[rstmgr_pkg::DomainAonSel]
+ rst_io_ni: rstmgr_aon_resets.rst_por_io_n[rstmgr_pkg::DomainAonSel]
+ rst_usb_ni: rstmgr_aon_resets.rst_por_usb_n[rstmgr_pkg::DomainAonSel]
+ rst_io_div2_ni: rstmgr_aon_resets.rst_por_io_div2_n[rstmgr_pkg::DomainAonSel]
+ rst_io_div4_ni: rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]
+ }
+ domain: Aon
+ base_addr: 0x40420000
+ generated: "true"
+ clock_connections:
+ {
+ clk_i: clkmgr_aon_clocks.clk_io_div4_powerup
+ }
+ size: 0x1000
+ bus_device: tlul
+ bus_host: none
+ available_input_list: []
+ available_output_list: []
+ available_inout_list: []
+ param_list: []
+ interrupt_list: []
+ alert_list: []
+ wakeup_list: []
+ reset_request_list: []
+ scan: "true"
+ scan_reset: "false"
+ inter_signal_list:
+ [
+ {
+ struct: clkmgr_out
+ type: uni
+ name: clocks
+ act: req
+ package: clkmgr_pkg
+ inst_name: clkmgr_aon
+ width: 1
+ default: ""
+ top_signame: clkmgr_aon_clocks
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: ast_clk_bypass_ack
+ act: rcv
+ package: lc_ctrl_pkg
+ inst_name: clkmgr_aon
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_clk_bypass_ack
+ act: req
+ package: lc_ctrl_pkg
+ inst_name: clkmgr_aon
+ width: 1
+ default: ""
+ top_signame: lc_ctrl_lc_clk_byp_ack
+ index: -1
+ }
+ {
+ struct: logic
+ type: uni
+ name: clk_main
+ act: rcv
+ package: ""
+ inst_name: clkmgr_aon
+ width: 1
+ default: ""
+ external: true
+ top_signame: clk_main
+ index: -1
+ }
+ {
+ struct: logic
+ type: uni
+ name: clk_io
+ act: rcv
+ package: ""
+ inst_name: clkmgr_aon
+ width: 1
+ default: ""
+ external: true
+ top_signame: clk_io
+ index: -1
+ }
+ {
+ struct: logic
+ type: uni
+ name: clk_usb
+ act: rcv
+ package: ""
+ inst_name: clkmgr_aon
+ width: 1
+ default: ""
+ external: true
+ top_signame: clk_usb
+ index: -1
+ }
+ {
+ struct: logic
+ type: uni
+ name: clk_aon
+ act: rcv
+ package: ""
+ inst_name: clkmgr_aon
+ width: 1
+ default: ""
+ external: true
+ top_signame: clk_aon
+ index: -1
+ }
+ {
+ struct: clkmgr_ast_out
+ type: uni
+ name: clocks_ast
+ act: req
+ package: clkmgr_pkg
+ inst_name: clkmgr_aon
+ width: 1
+ default: ""
+ external: true
+ top_signame: clks_ast
+ index: -1
+ }
+ {
+ struct: pwr_clk
+ type: req_rsp
+ name: pwr
+ act: rsp
+ inst_name: clkmgr_aon
+ width: 1
+ default: ""
+ package: pwrmgr_pkg
+ top_signame: pwrmgr_aon_pwr_clk
+ index: -1
+ }
+ {
+ struct: logic
+ type: uni
+ name: idle
+ act: rcv
+ package: ""
+ width: 4
+ inst_name: clkmgr_aon
+ default: ""
+ top_type: one-to-N
+ top_signame: clkmgr_aon_idle
+ index: -1
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: clkmgr_aon
+ width: 1
+ default: ""
+ top_signame: clkmgr_aon_tl
+ index: -1
+ }
+ ]
+ }
+ {
+ name: pinmux_aon
+ type: pinmux
+ clock: main
+ clock_srcs:
+ {
+ clk_i: io_div4
+ clk_aon_i: aon
+ }
+ clock_group: secure
+ reset_connections:
+ {
+ rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]
+ rst_aon_ni: rstmgr_aon_resets.rst_sys_aon_n[rstmgr_pkg::DomainAonSel]
+ }
+ domain: Aon
+ base_addr: 0x40460000
+ generated: "true"
+ clock_connections:
+ {
+ clk_i: clkmgr_aon_clocks.clk_io_div4_secure
+ clk_aon_i: clkmgr_aon_clocks.clk_aon_secure
+ }
+ size: 0x1000
+ bus_device: tlul
+ bus_host: none
+ available_input_list: []
+ available_output_list: []
+ available_inout_list: []
+ param_list: []
+ interrupt_list: []
+ alert_list: []
+ wakeup_list:
+ [
+ {
+ name: aon_wkup_req
+ width: "1"
+ }
+ ]
+ reset_request_list: []
+ scan: "false"
+ scan_reset: "false"
+ inter_signal_list:
+ [
+ {
+ struct: lc_strap
+ type: req_rsp
+ name: lc_pinmux_strap
+ act: rsp
+ package: pinmux_pkg
+ default: "'0"
+ inst_name: pinmux_aon
+ index: -1
+ }
+ {
+ struct: dft_strap_test
+ type: uni
+ name: dft_strap_test
+ act: req
+ package: pinmux_pkg
+ default: "'0"
+ inst_name: pinmux_aon
+ index: -1
+ }
+ {
+ struct: io_pok
+ type: uni
+ name: io_pok
+ act: rcv
+ package: pinmux_pkg
+ default: "{pinmux_pkg::NIOPokSignals{1'b1}}"
+ inst_name: pinmux_aon
+ index: -1
+ }
+ {
+ struct: logic
+ type: uni
+ name: sleep_en
+ act: rcv
+ package: ""
+ default: 1'b0
+ inst_name: pinmux_aon
+ index: -1
+ }
+ {
+ struct: logic
+ type: uni
+ name: aon_wkup_req
+ act: req
+ package: ""
+ default: 1'b0
+ inst_name: pinmux_aon
+ width: 1
+ top_signame: pwrmgr_aon_wakeups
+ index: -1
+ }
+ {
+ struct: logic
+ type: uni
+ name: usb_wkup_req
+ act: req
+ package: ""
+ default: 1'b0
+ inst_name: pinmux_aon
+ index: -1
+ }
+ {
+ name: usb_out_of_rst
+ type: uni
+ act: rcv
+ package: ""
+ struct: logic
+ width: 1
+ inst_name: pinmux_aon
+ default: ""
+ top_signame: usbdev_usb_out_of_rst
+ index: -1
+ }
+ {
+ name: usb_aon_wake_en
+ type: uni
+ act: rcv
+ package: ""
+ struct: logic
+ width: 1
+ inst_name: pinmux_aon
+ default: ""
+ top_signame: usbdev_usb_aon_wake_en
+ index: -1
+ }
+ {
+ name: usb_aon_wake_ack
+ type: uni
+ act: rcv
+ package: ""
+ struct: logic
+ width: 1
+ inst_name: pinmux_aon
+ default: ""
+ top_signame: usbdev_usb_aon_wake_ack
+ index: -1
+ }
+ {
+ name: usb_suspend
+ type: uni
+ act: rcv
+ package: ""
+ struct: logic
+ width: 1
+ inst_name: pinmux_aon
+ default: ""
+ top_signame: usbdev_usb_suspend
+ index: -1
+ }
+ {
+ name: usb_state_debug
+ type: uni
+ act: req
+ package: usbdev_pkg
+ struct: awk_state
+ inst_name: pinmux_aon
+ width: 1
+ default: ""
+ top_type: broadcast
+ top_signame: pinmux_aon_usb_state_debug
+ index: -1
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: pinmux_aon
+ width: 1
+ default: ""
+ top_signame: pinmux_aon_tl
+ index: -1
+ }
+ ]
+ }
+ {
+ name: padctrl_aon
+ type: padctrl
+ clock: main
+ clock_srcs:
+ {
+ clk_i: io_div4
+ }
+ clock_group: secure
+ reset_connections:
+ {
+ rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]
+ }
+ domain: Aon
+ base_addr: 0x40470000
+ generated: "true"
+ clock_connections:
+ {
+ clk_i: clkmgr_aon_clocks.clk_io_div4_secure
+ }
+ size: 0x1000
+ bus_device: tlul
+ bus_host: none
+ available_input_list: []
+ available_output_list: []
+ available_inout_list: []
+ param_list: []
+ interrupt_list: []
+ alert_list: []
+ wakeup_list: []
+ reset_request_list: []
+ scan: "false"
+ scan_reset: "false"
+ inter_signal_list:
+ [
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: padctrl_aon
+ width: 1
+ default: ""
+ top_signame: padctrl_aon_tl
+ index: -1
+ }
+ ]
+ }
+ {
+ name: sensor_ctrl_aon
+ type: sensor_ctrl
+ clock_srcs:
+ {
+ clk_i: io_div4
+ }
+ clock_group: secure
+ clock_reset_export:
+ [
+ ast
+ ]
+ reset_connections:
+ {
+ rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]
+ }
+ domain: Aon
+ base_addr: 0x40500000
+ top_only: "true"
+ clock_connections:
+ {
+ clk_i: clkmgr_aon_clocks.clk_io_div4_secure
+ }
+ size: 0x1000
+ bus_device: tlul
+ bus_host: none
+ available_input_list: []
+ available_output_list: []
+ available_inout_list: []
+ param_list: []
+ interrupt_list: []
+ alert_list:
+ [
+ {
+ name: recov_as
+ width: 1
+ bits: "0"
+ bitinfo:
+ [
+ 1
+ 1
+ 0
+ ]
+ type: alert
+ async: 0
+ }
+ {
+ name: recov_cg
+ width: 1
+ bits: "1"
+ bitinfo:
+ [
+ 2
+ 1
+ 1
+ ]
+ type: alert
+ async: 0
+ }
+ {
+ name: recov_gd
+ width: 1
+ bits: "2"
+ bitinfo:
+ [
+ 4
+ 1
+ 2
+ ]
+ type: alert
+ async: 0
+ }
+ {
+ name: recov_ts_hi
+ width: 1
+ bits: "3"
+ bitinfo:
+ [
+ 8
+ 1
+ 3
+ ]
+ type: alert
+ async: 0
+ }
+ {
+ name: recov_ts_lo
+ width: 1
+ bits: "4"
+ bitinfo:
+ [
+ 16
+ 1
+ 4
+ ]
+ type: alert
+ async: 0
+ }
+ {
+ name: recov_ls
+ width: 1
+ bits: "5"
+ bitinfo:
+ [
+ 32
+ 1
+ 5
+ ]
+ type: alert
+ async: 0
+ }
+ {
+ name: recov_ot
+ width: 1
+ bits: "6"
+ bitinfo:
+ [
+ 64
+ 1
+ 6
+ ]
+ type: alert
+ async: 0
+ }
+ ]
+ wakeup_list: []
+ reset_request_list: []
+ scan: "false"
+ scan_reset: "false"
+ inter_signal_list:
+ [
+ {
+ struct: ast_alert
+ type: req_rsp
+ name: ast_alert
+ act: rsp
+ package: ast_wrapper_pkg
+ inst_name: sensor_ctrl_aon
+ width: 1
+ default: ""
+ external: true
+ top_signame: sensor_ctrl_ast_alert
+ index: -1
+ }
+ {
+ struct: ast_status
+ type: uni
+ name: ast_status
+ act: rcv
+ package: ast_wrapper_pkg
+ inst_name: sensor_ctrl_aon
+ width: 1
+ default: ""
+ external: true
+ top_signame: sensor_ctrl_ast_status
+ index: -1
+ }
+ {
+ struct: tl
+ package: tlul_pkg
+ type: req_rsp
+ act: rsp
+ name: tl
+ inst_name: sensor_ctrl_aon
+ width: 1
+ default: ""
+ top_signame: sensor_ctrl_aon_tl
+ index: -1
+ }
+ ]
+ }
+ {
+ name: sram_ctrl_ret_aon
type: sram_ctrl
clock_srcs:
{
@@ -4623,15 +4623,15 @@
clock_group: peri
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]
- rst_otp_ni: rstmgr_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]
+ rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]
+ rst_otp_ni: rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]
}
domain: Aon
base_addr: 0x40510000
clock_connections:
{
- clk_i: clkmgr_clocks.clk_io_div4_peri
- clk_otp_i: clkmgr_clocks.clk_io_div4_peri
+ clk_i: clkmgr_aon_clocks.clk_io_div4_peri
+ clk_otp_i: clkmgr_aon_clocks.clk_io_div4_peri
}
size: 0x1000
bus_device: tlul
@@ -4650,7 +4650,7 @@
local: "false"
default: 0x83d0550b80e84eb1f4c3471c5def7861
expose: "false"
- name_top: RndCnstSramCtrlRetSramKey
+ name_top: RndCnstSramCtrlRetAonSramKey
randwidth: 128
}
{
@@ -4662,7 +4662,7 @@
local: "false"
default: 0x2d73930d4cac3785
expose: "false"
- name_top: RndCnstSramCtrlRetSramNonce
+ name_top: RndCnstSramCtrlRetAonSramNonce
randwidth: 64
}
]
@@ -4696,7 +4696,7 @@
act: req
default: "'0"
package: otp_ctrl_pkg
- inst_name: sram_ctrl_ret
+ inst_name: sram_ctrl_ret_aon
width: 1
top_signame: otp_ctrl_sram_otp_key
index: 1
@@ -4708,9 +4708,9 @@
act: req
default: "'0"
package: sram_ctrl_pkg
- inst_name: sram_ctrl_ret
+ inst_name: sram_ctrl_ret_aon
width: 1
- top_signame: sram_ctrl_ret_sram_scr
+ top_signame: sram_ctrl_ret_aon_sram_scr
index: -1
}
{
@@ -4720,7 +4720,7 @@
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
- inst_name: sram_ctrl_ret
+ inst_name: sram_ctrl_ret_aon
width: 1
top_signame: lc_ctrl_lc_escalate_en
index: -1
@@ -4731,10 +4731,10 @@
type: req_rsp
act: rsp
name: tl
- inst_name: sram_ctrl_ret
+ inst_name: sram_ctrl_ret_aon
width: 1
default: ""
- top_signame: sram_ctrl_ret_tl
+ top_signame: sram_ctrl_ret_aon_tl
index: -1
}
]
@@ -4750,15 +4750,15 @@
clock_group: infra
reset_connections:
{
- rst_ni: rstmgr_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]
- rst_otp_ni: rstmgr_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]
+ rst_otp_ni: rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41000000
generated: "true"
clock_connections:
{
- clk_i: clkmgr_clocks.clk_main_infra
- clk_otp_i: clkmgr_clocks.clk_io_div4_infra
+ clk_i: clkmgr_aon_clocks.clk_main_infra
+ clk_otp_i: clkmgr_aon_clocks.clk_io_div4_infra
}
domain: "0"
size: 0x1000
@@ -5061,7 +5061,7 @@
inst_name: flash_ctrl
width: 1
default: ""
- top_signame: pwrmgr_pwr_flash
+ top_signame: pwrmgr_aon_pwr_flash
index: -1
}
{
@@ -5101,13 +5101,13 @@
clock_group: secure
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41010000
generated: "true"
clock_connections:
{
- clk_i: clkmgr_clocks.clk_main_secure
+ clk_i: clkmgr_aon_clocks.clk_main_secure
}
domain: "0"
size: 0x1000
@@ -5149,12 +5149,12 @@
clock_group: trans
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41100000
clock_connections:
{
- clk_i: clkmgr_clocks.clk_main_aes
+ clk_i: clkmgr_aon_clocks.clk_main_aes
}
domain: "0"
size: 0x1000
@@ -5334,7 +5334,7 @@
width: 1
inst_name: aes
default: ""
- top_signame: clkmgr_idle
+ top_signame: clkmgr_aon_idle
index: 0
}
{
@@ -5361,12 +5361,12 @@
clock_group: trans
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41110000
clock_connections:
{
- clk_i: clkmgr_clocks.clk_main_hmac
+ clk_i: clkmgr_aon_clocks.clk_main_hmac
}
domain: "0"
size: 0x1000
@@ -5431,7 +5431,7 @@
width: 1
inst_name: hmac
default: ""
- top_signame: clkmgr_idle
+ top_signame: clkmgr_aon_idle
index: 1
}
{
@@ -5459,14 +5459,14 @@
clock_group: trans
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
- rst_edn_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ rst_edn_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41120000
clock_connections:
{
- clk_i: clkmgr_clocks.clk_main_kmac
- clk_edn_i: clkmgr_clocks.clk_main_kmac
+ clk_i: clkmgr_aon_clocks.clk_main_kmac
+ clk_edn_i: clkmgr_aon_clocks.clk_main_kmac
}
domain: "0"
size: 0x1000
@@ -5602,7 +5602,7 @@
width: 1
inst_name: kmac
default: ""
- top_signame: clkmgr_idle
+ top_signame: clkmgr_aon_idle
index: 2
}
{
@@ -5630,14 +5630,14 @@
clock_group: secure
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
- rst_edn_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ rst_edn_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41130000
clock_connections:
{
- clk_i: clkmgr_clocks.clk_main_secure
- clk_edn_i: clkmgr_clocks.clk_main_secure
+ clk_i: clkmgr_aon_clocks.clk_main_secure
+ clk_edn_i: clkmgr_aon_clocks.clk_main_secure
}
domain: "0"
size: 0x1000
@@ -5989,12 +5989,12 @@
clock_group: secure
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41150000
clock_connections:
{
- clk_i: clkmgr_clocks.clk_main_secure
+ clk_i: clkmgr_aon_clocks.clk_main_secure
}
domain: "0"
size: 0x1000
@@ -6143,12 +6143,12 @@
clock_group: secure
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41160000
clock_connections:
{
- clk_i: clkmgr_clocks.clk_main_secure
+ clk_i: clkmgr_aon_clocks.clk_main_secure
}
domain: "0"
size: 0x1000
@@ -6283,12 +6283,12 @@
clock_group: secure
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41170000
clock_connections:
{
- clk_i: clkmgr_clocks.clk_main_secure
+ clk_i: clkmgr_aon_clocks.clk_main_secure
}
domain: "0"
size: 0x1000
@@ -6388,12 +6388,12 @@
clock_group: secure
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x41180000
clock_connections:
{
- clk_i: clkmgr_clocks.clk_main_secure
+ clk_i: clkmgr_aon_clocks.clk_main_secure
}
domain: "0"
size: 0x1000
@@ -6494,14 +6494,14 @@
clock_group: secure
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
- rst_otp_ni: rstmgr_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ rst_otp_ni: rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x411C0000
clock_connections:
{
- clk_i: clkmgr_clocks.clk_main_secure
- clk_otp_i: clkmgr_clocks.clk_io_div4_secure
+ clk_i: clkmgr_aon_clocks.clk_main_secure
+ clk_otp_i: clkmgr_aon_clocks.clk_io_div4_secure
}
domain: "0"
size: 0x1000
@@ -6620,12 +6620,12 @@
clock_group: trans
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
base_addr: 0x411D0000
clock_connections:
{
- clk_i: clkmgr_clocks.clk_main_otbn
+ clk_i: clkmgr_aon_clocks.clk_main_otbn
}
domain: "0"
size: 0x10000
@@ -6707,7 +6707,7 @@
inst_name: otbn
default: ""
package: ""
- top_signame: clkmgr_idle
+ top_signame: clkmgr_aon_idle
index: 3
}
{
@@ -6736,7 +6736,7 @@
clock_group: infra
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
type: rom
base_addr: 0x00008000
@@ -6759,7 +6759,7 @@
]
clock_connections:
{
- clk_i: clkmgr_clocks.clk_main_infra
+ clk_i: clkmgr_aon_clocks.clk_main_infra
}
domain: "0"
}
@@ -6772,7 +6772,7 @@
clock_group: infra
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
}
type: ram_1p_scr
base_addr: 0x10000000
@@ -6807,12 +6807,12 @@
]
clock_connections:
{
- clk_i: clkmgr_clocks.clk_main_infra
+ clk_i: clkmgr_aon_clocks.clk_main_infra
}
domain: "0"
}
{
- name: ram_ret
+ name: ram_ret_aon
clock_srcs:
{
clk_i: io_div4
@@ -6820,7 +6820,7 @@
clock_group: infra
reset_connections:
{
- rst_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]
+ rst_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]
}
domain: Aon
type: ram_1p_scr
@@ -6835,10 +6835,10 @@
type: req_rsp
act: rsp
name: tl
- inst_name: ram_ret
+ inst_name: ram_ret_aon
width: 1
default: ""
- top_signame: ram_ret_tl
+ top_signame: ram_ret_aon_tl
index: -1
}
{
@@ -6847,16 +6847,16 @@
type: req_rsp
name: sram_scr
act: rsp
- inst_name: ram_ret
+ inst_name: ram_ret_aon
width: 1
default: ""
- top_signame: sram_ctrl_ret_sram_scr
+ top_signame: sram_ctrl_ret_aon_sram_scr
index: -1
}
]
clock_connections:
{
- clk_i: clkmgr_clocks.clk_io_div4_infra
+ clk_i: clkmgr_aon_clocks.clk_io_div4_infra
}
}
{
@@ -6868,7 +6868,7 @@
clock_group: infra
reset_connections:
{
- rst_ni: rstmgr_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]
+ rst_ni: rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]
}
type: eflash
base_addr: 0x20000000
@@ -6982,7 +6982,7 @@
]
clock_connections:
{
- clk_i: clkmgr_clocks.clk_main_infra
+ clk_i: clkmgr_aon_clocks.clk_main_infra
}
words_per_page: 256
data_width: 64
@@ -7005,21 +7005,21 @@
{
alert_handler.crashdump:
[
- rstmgr.alert_dump
+ rstmgr_aon.alert_dump
]
alert_handler.esc_rx:
[
rv_core_ibex.esc_nmi_rx
lc_ctrl.esc_wipe_secrets_rx
lc_ctrl.esc_scrap_state_rx
- pwrmgr.esc_rst_rx
+ pwrmgr_aon.esc_rst_rx
]
alert_handler.esc_tx:
[
rv_core_ibex.esc_nmi_tx
lc_ctrl.esc_wipe_secrets_tx
lc_ctrl.esc_scrap_state_tx
- pwrmgr.esc_rst_tx
+ pwrmgr_aon.esc_rst_tx
]
csrng.csrng_cmd:
[
@@ -7058,56 +7058,56 @@
[
ram_main.sram_scr
]
- sram_ctrl_ret.sram_scr:
+ sram_ctrl_ret_aon.sram_scr:
[
- ram_ret.sram_scr
+ ram_ret_aon.sram_scr
]
otp_ctrl.sram_otp_key:
[
sram_ctrl_main.sram_otp_key
- sram_ctrl_ret.sram_otp_key
+ sram_ctrl_ret_aon.sram_otp_key
]
- pwrmgr.pwr_flash:
+ pwrmgr_aon.pwr_flash:
[
flash_ctrl.pwrmgr
]
- pwrmgr.pwr_rst:
+ pwrmgr_aon.pwr_rst:
[
- rstmgr.pwr
+ rstmgr_aon.pwr
]
- pwrmgr.pwr_clk:
+ pwrmgr_aon.pwr_clk:
[
- clkmgr.pwr
+ clkmgr_aon.pwr
]
- pwrmgr.pwr_otp:
+ pwrmgr_aon.pwr_otp:
[
otp_ctrl.pwr_otp
]
- pwrmgr.pwr_lc:
+ pwrmgr_aon.pwr_lc:
[
lc_ctrl.pwr_lc
]
rv_core_ibex.crashdump:
[
- rstmgr.cpu_dump
+ rstmgr_aon.cpu_dump
]
usbdev.usb_out_of_rst:
[
- pinmux.usb_out_of_rst
+ pinmux_aon.usb_out_of_rst
]
usbdev.usb_aon_wake_en:
[
- pinmux.usb_aon_wake_en
+ pinmux_aon.usb_aon_wake_en
]
usbdev.usb_aon_wake_ack:
[
- pinmux.usb_aon_wake_ack
+ pinmux_aon.usb_aon_wake_ack
]
usbdev.usb_suspend:
[
- pinmux.usb_suspend
+ pinmux_aon.usb_suspend
]
- pinmux.usb_state_debug:
+ pinmux_aon.usb_state_debug:
[
usbdev.usb_state_debug
]
@@ -7123,7 +7123,7 @@
[
kmac.keymgr_kdf
]
- clkmgr.idle:
+ clkmgr_aon.idle:
[
aes.idle
hmac.idle
@@ -7165,7 +7165,7 @@
[
otp_ctrl.lc_escalate_en
sram_ctrl_main.lc_escalate_en
- sram_ctrl_ret.lc_escalate_en
+ sram_ctrl_ret_aon.lc_escalate_en
]
lc_ctrl.lc_check_byp_en:
[
@@ -7174,7 +7174,7 @@
lc_ctrl.lc_clk_byp_req: []
lc_ctrl.lc_clk_byp_ack:
[
- clkmgr.lc_clk_bypass_ack
+ clkmgr_aon.lc_clk_bypass_ack
]
lc_ctrl.lc_creator_seed_sw_rw_en:
[
@@ -7198,11 +7198,11 @@
otp_ctrl.lc_seed_hw_rd_en
flash_ctrl.lc_seed_hw_rd_en
]
- pwrmgr.wakeups:
+ pwrmgr_aon.wakeups:
[
- pinmux.aon_wkup_req
+ pinmux_aon.aon_wkup_req
]
- pwrmgr.rstreqs:
+ pwrmgr_aon.rstreqs:
[
nmi_gen.nmi_rst_req
]
@@ -7258,14 +7258,6 @@
[
main.tl_rv_plic
]
- pinmux.tl:
- [
- main.tl_pinmux
- ]
- padctrl.tl:
- [
- main.tl_padctrl
- ]
otbn.tl:
[
main.tl_otbn
@@ -7326,21 +7318,29 @@
[
peri.tl_usbdev
]
- pwrmgr.tl:
+ pwrmgr_aon.tl:
[
- peri.tl_pwrmgr
+ peri.tl_pwrmgr_aon
]
- rstmgr.tl:
+ rstmgr_aon.tl:
[
- peri.tl_rstmgr
+ peri.tl_rstmgr_aon
]
- clkmgr.tl:
+ clkmgr_aon.tl:
[
- peri.tl_clkmgr
+ peri.tl_clkmgr_aon
]
- ram_ret.tl:
+ pinmux_aon.tl:
[
- peri.tl_ram_ret
+ peri.tl_pinmux_aon
+ ]
+ padctrl_aon.tl:
+ [
+ peri.tl_padctrl_aon
+ ]
+ ram_ret_aon.tl:
+ [
+ peri.tl_ram_ret_aon
]
otp_ctrl.tl:
[
@@ -7350,17 +7350,17 @@
[
peri.tl_lc_ctrl
]
- sensor_ctrl.tl:
+ sensor_ctrl_aon.tl:
[
- peri.tl_sensor_ctrl
+ peri.tl_sensor_ctrl_aon
]
alert_handler.tl:
[
peri.tl_alert_handler
]
- sram_ctrl_ret.tl:
+ sram_ctrl_ret_aon.tl:
[
- peri.tl_sram_ctrl_ret
+ peri.tl_sram_ctrl_ret_aon
]
nmi_gen.tl:
[
@@ -7369,10 +7369,10 @@
}
top:
[
- rstmgr.resets
- rstmgr.cpu
- pwrmgr.pwr_cpu
- clkmgr.clocks
+ rstmgr_aon.resets
+ rstmgr_aon.cpu
+ pwrmgr_aon.pwr_cpu
+ clkmgr_aon.clocks
main.tl_corei
main.tl_cored
main.tl_dm_sba
@@ -7380,14 +7380,14 @@
]
external:
{
- clkmgr.clk_main: clk_main
- clkmgr.clk_io: clk_io
- clkmgr.clk_usb: clk_usb
- clkmgr.clk_aon: clk_aon
- rstmgr.ast: ""
- pwrmgr.pwr_ast: ""
- sensor_ctrl.ast_alert: ""
- sensor_ctrl.ast_status: ""
+ clkmgr_aon.clk_main: clk_main
+ clkmgr_aon.clk_io: clk_io
+ clkmgr_aon.clk_usb: clk_usb
+ clkmgr_aon.clk_aon: clk_aon
+ rstmgr_aon.ast: rstmgr_ast
+ pwrmgr_aon.pwr_ast: pwrmgr_ast
+ sensor_ctrl_aon.ast_alert: sensor_ctrl_ast_alert
+ sensor_ctrl_aon.ast_status: sensor_ctrl_ast_status
usbdev.usb_ref_val: ""
usbdev.usb_ref_pulse: ""
peri.tl_ast_wrapper: ast_tl
@@ -7398,8 +7398,8 @@
eflash.flash_power_ready_h: flash_power_ready_h
eflash.flash_test_mode_a: flash_test_mode_a
eflash.flash_test_voltage_h: flash_test_voltage_h
- clkmgr.clocks_ast: clks_ast
- rstmgr.resets_ast: rsts_ast
+ clkmgr_aon.clocks_ast: clks_ast
+ rstmgr_aon.resets_ast: rsts_ast
}
}
xbar:
@@ -7415,13 +7415,13 @@
reset: rst_main_ni
reset_connections:
{
- rst_main_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
- rst_fixed_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
+ rst_main_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ rst_fixed_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
clock_connections:
{
- clk_main_i: clkmgr_clocks.clk_main_infra
- clk_fixed_i: clkmgr_clocks.clk_io_div4_infra
+ clk_main_i: clkmgr_aon_clocks.clk_main_infra
+ clk_fixed_i: clkmgr_aon_clocks.clk_io_div4_infra
}
domain: "0"
connections:
@@ -7448,8 +7448,6 @@
edn1
hmac
rv_plic
- pinmux
- padctrl
otbn
keymgr
kmac
@@ -7469,8 +7467,6 @@
edn1
hmac
rv_plic
- pinmux
- padctrl
otbn
kmac
sram_ctrl_main
@@ -7596,11 +7592,7 @@
[
{
base_addr: 0x40000000
- size_byte: 0x421000
- }
- {
- base_addr: 0x40500000
- size_byte: 0x21000
+ size_byte: 0x800000
}
]
}
@@ -7767,42 +7759,6 @@
pipeline: "true"
}
{
- name: pinmux
- type: device
- clock: clk_main_i
- reset: rst_fixed_ni
- inst_type: pinmux
- addr_range:
- [
- {
- base_addr: 0x40460000
- size_byte: 0x1000
- }
- ]
- pipeline_byp: "false"
- xbar: false
- stub: false
- pipeline: "true"
- }
- {
- name: padctrl
- type: device
- clock: clk_main_i
- reset: rst_fixed_ni
- inst_type: padctrl
- addr_range:
- [
- {
- base_addr: 0x40470000
- size_byte: 0x1000
- }
- ]
- pipeline_byp: "false"
- xbar: false
- stub: false
- pipeline: "true"
- }
- {
name: otbn
type: device
clock: clk_main_i
@@ -8068,30 +8024,6 @@
{
struct: tl
type: req_rsp
- name: tl_pinmux
- act: req
- package: tlul_pkg
- inst_name: main
- width: 1
- default: ""
- top_signame: pinmux_tl
- index: -1
- }
- {
- struct: tl
- type: req_rsp
- name: tl_padctrl
- act: req
- package: tlul_pkg
- inst_name: main
- width: 1
- default: ""
- top_signame: padctrl_tl
- index: -1
- }
- {
- struct: tl
- type: req_rsp
name: tl_otbn
act: req
package: tlul_pkg
@@ -8137,11 +8069,11 @@
reset: rst_peri_ni
reset_connections:
{
- rst_peri_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
+ rst_peri_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
clock_connections:
{
- clk_peri_i: clkmgr_clocks.clk_io_div4_infra
+ clk_peri_i: clkmgr_aon_clocks.clk_io_div4_infra
}
domain: "0"
connections:
@@ -8160,17 +8092,19 @@
spi_device
rv_timer
usbdev
- pwrmgr
- rstmgr
- clkmgr
- ram_ret
+ pwrmgr_aon
+ rstmgr_aon
+ clkmgr_aon
+ pinmux_aon
+ padctrl_aon
+ ram_ret_aon
otp_ctrl
lc_ctrl
- sensor_ctrl
+ sensor_ctrl_aon
alert_handler
nmi_gen
ast_wrapper
- sram_ctrl_ret
+ sram_ctrl_ret_aon
]
}
nodes:
@@ -8394,7 +8328,7 @@
addr_range:
[
{
- base_addr: 0x40500000
+ base_addr: 0x40110000
size_byte: 0x1000
}
]
@@ -8403,7 +8337,7 @@
pipeline_byp: "true"
}
{
- name: pwrmgr
+ name: pwrmgr_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
@@ -8421,7 +8355,7 @@
pipeline_byp: "true"
}
{
- name: rstmgr
+ name: rstmgr_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
@@ -8439,7 +8373,7 @@
pipeline_byp: "true"
}
{
- name: clkmgr
+ name: clkmgr_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
@@ -8457,7 +8391,43 @@
pipeline_byp: "true"
}
{
- name: ram_ret
+ name: pinmux_aon
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: "false"
+ inst_type: pinmux
+ addr_range:
+ [
+ {
+ base_addr: 0x40460000
+ size_byte: 0x1000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline_byp: "true"
+ }
+ {
+ name: padctrl_aon
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: "false"
+ inst_type: padctrl
+ addr_range:
+ [
+ {
+ base_addr: 0x40470000
+ size_byte: 0x1000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline_byp: "true"
+ }
+ {
+ name: ram_ret_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
@@ -8511,7 +8481,7 @@
pipeline_byp: "true"
}
{
- name: sensor_ctrl
+ name: sensor_ctrl_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
@@ -8520,7 +8490,7 @@
addr_range:
[
{
- base_addr: 0x40110000
+ base_addr: 0x40500000
size_byte: 0x1000
}
]
@@ -8547,7 +8517,7 @@
pipeline_byp: "true"
}
{
- name: sram_ctrl_ret
+ name: sram_ctrl_ret_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
@@ -8592,7 +8562,7 @@
addr_range:
[
{
- base_addr: 0x40180000
+ base_addr: 0x40490000
size_byte: 0x1000
}
]
@@ -8763,49 +8733,73 @@
{
struct: tl
type: req_rsp
- name: tl_pwrmgr
+ name: tl_pwrmgr_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
- top_signame: pwrmgr_tl
+ top_signame: pwrmgr_aon_tl
index: -1
}
{
struct: tl
type: req_rsp
- name: tl_rstmgr
+ name: tl_rstmgr_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
- top_signame: rstmgr_tl
+ top_signame: rstmgr_aon_tl
index: -1
}
{
struct: tl
type: req_rsp
- name: tl_clkmgr
+ name: tl_clkmgr_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
- top_signame: clkmgr_tl
+ top_signame: clkmgr_aon_tl
index: -1
}
{
struct: tl
type: req_rsp
- name: tl_ram_ret
+ name: tl_pinmux_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
- top_signame: ram_ret_tl
+ top_signame: pinmux_aon_tl
+ index: -1
+ }
+ {
+ struct: tl
+ type: req_rsp
+ name: tl_padctrl_aon
+ act: req
+ package: tlul_pkg
+ inst_name: peri
+ width: 1
+ default: ""
+ top_signame: padctrl_aon_tl
+ index: -1
+ }
+ {
+ struct: tl
+ type: req_rsp
+ name: tl_ram_ret_aon
+ act: req
+ package: tlul_pkg
+ inst_name: peri
+ width: 1
+ default: ""
+ top_signame: ram_ret_aon_tl
index: -1
}
{
@@ -8835,13 +8829,13 @@
{
struct: tl
type: req_rsp
- name: tl_sensor_ctrl
+ name: tl_sensor_ctrl_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
- top_signame: sensor_ctrl_tl
+ top_signame: sensor_ctrl_aon_tl
index: -1
}
{
@@ -8859,13 +8853,13 @@
{
struct: tl
type: req_rsp
- name: tl_sram_ctrl_ret
+ name: tl_sram_ctrl_ret_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
- top_signame: sram_ctrl_ret_tl
+ top_signame: sram_ctrl_ret_aon_tl
index: -1
}
{
@@ -8913,7 +8907,7 @@
alert_handler
nmi_gen
usbdev
- pwrmgr
+ pwrmgr_aon
otbn
keymgr
kmac
@@ -10499,7 +10493,7 @@
module_name: usbdev
}
{
- name: pwrmgr_wakeup
+ name: pwrmgr_aon_wakeup
width: 1
bits: "0"
bitinfo:
@@ -10509,7 +10503,7 @@
0
]
type: interrupt
- module_name: pwrmgr
+ module_name: pwrmgr_aon
}
{
name: otbn_done
@@ -10750,13 +10744,13 @@
[
aes
otbn
- sensor_ctrl
+ sensor_ctrl_aon
keymgr
otp_ctrl
lc_ctrl
entropy_src
sram_ctrl_main
- sram_ctrl_ret
+ sram_ctrl_ret_aon
flash_ctrl
]
alert:
@@ -10818,7 +10812,7 @@
module_name: otbn
}
{
- name: sensor_ctrl_recov_as
+ name: sensor_ctrl_aon_recov_as
width: 1
bits: "0"
bitinfo:
@@ -10829,10 +10823,10 @@
]
type: alert
async: 0
- module_name: sensor_ctrl
+ module_name: sensor_ctrl_aon
}
{
- name: sensor_ctrl_recov_cg
+ name: sensor_ctrl_aon_recov_cg
width: 1
bits: "1"
bitinfo:
@@ -10843,10 +10837,10 @@
]
type: alert
async: 0
- module_name: sensor_ctrl
+ module_name: sensor_ctrl_aon
}
{
- name: sensor_ctrl_recov_gd
+ name: sensor_ctrl_aon_recov_gd
width: 1
bits: "2"
bitinfo:
@@ -10857,10 +10851,10 @@
]
type: alert
async: 0
- module_name: sensor_ctrl
+ module_name: sensor_ctrl_aon
}
{
- name: sensor_ctrl_recov_ts_hi
+ name: sensor_ctrl_aon_recov_ts_hi
width: 1
bits: "3"
bitinfo:
@@ -10871,10 +10865,10 @@
]
type: alert
async: 0
- module_name: sensor_ctrl
+ module_name: sensor_ctrl_aon
}
{
- name: sensor_ctrl_recov_ts_lo
+ name: sensor_ctrl_aon_recov_ts_lo
width: 1
bits: "4"
bitinfo:
@@ -10885,10 +10879,10 @@
]
type: alert
async: 0
- module_name: sensor_ctrl
+ module_name: sensor_ctrl_aon
}
{
- name: sensor_ctrl_recov_ls
+ name: sensor_ctrl_aon_recov_ls
width: 1
bits: "5"
bitinfo:
@@ -10899,10 +10893,10 @@
]
type: alert
async: 0
- module_name: sensor_ctrl
+ module_name: sensor_ctrl_aon
}
{
- name: sensor_ctrl_recov_ot
+ name: sensor_ctrl_aon_recov_ot
width: 1
bits: "6"
bitinfo:
@@ -10913,7 +10907,7 @@
]
type: alert
async: 0
- module_name: sensor_ctrl
+ module_name: sensor_ctrl_aon
}
{
name: keymgr_fatal_fault_err
@@ -11028,7 +11022,7 @@
module_name: sram_ctrl_main
}
{
- name: sram_ctrl_ret_fatal_parity_error
+ name: sram_ctrl_ret_aon_fatal_parity_error
width: 1
bits: "0"
bitinfo:
@@ -11039,7 +11033,7 @@
]
type: alert
async: 0
- module_name: sram_ctrl_ret
+ module_name: sram_ctrl_ret_aon
}
{
name: flash_ctrl_recov_err
@@ -11478,16 +11472,16 @@
{
ast:
{
- sensor_ctrl:
- [
- io_div4_secure
- ]
usbdev:
[
io_div4_peri
aon_peri
usb_peri
]
+ sensor_ctrl_aon:
+ [
+ io_div4_secure
+ ]
}
}
wakeups:
@@ -11495,7 +11489,7 @@
{
name: aon_wkup_req
width: "1"
- module: pinmux
+ module: pinmux_aon
}
]
reset_requests:
@@ -11509,37 +11503,37 @@
{
ast:
{
- sensor_ctrl:
- [
- sys_io_div4
- ]
usbdev:
[
sys_io_div4
sys_aon
usb
]
+ sensor_ctrl_aon:
+ [
+ sys_io_div4
+ ]
}
}
reset_paths:
{
rst_ni: rst_ni
- por_aon: rstmgr_resets.rst_por_aon_n
- por: rstmgr_resets.rst_por_n
- por_io: rstmgr_resets.rst_por_io_n
- por_io_div2: rstmgr_resets.rst_por_io_div2_n
- por_io_div4: rstmgr_resets.rst_por_io_div4_n
- por_usb: rstmgr_resets.rst_por_usb_n
- lc: rstmgr_resets.rst_lc_n
- lc_io_div4: rstmgr_resets.rst_lc_io_div4_n
- sys: rstmgr_resets.rst_sys_n
- sys_io_div4: rstmgr_resets.rst_sys_io_div4_n
- sys_aon: rstmgr_resets.rst_sys_aon_n
- spi_device: rstmgr_resets.rst_spi_device_n
- usb: rstmgr_resets.rst_usb_n
- i2c0: rstmgr_resets.rst_i2c0_n
- i2c1: rstmgr_resets.rst_i2c1_n
- i2c2: rstmgr_resets.rst_i2c2_n
+ por_aon: rstmgr_aon_resets.rst_por_aon_n
+ por: rstmgr_aon_resets.rst_por_n
+ por_io: rstmgr_aon_resets.rst_por_io_n
+ por_io_div2: rstmgr_aon_resets.rst_por_io_div2_n
+ por_io_div4: rstmgr_aon_resets.rst_por_io_div4_n
+ por_usb: rstmgr_aon_resets.rst_por_usb_n
+ lc: rstmgr_aon_resets.rst_lc_n
+ lc_io_div4: rstmgr_aon_resets.rst_lc_io_div4_n
+ sys: rstmgr_aon_resets.rst_sys_n
+ sys_io_div4: rstmgr_aon_resets.rst_sys_io_div4_n
+ sys_aon: rstmgr_aon_resets.rst_sys_aon_n
+ spi_device: rstmgr_aon_resets.rst_spi_device_n
+ usb: rstmgr_aon_resets.rst_usb_n
+ i2c0: rstmgr_aon_resets.rst_i2c0_n
+ i2c1: rstmgr_aon_resets.rst_i2c1_n
+ i2c2: rstmgr_aon_resets.rst_i2c2_n
}
inter_signal:
{
@@ -11678,29 +11672,93 @@
index: -1
}
{
- struct: ast_alert
- type: req_rsp
- name: ast_alert
- act: rsp
- package: ast_wrapper_pkg
- inst_name: sensor_ctrl
+ name: usb_ref_val
+ type: uni
+ act: req
+ package: ""
+ struct: logic
width: 1
+ inst_name: usbdev
default: ""
external: true
- top_signame: sensor_ctrl_ast_alert
+ top_signame: usbdev_usb_ref_val
index: -1
}
{
- struct: ast_status
+ name: usb_ref_pulse
type: uni
- name: ast_status
- act: rcv
- package: ast_wrapper_pkg
- inst_name: sensor_ctrl
+ act: req
+ package: ""
+ struct: logic
width: 1
+ inst_name: usbdev
default: ""
external: true
- top_signame: sensor_ctrl_ast_status
+ top_signame: usbdev_usb_ref_pulse
+ index: -1
+ }
+ {
+ name: usb_out_of_rst
+ type: uni
+ act: req
+ package: ""
+ struct: logic
+ width: 1
+ inst_name: usbdev
+ default: ""
+ top_type: broadcast
+ top_signame: usbdev_usb_out_of_rst
+ index: -1
+ }
+ {
+ name: usb_aon_wake_en
+ type: uni
+ act: req
+ package: ""
+ struct: logic
+ width: 1
+ inst_name: usbdev
+ default: ""
+ top_type: broadcast
+ top_signame: usbdev_usb_aon_wake_en
+ index: -1
+ }
+ {
+ name: usb_aon_wake_ack
+ type: uni
+ act: req
+ package: ""
+ struct: logic
+ width: 1
+ inst_name: usbdev
+ default: ""
+ top_type: broadcast
+ top_signame: usbdev_usb_aon_wake_ack
+ index: -1
+ }
+ {
+ name: usb_suspend
+ type: uni
+ act: req
+ package: ""
+ struct: logic
+ width: 1
+ inst_name: usbdev
+ default: ""
+ top_type: broadcast
+ top_signame: usbdev_usb_suspend
+ index: -1
+ }
+ {
+ name: usb_state_debug
+ type: uni
+ act: rcv
+ package: usbdev_pkg
+ struct: awk_state
+ inst_name: usbdev
+ width: 1
+ default: ""
+ top_signame: pinmux_aon_usb_state_debug
index: -1
}
{
@@ -11709,10 +11767,10 @@
type: req_rsp
act: rsp
name: tl
- inst_name: sensor_ctrl
+ inst_name: usbdev
width: 1
default: ""
- top_signame: sensor_ctrl_tl
+ top_signame: usbdev_tl
index: -1
}
{
@@ -11759,7 +11817,7 @@
package: pwrmgr_pkg
inst_name: otp_ctrl
width: 1
- top_signame: pwrmgr_pwr_otp
+ top_signame: pwrmgr_aon_pwr_otp
index: -1
}
{
@@ -11997,7 +12055,7 @@
inst_name: lc_ctrl
width: 1
default: ""
- top_signame: pwrmgr_pwr_lc
+ top_signame: pwrmgr_aon_pwr_lc
index: -1
}
{
@@ -12357,7 +12415,7 @@
default: 1'b0
inst_name: nmi_gen
width: 1
- top_signame: pwrmgr_rstreqs
+ top_signame: pwrmgr_aon_rstreqs
index: -1
}
{
@@ -12397,11 +12455,11 @@
name: pwr_ast
act: req
package: pwrmgr_pkg
- inst_name: pwrmgr
+ inst_name: pwrmgr_aon
width: 1
default: ""
external: true
- top_signame: pwrmgr_pwr_ast
+ top_signame: pwrmgr_ast
index: -1
}
{
@@ -12410,10 +12468,10 @@
name: pwr_rst
act: req
package: pwrmgr_pkg
- inst_name: pwrmgr
+ inst_name: pwrmgr_aon
width: 1
default: ""
- top_signame: pwrmgr_pwr_rst
+ top_signame: pwrmgr_aon_pwr_rst
index: -1
}
{
@@ -12422,10 +12480,10 @@
name: pwr_clk
act: req
package: pwrmgr_pkg
- inst_name: pwrmgr
+ inst_name: pwrmgr_aon
width: 1
default: ""
- top_signame: pwrmgr_pwr_clk
+ top_signame: pwrmgr_aon_pwr_clk
index: -1
}
{
@@ -12434,10 +12492,10 @@
name: pwr_otp
act: req
package: pwrmgr_pkg
- inst_name: pwrmgr
+ inst_name: pwrmgr_aon
width: 1
default: ""
- top_signame: pwrmgr_pwr_otp
+ top_signame: pwrmgr_aon_pwr_otp
index: -1
}
{
@@ -12446,10 +12504,10 @@
name: pwr_lc
act: req
package: pwrmgr_pkg
- inst_name: pwrmgr
+ inst_name: pwrmgr_aon
width: 1
default: ""
- top_signame: pwrmgr_pwr_lc
+ top_signame: pwrmgr_aon_pwr_lc
index: -1
}
{
@@ -12458,10 +12516,10 @@
name: pwr_flash
act: req
package: pwrmgr_pkg
- inst_name: pwrmgr
+ inst_name: pwrmgr_aon
width: 1
default: ""
- top_signame: pwrmgr_pwr_flash
+ top_signame: pwrmgr_aon_pwr_flash
index: -1
}
{
@@ -12470,7 +12528,7 @@
name: esc_rst_tx
act: rcv
package: prim_esc_pkg
- inst_name: pwrmgr
+ inst_name: pwrmgr_aon
width: 1
default: ""
top_signame: alert_handler_esc_tx
@@ -12482,7 +12540,7 @@
name: esc_rst_rx
act: req
package: prim_esc_pkg
- inst_name: pwrmgr
+ inst_name: pwrmgr_aon
width: 1
default: ""
top_signame: alert_handler_esc_rx
@@ -12494,10 +12552,10 @@
name: pwr_cpu
act: rcv
package: pwrmgr_pkg
- inst_name: pwrmgr
+ inst_name: pwrmgr_aon
width: 1
default: ""
- top_signame: pwrmgr_pwr_cpu
+ top_signame: pwrmgr_aon_pwr_cpu
index: -1
}
{
@@ -12507,10 +12565,10 @@
name: wakeups
act: rcv
package: ""
- inst_name: pwrmgr
+ inst_name: pwrmgr_aon
default: ""
top_type: broadcast
- top_signame: pwrmgr_wakeups
+ top_signame: pwrmgr_aon_wakeups
index: -1
}
{
@@ -12520,10 +12578,10 @@
name: rstreqs
act: rcv
package: ""
- inst_name: pwrmgr
+ inst_name: pwrmgr_aon
default: ""
top_type: broadcast
- top_signame: pwrmgr_rstreqs
+ top_signame: pwrmgr_aon_rstreqs
index: -1
}
{
@@ -12532,10 +12590,10 @@
type: req_rsp
act: rsp
name: tl
- inst_name: pwrmgr
+ inst_name: pwrmgr_aon
width: 1
default: ""
- top_signame: pwrmgr_tl
+ top_signame: pwrmgr_aon_tl
index: -1
}
{
@@ -12543,11 +12601,11 @@
type: req_rsp
name: pwr
act: rsp
- inst_name: rstmgr
+ inst_name: rstmgr_aon
width: 1
default: ""
package: pwrmgr_pkg
- top_signame: pwrmgr_pwr_rst
+ top_signame: pwrmgr_aon_pwr_rst
index: -1
}
{
@@ -12556,10 +12614,10 @@
name: resets
act: req
package: rstmgr_pkg
- inst_name: rstmgr
+ inst_name: rstmgr_aon
width: 1
default: ""
- top_signame: rstmgr_resets
+ top_signame: rstmgr_aon_resets
index: -1
}
{
@@ -12568,7 +12626,7 @@
name: ast
act: rcv
package: rstmgr_pkg
- inst_name: rstmgr
+ inst_name: rstmgr_aon
width: 1
default: ""
external: true
@@ -12581,10 +12639,10 @@
name: cpu
act: rcv
package: rstmgr_pkg
- inst_name: rstmgr
+ inst_name: rstmgr_aon
width: 1
default: ""
- top_signame: rstmgr_cpu
+ top_signame: rstmgr_aon_cpu
index: -1
}
{
@@ -12593,7 +12651,7 @@
name: alert_dump
act: rcv
package: alert_pkg
- inst_name: rstmgr
+ inst_name: rstmgr_aon
width: 1
default: ""
top_signame: alert_handler_crashdump
@@ -12605,7 +12663,7 @@
name: cpu_dump
act: rcv
package: rv_core_ibex_pkg
- inst_name: rstmgr
+ inst_name: rstmgr_aon
width: 1
default: ""
top_signame: rv_core_ibex_crashdump
@@ -12617,7 +12675,7 @@
name: resets_ast
act: req
package: rstmgr_pkg
- inst_name: rstmgr
+ inst_name: rstmgr_aon
width: 1
default: ""
external: true
@@ -12630,10 +12688,10 @@
type: req_rsp
act: rsp
name: tl
- inst_name: rstmgr
+ inst_name: rstmgr_aon
width: 1
default: ""
- top_signame: rstmgr_tl
+ top_signame: rstmgr_aon_tl
index: -1
}
{
@@ -12642,10 +12700,10 @@
name: clocks
act: req
package: clkmgr_pkg
- inst_name: clkmgr
+ inst_name: clkmgr_aon
width: 1
default: ""
- top_signame: clkmgr_clocks
+ top_signame: clkmgr_aon_clocks
index: -1
}
{
@@ -12654,7 +12712,7 @@
name: ast_clk_bypass_ack
act: rcv
package: lc_ctrl_pkg
- inst_name: clkmgr
+ inst_name: clkmgr_aon
index: -1
}
{
@@ -12663,7 +12721,7 @@
name: lc_clk_bypass_ack
act: req
package: lc_ctrl_pkg
- inst_name: clkmgr
+ inst_name: clkmgr_aon
width: 1
default: ""
top_signame: lc_ctrl_lc_clk_byp_ack
@@ -12675,7 +12733,7 @@
name: clk_main
act: rcv
package: ""
- inst_name: clkmgr
+ inst_name: clkmgr_aon
width: 1
default: ""
external: true
@@ -12688,7 +12746,7 @@
name: clk_io
act: rcv
package: ""
- inst_name: clkmgr
+ inst_name: clkmgr_aon
width: 1
default: ""
external: true
@@ -12701,7 +12759,7 @@
name: clk_usb
act: rcv
package: ""
- inst_name: clkmgr
+ inst_name: clkmgr_aon
width: 1
default: ""
external: true
@@ -12714,7 +12772,7 @@
name: clk_aon
act: rcv
package: ""
- inst_name: clkmgr
+ inst_name: clkmgr_aon
width: 1
default: ""
external: true
@@ -12727,7 +12785,7 @@
name: clocks_ast
act: req
package: clkmgr_pkg
- inst_name: clkmgr
+ inst_name: clkmgr_aon
width: 1
default: ""
external: true
@@ -12739,11 +12797,11 @@
type: req_rsp
name: pwr
act: rsp
- inst_name: clkmgr
+ inst_name: clkmgr_aon
width: 1
default: ""
package: pwrmgr_pkg
- top_signame: pwrmgr_pwr_clk
+ top_signame: pwrmgr_aon_pwr_clk
index: -1
}
{
@@ -12753,10 +12811,10 @@
act: rcv
package: ""
width: 4
- inst_name: clkmgr
+ inst_name: clkmgr_aon
default: ""
top_type: one-to-N
- top_signame: clkmgr_idle
+ top_signame: clkmgr_aon_idle
index: -1
}
{
@@ -12765,10 +12823,10 @@
type: req_rsp
act: rsp
name: tl
- inst_name: clkmgr
+ inst_name: clkmgr_aon
width: 1
default: ""
- top_signame: clkmgr_tl
+ top_signame: clkmgr_aon_tl
index: -1
}
{
@@ -12778,7 +12836,7 @@
act: rsp
package: pinmux_pkg
default: "'0"
- inst_name: pinmux
+ inst_name: pinmux_aon
index: -1
}
{
@@ -12788,7 +12846,7 @@
act: req
package: pinmux_pkg
default: "'0"
- inst_name: pinmux
+ inst_name: pinmux_aon
index: -1
}
{
@@ -12798,7 +12856,7 @@
act: rcv
package: pinmux_pkg
default: "{pinmux_pkg::NIOPokSignals{1'b1}}"
- inst_name: pinmux
+ inst_name: pinmux_aon
index: -1
}
{
@@ -12808,7 +12866,7 @@
act: rcv
package: ""
default: 1'b0
- inst_name: pinmux
+ inst_name: pinmux_aon
index: -1
}
{
@@ -12818,9 +12876,9 @@
act: req
package: ""
default: 1'b0
- inst_name: pinmux
+ inst_name: pinmux_aon
width: 1
- top_signame: pwrmgr_wakeups
+ top_signame: pwrmgr_aon_wakeups
index: -1
}
{
@@ -12830,7 +12888,7 @@
act: req
package: ""
default: 1'b0
- inst_name: pinmux
+ inst_name: pinmux_aon
index: -1
}
{
@@ -12840,7 +12898,7 @@
package: ""
struct: logic
width: 1
- inst_name: pinmux
+ inst_name: pinmux_aon
default: ""
top_signame: usbdev_usb_out_of_rst
index: -1
@@ -12852,7 +12910,7 @@
package: ""
struct: logic
width: 1
- inst_name: pinmux
+ inst_name: pinmux_aon
default: ""
top_signame: usbdev_usb_aon_wake_en
index: -1
@@ -12864,7 +12922,7 @@
package: ""
struct: logic
width: 1
- inst_name: pinmux
+ inst_name: pinmux_aon
default: ""
top_signame: usbdev_usb_aon_wake_ack
index: -1
@@ -12876,7 +12934,7 @@
package: ""
struct: logic
width: 1
- inst_name: pinmux
+ inst_name: pinmux_aon
default: ""
top_signame: usbdev_usb_suspend
index: -1
@@ -12887,11 +12945,11 @@
act: req
package: usbdev_pkg
struct: awk_state
- inst_name: pinmux
+ inst_name: pinmux_aon
width: 1
default: ""
top_type: broadcast
- top_signame: pinmux_usb_state_debug
+ top_signame: pinmux_aon_usb_state_debug
index: -1
}
{
@@ -12900,10 +12958,10 @@
type: req_rsp
act: rsp
name: tl
- inst_name: pinmux
+ inst_name: pinmux_aon
width: 1
default: ""
- top_signame: pinmux_tl
+ top_signame: pinmux_aon_tl
index: -1
}
{
@@ -12912,100 +12970,36 @@
type: req_rsp
act: rsp
name: tl
- inst_name: padctrl
+ inst_name: padctrl_aon
width: 1
default: ""
- top_signame: padctrl_tl
+ top_signame: padctrl_aon_tl
index: -1
}
{
- name: usb_ref_val
- type: uni
- act: req
- package: ""
- struct: logic
+ struct: ast_alert
+ type: req_rsp
+ name: ast_alert
+ act: rsp
+ package: ast_wrapper_pkg
+ inst_name: sensor_ctrl_aon
width: 1
- inst_name: usbdev
default: ""
external: true
- top_signame: usbdev_usb_ref_val
+ top_signame: sensor_ctrl_ast_alert
index: -1
}
{
- name: usb_ref_pulse
+ struct: ast_status
type: uni
- act: req
- package: ""
- struct: logic
- width: 1
- inst_name: usbdev
- default: ""
- external: true
- top_signame: usbdev_usb_ref_pulse
- index: -1
- }
- {
- name: usb_out_of_rst
- type: uni
- act: req
- package: ""
- struct: logic
- width: 1
- inst_name: usbdev
- default: ""
- top_type: broadcast
- top_signame: usbdev_usb_out_of_rst
- index: -1
- }
- {
- name: usb_aon_wake_en
- type: uni
- act: req
- package: ""
- struct: logic
- width: 1
- inst_name: usbdev
- default: ""
- top_type: broadcast
- top_signame: usbdev_usb_aon_wake_en
- index: -1
- }
- {
- name: usb_aon_wake_ack
- type: uni
- act: req
- package: ""
- struct: logic
- width: 1
- inst_name: usbdev
- default: ""
- top_type: broadcast
- top_signame: usbdev_usb_aon_wake_ack
- index: -1
- }
- {
- name: usb_suspend
- type: uni
- act: req
- package: ""
- struct: logic
- width: 1
- inst_name: usbdev
- default: ""
- top_type: broadcast
- top_signame: usbdev_usb_suspend
- index: -1
- }
- {
- name: usb_state_debug
- type: uni
+ name: ast_status
act: rcv
- package: usbdev_pkg
- struct: awk_state
- inst_name: usbdev
+ package: ast_wrapper_pkg
+ inst_name: sensor_ctrl_aon
width: 1
default: ""
- top_signame: pinmux_usb_state_debug
+ external: true
+ top_signame: sensor_ctrl_ast_status
index: -1
}
{
@@ -13014,10 +13008,10 @@
type: req_rsp
act: rsp
name: tl
- inst_name: usbdev
+ inst_name: sensor_ctrl_aon
width: 1
default: ""
- top_signame: usbdev_tl
+ top_signame: sensor_ctrl_aon_tl
index: -1
}
{
@@ -13027,7 +13021,7 @@
act: req
default: "'0"
package: otp_ctrl_pkg
- inst_name: sram_ctrl_ret
+ inst_name: sram_ctrl_ret_aon
width: 1
top_signame: otp_ctrl_sram_otp_key
index: 1
@@ -13039,9 +13033,9 @@
act: req
default: "'0"
package: sram_ctrl_pkg
- inst_name: sram_ctrl_ret
+ inst_name: sram_ctrl_ret_aon
width: 1
- top_signame: sram_ctrl_ret_sram_scr
+ top_signame: sram_ctrl_ret_aon_sram_scr
index: -1
}
{
@@ -13051,7 +13045,7 @@
act: rcv
default: lc_ctrl_pkg::Off
package: lc_ctrl_pkg
- inst_name: sram_ctrl_ret
+ inst_name: sram_ctrl_ret_aon
width: 1
top_signame: lc_ctrl_lc_escalate_en
index: -1
@@ -13062,10 +13056,10 @@
type: req_rsp
act: rsp
name: tl
- inst_name: sram_ctrl_ret
+ inst_name: sram_ctrl_ret_aon
width: 1
default: ""
- top_signame: sram_ctrl_ret_tl
+ top_signame: sram_ctrl_ret_aon_tl
index: -1
}
{
@@ -13200,7 +13194,7 @@
inst_name: flash_ctrl
width: 1
default: ""
- top_signame: pwrmgr_pwr_flash
+ top_signame: pwrmgr_aon_pwr_flash
index: -1
}
{
@@ -13249,7 +13243,7 @@
width: 1
inst_name: aes
default: ""
- top_signame: clkmgr_idle
+ top_signame: clkmgr_aon_idle
index: 0
}
{
@@ -13273,7 +13267,7 @@
width: 1
inst_name: hmac
default: ""
- top_signame: clkmgr_idle
+ top_signame: clkmgr_aon_idle
index: 1
}
{
@@ -13331,7 +13325,7 @@
width: 1
inst_name: kmac
default: ""
- top_signame: clkmgr_idle
+ top_signame: clkmgr_aon_idle
index: 2
}
{
@@ -13721,7 +13715,7 @@
inst_name: otbn
default: ""
package: ""
- top_signame: clkmgr_idle
+ top_signame: clkmgr_aon_idle
index: 3
}
{
@@ -13778,10 +13772,10 @@
type: req_rsp
act: rsp
name: tl
- inst_name: ram_ret
+ inst_name: ram_ret_aon
width: 1
default: ""
- top_signame: ram_ret_tl
+ top_signame: ram_ret_aon_tl
index: -1
}
{
@@ -13790,10 +13784,10 @@
type: req_rsp
name: sram_scr
act: rsp
- inst_name: ram_ret
+ inst_name: ram_ret_aon
width: 1
default: ""
- top_signame: sram_ctrl_ret_sram_scr
+ top_signame: sram_ctrl_ret_aon_sram_scr
index: -1
}
{
@@ -14104,30 +14098,6 @@
{
struct: tl
type: req_rsp
- name: tl_pinmux
- act: req
- package: tlul_pkg
- inst_name: main
- width: 1
- default: ""
- top_signame: pinmux_tl
- index: -1
- }
- {
- struct: tl
- type: req_rsp
- name: tl_padctrl
- act: req
- package: tlul_pkg
- inst_name: main
- width: 1
- default: ""
- top_signame: padctrl_tl
- index: -1
- }
- {
- struct: tl
- type: req_rsp
name: tl_otbn
act: req
package: tlul_pkg
@@ -14320,49 +14290,73 @@
{
struct: tl
type: req_rsp
- name: tl_pwrmgr
+ name: tl_pwrmgr_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
- top_signame: pwrmgr_tl
+ top_signame: pwrmgr_aon_tl
index: -1
}
{
struct: tl
type: req_rsp
- name: tl_rstmgr
+ name: tl_rstmgr_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
- top_signame: rstmgr_tl
+ top_signame: rstmgr_aon_tl
index: -1
}
{
struct: tl
type: req_rsp
- name: tl_clkmgr
+ name: tl_clkmgr_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
- top_signame: clkmgr_tl
+ top_signame: clkmgr_aon_tl
index: -1
}
{
struct: tl
type: req_rsp
- name: tl_ram_ret
+ name: tl_pinmux_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
- top_signame: ram_ret_tl
+ top_signame: pinmux_aon_tl
+ index: -1
+ }
+ {
+ struct: tl
+ type: req_rsp
+ name: tl_padctrl_aon
+ act: req
+ package: tlul_pkg
+ inst_name: peri
+ width: 1
+ default: ""
+ top_signame: padctrl_aon_tl
+ index: -1
+ }
+ {
+ struct: tl
+ type: req_rsp
+ name: tl_ram_ret_aon
+ act: req
+ package: tlul_pkg
+ inst_name: peri
+ width: 1
+ default: ""
+ top_signame: ram_ret_aon_tl
index: -1
}
{
@@ -14392,13 +14386,13 @@
{
struct: tl
type: req_rsp
- name: tl_sensor_ctrl
+ name: tl_sensor_ctrl_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
- top_signame: sensor_ctrl_tl
+ top_signame: sensor_ctrl_aon_tl
index: -1
}
{
@@ -14416,13 +14410,13 @@
{
struct: tl
type: req_rsp
- name: tl_sram_ctrl_ret
+ name: tl_sram_ctrl_ret_aon
act: req
package: tlul_pkg
inst_name: peri
width: 1
default: ""
- top_signame: sram_ctrl_ret_tl
+ top_signame: sram_ctrl_ret_aon_tl
index: -1
}
{
@@ -14538,7 +14532,7 @@
{
package: pwrmgr_pkg
struct: pwr_ast_req
- signame: pwrmgr_pwr_ast_req_o
+ signame: pwrmgr_ast_req_o
width: 1
type: req_rsp
default: ""
@@ -14547,7 +14541,7 @@
{
package: pwrmgr_pkg
struct: pwr_ast_rsp
- signame: pwrmgr_pwr_ast_rsp_i
+ signame: pwrmgr_ast_rsp_i
width: 1
type: req_rsp
default: ""
@@ -14839,7 +14833,7 @@
{
package: sram_ctrl_pkg
struct: sram_scr_req
- signame: sram_ctrl_ret_sram_scr_req
+ signame: sram_ctrl_ret_aon_sram_scr_req
width: 1
type: req_rsp
default: "'0"
@@ -14847,7 +14841,7 @@
{
package: sram_ctrl_pkg
struct: sram_scr_rsp
- signame: sram_ctrl_ret_sram_scr_rsp
+ signame: sram_ctrl_ret_aon_sram_scr_rsp
width: 1
type: req_rsp
default: "'0"
@@ -14871,7 +14865,7 @@
{
package: pwrmgr_pkg
struct: pwr_flash_req
- signame: pwrmgr_pwr_flash_req
+ signame: pwrmgr_aon_pwr_flash_req
width: 1
type: req_rsp
default: ""
@@ -14879,7 +14873,7 @@
{
package: pwrmgr_pkg
struct: pwr_flash_rsp
- signame: pwrmgr_pwr_flash_rsp
+ signame: pwrmgr_aon_pwr_flash_rsp
width: 1
type: req_rsp
default: ""
@@ -14887,7 +14881,7 @@
{
package: pwrmgr_pkg
struct: pwr_rst_req
- signame: pwrmgr_pwr_rst_req
+ signame: pwrmgr_aon_pwr_rst_req
width: 1
type: req_rsp
default: ""
@@ -14895,7 +14889,7 @@
{
package: pwrmgr_pkg
struct: pwr_rst_rsp
- signame: pwrmgr_pwr_rst_rsp
+ signame: pwrmgr_aon_pwr_rst_rsp
width: 1
type: req_rsp
default: ""
@@ -14903,7 +14897,7 @@
{
package: pwrmgr_pkg
struct: pwr_clk_req
- signame: pwrmgr_pwr_clk_req
+ signame: pwrmgr_aon_pwr_clk_req
width: 1
type: req_rsp
default: ""
@@ -14911,7 +14905,7 @@
{
package: pwrmgr_pkg
struct: pwr_clk_rsp
- signame: pwrmgr_pwr_clk_rsp
+ signame: pwrmgr_aon_pwr_clk_rsp
width: 1
type: req_rsp
default: ""
@@ -14919,7 +14913,7 @@
{
package: pwrmgr_pkg
struct: pwr_otp_req
- signame: pwrmgr_pwr_otp_req
+ signame: pwrmgr_aon_pwr_otp_req
width: 1
type: req_rsp
default: ""
@@ -14927,7 +14921,7 @@
{
package: pwrmgr_pkg
struct: pwr_otp_rsp
- signame: pwrmgr_pwr_otp_rsp
+ signame: pwrmgr_aon_pwr_otp_rsp
width: 1
type: req_rsp
default: ""
@@ -14935,7 +14929,7 @@
{
package: pwrmgr_pkg
struct: pwr_lc_req
- signame: pwrmgr_pwr_lc_req
+ signame: pwrmgr_aon_pwr_lc_req
width: 1
type: req_rsp
default: ""
@@ -14943,7 +14937,7 @@
{
package: pwrmgr_pkg
struct: pwr_lc_rsp
- signame: pwrmgr_pwr_lc_rsp
+ signame: pwrmgr_aon_pwr_lc_rsp
width: 1
type: req_rsp
default: ""
@@ -14991,7 +14985,7 @@
{
package: usbdev_pkg
struct: awk_state
- signame: pinmux_usb_state_debug
+ signame: pinmux_aon_usb_state_debug
width: 1
type: uni
default: ""
@@ -15031,7 +15025,7 @@
{
package: ""
struct: logic
- signame: clkmgr_idle
+ signame: clkmgr_aon_idle
width: 4
type: uni
default: ""
@@ -15199,7 +15193,7 @@
{
package: ""
struct: logic
- signame: pwrmgr_wakeups
+ signame: pwrmgr_aon_wakeups
width: 1
type: uni
default: ""
@@ -15207,7 +15201,7 @@
{
package: ""
struct: logic
- signame: pwrmgr_rstreqs
+ signame: pwrmgr_aon_rstreqs
width: 1
type: uni
default: ""
@@ -15423,38 +15417,6 @@
{
package: tlul_pkg
struct: tl_h2d
- signame: pinmux_tl_req
- width: 1
- type: req_rsp
- default: ""
- }
- {
- package: tlul_pkg
- struct: tl_d2h
- signame: pinmux_tl_rsp
- width: 1
- type: req_rsp
- default: ""
- }
- {
- package: tlul_pkg
- struct: tl_h2d
- signame: padctrl_tl_req
- width: 1
- type: req_rsp
- default: ""
- }
- {
- package: tlul_pkg
- struct: tl_d2h
- signame: padctrl_tl_rsp
- width: 1
- type: req_rsp
- default: ""
- }
- {
- package: tlul_pkg
- struct: tl_h2d
signame: otbn_tl_req
width: 1
type: req_rsp
@@ -15695,7 +15657,7 @@
{
package: tlul_pkg
struct: tl_h2d
- signame: pwrmgr_tl_req
+ signame: pwrmgr_aon_tl_req
width: 1
type: req_rsp
default: ""
@@ -15703,7 +15665,7 @@
{
package: tlul_pkg
struct: tl_d2h
- signame: pwrmgr_tl_rsp
+ signame: pwrmgr_aon_tl_rsp
width: 1
type: req_rsp
default: ""
@@ -15711,7 +15673,7 @@
{
package: tlul_pkg
struct: tl_h2d
- signame: rstmgr_tl_req
+ signame: rstmgr_aon_tl_req
width: 1
type: req_rsp
default: ""
@@ -15719,7 +15681,7 @@
{
package: tlul_pkg
struct: tl_d2h
- signame: rstmgr_tl_rsp
+ signame: rstmgr_aon_tl_rsp
width: 1
type: req_rsp
default: ""
@@ -15727,7 +15689,7 @@
{
package: tlul_pkg
struct: tl_h2d
- signame: clkmgr_tl_req
+ signame: clkmgr_aon_tl_req
width: 1
type: req_rsp
default: ""
@@ -15735,7 +15697,7 @@
{
package: tlul_pkg
struct: tl_d2h
- signame: clkmgr_tl_rsp
+ signame: clkmgr_aon_tl_rsp
width: 1
type: req_rsp
default: ""
@@ -15743,7 +15705,7 @@
{
package: tlul_pkg
struct: tl_h2d
- signame: ram_ret_tl_req
+ signame: pinmux_aon_tl_req
width: 1
type: req_rsp
default: ""
@@ -15751,7 +15713,39 @@
{
package: tlul_pkg
struct: tl_d2h
- signame: ram_ret_tl_rsp
+ signame: pinmux_aon_tl_rsp
+ width: 1
+ type: req_rsp
+ default: ""
+ }
+ {
+ package: tlul_pkg
+ struct: tl_h2d
+ signame: padctrl_aon_tl_req
+ width: 1
+ type: req_rsp
+ default: ""
+ }
+ {
+ package: tlul_pkg
+ struct: tl_d2h
+ signame: padctrl_aon_tl_rsp
+ width: 1
+ type: req_rsp
+ default: ""
+ }
+ {
+ package: tlul_pkg
+ struct: tl_h2d
+ signame: ram_ret_aon_tl_req
+ width: 1
+ type: req_rsp
+ default: ""
+ }
+ {
+ package: tlul_pkg
+ struct: tl_d2h
+ signame: ram_ret_aon_tl_rsp
width: 1
type: req_rsp
default: ""
@@ -15791,7 +15785,7 @@
{
package: tlul_pkg
struct: tl_h2d
- signame: sensor_ctrl_tl_req
+ signame: sensor_ctrl_aon_tl_req
width: 1
type: req_rsp
default: ""
@@ -15799,7 +15793,7 @@
{
package: tlul_pkg
struct: tl_d2h
- signame: sensor_ctrl_tl_rsp
+ signame: sensor_ctrl_aon_tl_rsp
width: 1
type: req_rsp
default: ""
@@ -15823,7 +15817,7 @@
{
package: tlul_pkg
struct: tl_h2d
- signame: sram_ctrl_ret_tl_req
+ signame: sram_ctrl_ret_aon_tl_req
width: 1
type: req_rsp
default: ""
@@ -15831,7 +15825,7 @@
{
package: tlul_pkg
struct: tl_d2h
- signame: sram_ctrl_ret_tl_rsp
+ signame: sram_ctrl_ret_aon_tl_rsp
width: 1
type: req_rsp
default: ""
@@ -15855,7 +15849,7 @@
{
package: rstmgr_pkg
struct: rstmgr_out
- signame: rstmgr_resets
+ signame: rstmgr_aon_resets
width: 1
type: uni
default: ""
@@ -15863,7 +15857,7 @@
{
package: rstmgr_pkg
struct: rstmgr_cpu
- signame: rstmgr_cpu
+ signame: rstmgr_aon_cpu
width: 1
type: uni
default: ""
@@ -15871,7 +15865,7 @@
{
package: pwrmgr_pkg
struct: pwr_cpu
- signame: pwrmgr_pwr_cpu
+ signame: pwrmgr_aon_pwr_cpu
width: 1
type: uni
default: ""
@@ -15879,7 +15873,7 @@
{
package: clkmgr_pkg
struct: clkmgr_out
- signame: clkmgr_clocks
+ signame: clkmgr_aon_clocks
width: 1
type: uni
default: ""
diff --git a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
index a7d3284..b5f25a7 100644
--- a/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
+++ b/hw/top_earlgrey/dv/autogen/tb__alert_handler_connect.sv
@@ -8,13 +8,13 @@
assign alert_if[1].alert_tx = `CHIP_HIER.u_aes.alert_tx_o[1];
assign alert_if[2].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[0];
assign alert_if[3].alert_tx = `CHIP_HIER.u_otbn.alert_tx_o[1];
-assign alert_if[4].alert_tx = `CHIP_HIER.u_sensor_ctrl.alert_tx_o[0];
-assign alert_if[5].alert_tx = `CHIP_HIER.u_sensor_ctrl.alert_tx_o[1];
-assign alert_if[6].alert_tx = `CHIP_HIER.u_sensor_ctrl.alert_tx_o[2];
-assign alert_if[7].alert_tx = `CHIP_HIER.u_sensor_ctrl.alert_tx_o[3];
-assign alert_if[8].alert_tx = `CHIP_HIER.u_sensor_ctrl.alert_tx_o[4];
-assign alert_if[9].alert_tx = `CHIP_HIER.u_sensor_ctrl.alert_tx_o[5];
-assign alert_if[10].alert_tx = `CHIP_HIER.u_sensor_ctrl.alert_tx_o[6];
+assign alert_if[4].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[0];
+assign alert_if[5].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[1];
+assign alert_if[6].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[2];
+assign alert_if[7].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[3];
+assign alert_if[8].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[4];
+assign alert_if[9].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[5];
+assign alert_if[10].alert_tx = `CHIP_HIER.u_sensor_ctrl_aon.alert_tx_o[6];
assign alert_if[11].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[0];
assign alert_if[12].alert_tx = `CHIP_HIER.u_keymgr.alert_tx_o[1];
assign alert_if[13].alert_tx = `CHIP_HIER.u_otp_ctrl.alert_tx_o[0];
@@ -23,7 +23,7 @@
assign alert_if[16].alert_tx = `CHIP_HIER.u_lc_ctrl.alert_tx_o[1];
assign alert_if[17].alert_tx = `CHIP_HIER.u_entropy_src.alert_tx_o[0];
assign alert_if[18].alert_tx = `CHIP_HIER.u_sram_ctrl_main.alert_tx_o[0];
-assign alert_if[19].alert_tx = `CHIP_HIER.u_sram_ctrl_ret.alert_tx_o[0];
+assign alert_if[19].alert_tx = `CHIP_HIER.u_sram_ctrl_ret_aon.alert_tx_o[0];
assign alert_if[20].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[0];
assign alert_if[21].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[1];
assign alert_if[22].alert_tx = `CHIP_HIER.u_flash_ctrl.alert_tx_o[2];
diff --git a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
index 0259a9f..7fcbc62 100644
--- a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
+++ b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
@@ -46,8 +46,6 @@
tl_if edn0_tl_if(clk_main, rst_n);
tl_if edn1_tl_if(clk_main, rst_n);
tl_if rv_plic_tl_if(clk_main, rst_n);
-tl_if pinmux_tl_if(clk_main, rst_n);
-tl_if padctrl_tl_if(clk_main, rst_n);
tl_if otbn_tl_if(clk_main, rst_n);
tl_if keymgr_tl_if(clk_main, rst_n);
tl_if sram_ctrl_main_tl_if(clk_main, rst_n);
@@ -63,15 +61,17 @@
tl_if spi_device_tl_if(clk_io_div4, rst_n);
tl_if rv_timer_tl_if(clk_io_div4, rst_n);
tl_if usbdev_tl_if(clk_io_div4, rst_n);
-tl_if pwrmgr_tl_if(clk_io_div4, rst_n);
-tl_if rstmgr_tl_if(clk_io_div4, rst_n);
-tl_if clkmgr_tl_if(clk_io_div4, rst_n);
-tl_if ram_ret_tl_if(clk_io_div4, rst_n);
+tl_if pwrmgr_aon_tl_if(clk_io_div4, rst_n);
+tl_if rstmgr_aon_tl_if(clk_io_div4, rst_n);
+tl_if clkmgr_aon_tl_if(clk_io_div4, rst_n);
+tl_if pinmux_aon_tl_if(clk_io_div4, rst_n);
+tl_if padctrl_aon_tl_if(clk_io_div4, rst_n);
+tl_if ram_ret_aon_tl_if(clk_io_div4, rst_n);
tl_if otp_ctrl_tl_if(clk_io_div4, rst_n);
tl_if lc_ctrl_tl_if(clk_io_div4, rst_n);
-tl_if sensor_ctrl_tl_if(clk_io_div4, rst_n);
+tl_if sensor_ctrl_aon_tl_if(clk_io_div4, rst_n);
tl_if alert_handler_tl_if(clk_io_div4, rst_n);
-tl_if sram_ctrl_ret_tl_if(clk_io_div4, rst_n);
+tl_if sram_ctrl_ret_aon_tl_if(clk_io_div4, rst_n);
tl_if nmi_gen_tl_if(clk_io_div4, rst_n);
tl_if ast_wrapper_tl_if(clk_io_div4, rst_n);
@@ -115,8 +115,6 @@
`DRIVE_CHIP_TL_DEVICE_IF(edn0, edn0, tl)
`DRIVE_CHIP_TL_DEVICE_IF(edn1, edn1, tl)
`DRIVE_CHIP_TL_DEVICE_IF(rv_plic, rv_plic, tl)
- `DRIVE_CHIP_TL_DEVICE_IF(pinmux, pinmux, tl)
- `DRIVE_CHIP_TL_DEVICE_IF(padctrl, padctrl, tl)
`DRIVE_CHIP_TL_DEVICE_IF(otbn, otbn, tl)
`DRIVE_CHIP_TL_DEVICE_IF(keymgr, keymgr, tl)
`DRIVE_CHIP_TL_DEVICE_IF(sram_ctrl_main, sram_ctrl_main, tl)
@@ -132,15 +130,17 @@
`DRIVE_CHIP_TL_DEVICE_IF(spi_device, spi_device, tl)
`DRIVE_CHIP_TL_DEVICE_IF(rv_timer, rv_timer, tl)
`DRIVE_CHIP_TL_DEVICE_IF(usbdev, usbdev, tl)
- `DRIVE_CHIP_TL_DEVICE_IF(pwrmgr, pwrmgr, tl)
- `DRIVE_CHIP_TL_DEVICE_IF(rstmgr, rstmgr, tl)
- `DRIVE_CHIP_TL_DEVICE_IF(clkmgr, clkmgr, tl)
- `DRIVE_CHIP_TL_DEVICE_IF(ram_ret, tl_adapter_ram_ret, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(pwrmgr_aon, pwrmgr_aon, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(rstmgr_aon, rstmgr_aon, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(clkmgr_aon, clkmgr_aon, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(pinmux_aon, pinmux_aon, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(padctrl_aon, padctrl_aon, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(ram_ret_aon, tl_adapter_ram_ret_aon, tl)
`DRIVE_CHIP_TL_DEVICE_IF(otp_ctrl, otp_ctrl, tl)
`DRIVE_CHIP_TL_DEVICE_IF(lc_ctrl, lc_ctrl, tl)
- `DRIVE_CHIP_TL_DEVICE_IF(sensor_ctrl, sensor_ctrl, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(sensor_ctrl_aon, sensor_ctrl_aon, tl)
`DRIVE_CHIP_TL_DEVICE_IF(alert_handler, alert_handler, tl)
- `DRIVE_CHIP_TL_DEVICE_IF(sram_ctrl_ret, sram_ctrl_ret, tl)
+ `DRIVE_CHIP_TL_DEVICE_IF(sram_ctrl_ret_aon, sram_ctrl_ret_aon, tl)
`DRIVE_CHIP_TL_DEVICE_IF(nmi_gen, nmi_gen, tl)
`DRIVE_CHIP_TL_EXT_DEVICE_IF(ast_wrapper, ast_tl)
end
diff --git a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
index 8440ace..7c03c89 100644
--- a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
+++ b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
@@ -46,12 +46,6 @@
'{"rv_plic", '{
'{32'h41010000, 32'h41010fff}
}},
- '{"pinmux", '{
- '{32'h40460000, 32'h40460fff}
- }},
- '{"padctrl", '{
- '{32'h40470000, 32'h40470fff}
- }},
'{"otbn", '{
'{32'h411d0000, 32'h411dffff}
}},
@@ -95,18 +89,24 @@
'{32'h40100000, 32'h40100fff}
}},
'{"usbdev", '{
- '{32'h40500000, 32'h40500fff}
+ '{32'h40110000, 32'h40110fff}
}},
- '{"pwrmgr", '{
+ '{"pwrmgr_aon", '{
'{32'h40400000, 32'h40400fff}
}},
- '{"rstmgr", '{
+ '{"rstmgr_aon", '{
'{32'h40410000, 32'h40410fff}
}},
- '{"clkmgr", '{
+ '{"clkmgr_aon", '{
'{32'h40420000, 32'h40420fff}
}},
- '{"ram_ret", '{
+ '{"pinmux_aon", '{
+ '{32'h40460000, 32'h40460fff}
+ }},
+ '{"padctrl_aon", '{
+ '{32'h40470000, 32'h40470fff}
+ }},
+ '{"ram_ret_aon", '{
'{32'h40520000, 32'h40520fff}
}},
'{"otp_ctrl", '{
@@ -115,20 +115,20 @@
'{"lc_ctrl", '{
'{32'h40140000, 32'h40140fff}
}},
- '{"sensor_ctrl", '{
- '{32'h40110000, 32'h40110fff}
+ '{"sensor_ctrl_aon", '{
+ '{32'h40500000, 32'h40500fff}
}},
'{"alert_handler", '{
'{32'h40150000, 32'h40150fff}
}},
- '{"sram_ctrl_ret", '{
+ '{"sram_ctrl_ret_aon", '{
'{32'h40510000, 32'h40510fff}
}},
'{"nmi_gen", '{
'{32'h40160000, 32'h40160fff}
}},
'{"ast_wrapper", '{
- '{32'h40180000, 32'h40180fff}
+ '{32'h40490000, 32'h40490fff}
}}};
// List of Xbar hosts
@@ -156,17 +156,19 @@
"spi_device",
"rv_timer",
"usbdev",
- "pwrmgr",
- "rstmgr",
- "clkmgr",
- "ram_ret",
+ "pwrmgr_aon",
+ "rstmgr_aon",
+ "clkmgr_aon",
+ "pinmux_aon",
+ "padctrl_aon",
+ "ram_ret_aon",
"otp_ctrl",
"lc_ctrl",
- "sensor_ctrl",
+ "sensor_ctrl_aon",
"alert_handler",
"nmi_gen",
"ast_wrapper",
- "sram_ctrl_ret",
+ "sram_ctrl_ret_aon",
"flash_ctrl",
"aes",
"entropy_src",
@@ -175,8 +177,6 @@
"edn1",
"hmac",
"rv_plic",
- "pinmux",
- "padctrl",
"otbn",
"keymgr",
"kmac",
@@ -198,17 +198,19 @@
"spi_device",
"rv_timer",
"usbdev",
- "pwrmgr",
- "rstmgr",
- "clkmgr",
- "ram_ret",
+ "pwrmgr_aon",
+ "rstmgr_aon",
+ "clkmgr_aon",
+ "pinmux_aon",
+ "padctrl_aon",
+ "ram_ret_aon",
"otp_ctrl",
"lc_ctrl",
- "sensor_ctrl",
+ "sensor_ctrl_aon",
"alert_handler",
"nmi_gen",
"ast_wrapper",
- "sram_ctrl_ret",
+ "sram_ctrl_ret_aon",
"flash_ctrl",
"aes",
"entropy_src",
@@ -217,8 +219,6 @@
"edn1",
"hmac",
"rv_plic",
- "pinmux",
- "padctrl",
"otbn",
"kmac",
"sram_ctrl_main"}}
diff --git a/hw/top_earlgrey/dv/env/autogen/alert_handler_env_pkg__params.sv b/hw/top_earlgrey/dv/env/autogen/alert_handler_env_pkg__params.sv
index e33f2c5..08608ac 100644
--- a/hw/top_earlgrey/dv/env/autogen/alert_handler_env_pkg__params.sv
+++ b/hw/top_earlgrey/dv/env/autogen/alert_handler_env_pkg__params.sv
@@ -9,13 +9,13 @@
"aes_fatal_fault",
"otbn_fatal",
"otbn_recov",
- "sensor_ctrl_recov_as",
- "sensor_ctrl_recov_cg",
- "sensor_ctrl_recov_gd",
- "sensor_ctrl_recov_ts_hi",
- "sensor_ctrl_recov_ts_lo",
- "sensor_ctrl_recov_ls",
- "sensor_ctrl_recov_ot",
+ "sensor_ctrl_aon_recov_as",
+ "sensor_ctrl_aon_recov_cg",
+ "sensor_ctrl_aon_recov_gd",
+ "sensor_ctrl_aon_recov_ts_hi",
+ "sensor_ctrl_aon_recov_ts_lo",
+ "sensor_ctrl_aon_recov_ls",
+ "sensor_ctrl_aon_recov_ot",
"keymgr_fatal_fault_err",
"keymgr_recov_operation_err",
"otp_ctrl_fatal_macro_error",
@@ -24,7 +24,7 @@
"lc_ctrl_fatal_state_error",
"entropy_src_recov_alert_count_met",
"sram_ctrl_main_fatal_parity_error",
- "sram_ctrl_ret_fatal_parity_error",
+ "sram_ctrl_ret_aon_fatal_parity_error",
"flash_ctrl_recov_err",
"flash_ctrl_recov_mp_err",
"flash_ctrl_recov_ecc_err"
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
index 0afe20c..8a0a1b2 100644
--- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
+++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr.sv
@@ -446,10 +446,10 @@
// Exported clocks
////////////////////////////////////////////////////
- assign clocks_ast_o.clk_ast_sensor_ctrl_io_div4_secure = clocks_o.clk_io_div4_secure;
assign clocks_ast_o.clk_ast_usbdev_io_div4_peri = clocks_o.clk_io_div4_peri;
assign clocks_ast_o.clk_ast_usbdev_aon_peri = clocks_o.clk_aon_peri;
assign clocks_ast_o.clk_ast_usbdev_usb_peri = clocks_o.clk_usb_peri;
+ assign clocks_ast_o.clk_ast_sensor_ctrl_aon_io_div4_secure = clocks_o.clk_io_div4_secure;
////////////////////////////////////////////////////
// Assertions
diff --git a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv
index 1ff9b76..9652869 100644
--- a/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv
+++ b/hw/top_earlgrey/ip/clkmgr/rtl/autogen/clkmgr_pkg.sv
@@ -45,10 +45,10 @@
} clkmgr_out_t;
typedef struct packed {
- logic clk_ast_sensor_ctrl_io_div4_secure;
logic clk_ast_usbdev_io_div4_peri;
logic clk_ast_usbdev_aon_peri;
logic clk_ast_usbdev_usb_peri;
+ logic clk_ast_sensor_ctrl_aon_io_div4_secure;
} clkmgr_ast_out_t;
typedef struct packed {
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
index ccf41e4..50887c2 100644
--- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
+++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
@@ -691,10 +691,10 @@
////////////////////////////////////////////////////
// Exported resets //
////////////////////////////////////////////////////
- assign resets_ast_o.rst_ast_sensor_ctrl_sys_io_div4_n = resets_o.rst_sys_io_div4_n;
assign resets_ast_o.rst_ast_usbdev_sys_io_div4_n = resets_o.rst_sys_io_div4_n;
assign resets_ast_o.rst_ast_usbdev_sys_aon_n = resets_o.rst_sys_aon_n;
assign resets_ast_o.rst_ast_usbdev_usb_n = resets_o.rst_usb_n;
+ assign resets_ast_o.rst_ast_sensor_ctrl_aon_sys_io_div4_n = resets_o.rst_sys_io_div4_n;
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv
index b4419c9..8c1737a 100644
--- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv
+++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv
@@ -68,10 +68,10 @@
// exported resets
typedef struct packed {
- logic [PowerDomains-1:0] rst_ast_sensor_ctrl_sys_io_div4_n;
logic [PowerDomains-1:0] rst_ast_usbdev_sys_io_div4_n;
logic [PowerDomains-1:0] rst_ast_usbdev_sys_aon_n;
logic [PowerDomains-1:0] rst_ast_usbdev_usb_n;
+ logic [PowerDomains-1:0] rst_ast_sensor_ctrl_aon_sys_io_div4_n;
} rstmgr_ast_out_t;
// default value for rstmgr_ast_rsp_t (for dangling ports)
diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
index 37ce57a..d06265f 100644
--- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
+++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
@@ -17,13 +17,13 @@
reset: rst_main_ni
reset_connections:
{
- rst_main_ni: rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
- rst_fixed_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
+ rst_main_ni: rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]
+ rst_fixed_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
clock_connections:
{
- clk_main_i: clkmgr_clocks.clk_main_infra
- clk_fixed_i: clkmgr_clocks.clk_io_div4_infra
+ clk_main_i: clkmgr_aon_clocks.clk_main_infra
+ clk_fixed_i: clkmgr_aon_clocks.clk_io_div4_infra
}
domain: "0"
connections:
@@ -50,8 +50,6 @@
edn1
hmac
rv_plic
- pinmux
- padctrl
otbn
keymgr
kmac
@@ -71,8 +69,6 @@
edn1
hmac
rv_plic
- pinmux
- padctrl
otbn
kmac
sram_ctrl_main
@@ -198,11 +194,7 @@
[
{
base_addr: 0x40000000
- size_byte: 0x421000
- }
- {
- base_addr: 0x40500000
- size_byte: 0x21000
+ size_byte: 0x800000
}
]
}
@@ -369,42 +361,6 @@
pipeline: "true"
}
{
- name: pinmux
- type: device
- clock: clk_main_i
- reset: rst_fixed_ni
- inst_type: pinmux
- addr_range:
- [
- {
- base_addr: 0x40460000
- size_byte: 0x1000
- }
- ]
- pipeline_byp: "false"
- xbar: false
- stub: false
- pipeline: "true"
- }
- {
- name: padctrl
- type: device
- clock: clk_main_i
- reset: rst_fixed_ni
- inst_type: padctrl
- addr_range:
- [
- {
- base_addr: 0x40470000
- size_byte: 0x1000
- }
- ]
- pipeline_byp: "false"
- xbar: false
- stub: false
- pipeline: "true"
- }
- {
name: otbn
type: device
clock: clk_main_i
diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson
index 1a34054..73a77cb 100644
--- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson
+++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson
@@ -117,18 +117,6 @@
}
{ struct: "tl"
type: "req_rsp"
- name: "tl_pinmux"
- act: "req"
- package: "tlul_pkg"
- }
- { struct: "tl"
- type: "req_rsp"
- name: "tl_padctrl"
- act: "req"
- package: "tlul_pkg"
- }
- { struct: "tl"
- type: "req_rsp"
name: "tl_otbn"
act: "req"
package: "tlul_pkg"
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv
index d481eb5..664569d 100644
--- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv
+++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv
@@ -36,8 +36,6 @@
`CONNECT_TL_DEVICE_IF(edn0, dut, clk_main_i, rst_n)
`CONNECT_TL_DEVICE_IF(edn1, dut, clk_main_i, rst_n)
`CONNECT_TL_DEVICE_IF(rv_plic, dut, clk_main_i, rst_n)
-`CONNECT_TL_DEVICE_IF(pinmux, dut, clk_main_i, rst_n)
-`CONNECT_TL_DEVICE_IF(padctrl, dut, clk_main_i, rst_n)
`CONNECT_TL_DEVICE_IF(otbn, dut, clk_main_i, rst_n)
`CONNECT_TL_DEVICE_IF(keymgr, dut, clk_main_i, rst_n)
`CONNECT_TL_DEVICE_IF(sram_ctrl_main, dut, clk_main_i, rst_n)
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg
index 22ed882..2ab49e7 100644
--- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg
+++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg
@@ -27,10 +27,8 @@
-node tb.dut tl_ram_main_o.a_address[31:29]
-node tb.dut tl_eflash_o.a_address[28:20]
-node tb.dut tl_eflash_o.a_address[31:30]
--node tb.dut tl_peri_o.a_address[16:12]
--node tb.dut tl_peri_o.a_address[19:18]
--node tb.dut tl_peri_o.a_address[21:21]
--node tb.dut tl_peri_o.a_address[31:23]
+-node tb.dut tl_peri_o.a_address[29:23]
+-node tb.dut tl_peri_o.a_address[31:31]
-node tb.dut tl_flash_ctrl_o.a_address[23:12]
-node tb.dut tl_flash_ctrl_o.a_address[29:25]
-node tb.dut tl_flash_ctrl_o.a_address[31:31]
@@ -72,14 +70,6 @@
-node tb.dut tl_rv_plic_o.a_address[23:17]
-node tb.dut tl_rv_plic_o.a_address[29:25]
-node tb.dut tl_rv_plic_o.a_address[31:31]
--node tb.dut tl_pinmux_o.a_address[16:12]
--node tb.dut tl_pinmux_o.a_address[21:19]
--node tb.dut tl_pinmux_o.a_address[29:23]
--node tb.dut tl_pinmux_o.a_address[31:31]
--node tb.dut tl_padctrl_o.a_address[15:12]
--node tb.dut tl_padctrl_o.a_address[21:19]
--node tb.dut tl_padctrl_o.a_address[29:23]
--node tb.dut tl_padctrl_o.a_address[31:31]
-node tb.dut tl_otbn_o.a_address[17:17]
-node tb.dut tl_otbn_o.a_address[23:21]
-node tb.dut tl_otbn_o.a_address[29:25]
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
index 26d043b..a105e6e 100644
--- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
+++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
@@ -20,8 +20,7 @@
'{32'h20000000, 32'h200fffff}
}},
'{"peri", '{
- '{32'h40000000, 32'h40420fff},
- '{32'h40500000, 32'h40520fff}
+ '{32'h40000000, 32'h407fffff}
}},
'{"flash_ctrl", '{
'{32'h41000000, 32'h41000fff}
@@ -50,12 +49,6 @@
'{"rv_plic", '{
'{32'h41010000, 32'h41010fff}
}},
- '{"pinmux", '{
- '{32'h40460000, 32'h40460fff}
- }},
- '{"padctrl", '{
- '{32'h40470000, 32'h40470fff}
- }},
'{"otbn", '{
'{32'h411d0000, 32'h411dffff}
}},
@@ -88,8 +81,6 @@
"edn1",
"hmac",
"rv_plic",
- "pinmux",
- "padctrl",
"otbn",
"keymgr",
"kmac",
@@ -108,8 +99,6 @@
"edn1",
"hmac",
"rv_plic",
- "pinmux",
- "padctrl",
"otbn",
"kmac",
"sram_ctrl_main"}}
diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv
index 335b1b8..ded1cdd 100644
--- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv
+++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv
@@ -110,18 +110,6 @@
.h2d (tl_rv_plic_o),
.d2h (tl_rv_plic_i)
);
- bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_pinmux (
- .clk_i (clk_main_i),
- .rst_ni (rst_fixed_ni),
- .h2d (tl_pinmux_o),
- .d2h (tl_pinmux_i)
- );
- bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_padctrl (
- .clk_i (clk_main_i),
- .rst_ni (rst_fixed_ni),
- .h2d (tl_padctrl_o),
- .d2h (tl_padctrl_i)
- );
bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_otbn (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
index ff61dad..0f81cff 100644
--- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
+++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
@@ -10,8 +10,7 @@
localparam logic [31:0] ADDR_SPACE_DEBUG_MEM = 32'h 1a110000;
localparam logic [31:0] ADDR_SPACE_RAM_MAIN = 32'h 10000000;
localparam logic [31:0] ADDR_SPACE_EFLASH = 32'h 20000000;
- localparam logic [1:0][31:0] ADDR_SPACE_PERI = {
- 32'h 40500000,
+ localparam logic [0:0][31:0] ADDR_SPACE_PERI = {
32'h 40000000
};
localparam logic [31:0] ADDR_SPACE_FLASH_CTRL = 32'h 41000000;
@@ -23,8 +22,6 @@
localparam logic [31:0] ADDR_SPACE_EDN0 = 32'h 41170000;
localparam logic [31:0] ADDR_SPACE_EDN1 = 32'h 41180000;
localparam logic [31:0] ADDR_SPACE_RV_PLIC = 32'h 41010000;
- localparam logic [31:0] ADDR_SPACE_PINMUX = 32'h 40460000;
- localparam logic [31:0] ADDR_SPACE_PADCTRL = 32'h 40470000;
localparam logic [31:0] ADDR_SPACE_OTBN = 32'h 411d0000;
localparam logic [31:0] ADDR_SPACE_KEYMGR = 32'h 41130000;
localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_MAIN = 32'h 411c0000;
@@ -33,9 +30,8 @@
localparam logic [31:0] ADDR_MASK_DEBUG_MEM = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_RAM_MAIN = 32'h 0001ffff;
localparam logic [31:0] ADDR_MASK_EFLASH = 32'h 000fffff;
- localparam logic [1:0][31:0] ADDR_MASK_PERI = {
- 32'h 00020fff,
- 32'h 00420fff
+ localparam logic [0:0][31:0] ADDR_MASK_PERI = {
+ 32'h 007fffff
};
localparam logic [31:0] ADDR_MASK_FLASH_CTRL = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_HMAC = 32'h 00000fff;
@@ -46,14 +42,12 @@
localparam logic [31:0] ADDR_MASK_EDN0 = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_EDN1 = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_RV_PLIC = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_PINMUX = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_PADCTRL = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_OTBN = 32'h 0000ffff;
localparam logic [31:0] ADDR_MASK_KEYMGR = 32'h 00000fff;
localparam logic [31:0] ADDR_MASK_SRAM_CTRL_MAIN = 32'h 00000fff;
localparam int N_HOST = 3;
- localparam int N_DEVICE = 19;
+ localparam int N_DEVICE = 17;
typedef enum int {
TlRom = 0,
@@ -70,11 +64,9 @@
TlEdn0 = 11,
TlEdn1 = 12,
TlRvPlic = 13,
- TlPinmux = 14,
- TlPadctrl = 15,
- TlOtbn = 16,
- TlKeymgr = 17,
- TlSramCtrlMain = 18
+ TlOtbn = 14,
+ TlKeymgr = 15,
+ TlSramCtrlMain = 16
} tl_device_e;
typedef enum int {
diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv
index d5a027d..2788515 100644
--- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv
+++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv
@@ -7,91 +7,83 @@
//
// Interconnect
// corei
-// -> s1n_22
-// -> sm1_23
+// -> s1n_20
+// -> sm1_21
// -> rom
-// -> sm1_24
+// -> sm1_22
// -> debug_mem
-// -> sm1_25
+// -> sm1_23
// -> ram_main
-// -> sm1_26
+// -> sm1_24
// -> eflash
// cored
-// -> s1n_27
-// -> sm1_23
+// -> s1n_25
+// -> sm1_21
// -> rom
-// -> sm1_24
+// -> sm1_22
// -> debug_mem
-// -> sm1_25
+// -> sm1_23
// -> ram_main
-// -> sm1_26
+// -> sm1_24
// -> eflash
-// -> sm1_29
-// -> asf_28
+// -> sm1_27
+// -> asf_26
// -> peri
-// -> sm1_30
+// -> sm1_28
// -> flash_ctrl
-// -> sm1_31
+// -> sm1_29
// -> aes
-// -> sm1_32
+// -> sm1_30
// -> entropy_src
-// -> sm1_33
+// -> sm1_31
// -> csrng
-// -> sm1_34
+// -> sm1_32
// -> edn0
-// -> sm1_35
+// -> sm1_33
// -> edn1
-// -> sm1_36
+// -> sm1_34
// -> hmac
-// -> sm1_37
+// -> sm1_35
// -> rv_plic
-// -> sm1_38
-// -> pinmux
-// -> sm1_39
-// -> padctrl
-// -> sm1_40
+// -> sm1_36
// -> otbn
// -> keymgr
-// -> sm1_41
+// -> sm1_37
// -> kmac
-// -> sm1_42
+// -> sm1_38
// -> sram_ctrl_main
// dm_sba
-// -> s1n_43
-// -> sm1_23
+// -> s1n_39
+// -> sm1_21
// -> rom
-// -> sm1_25
+// -> sm1_23
// -> ram_main
-// -> sm1_26
+// -> sm1_24
// -> eflash
-// -> sm1_29
-// -> asf_28
+// -> sm1_27
+// -> asf_26
// -> peri
-// -> sm1_30
+// -> sm1_28
// -> flash_ctrl
-// -> sm1_31
+// -> sm1_29
// -> aes
-// -> sm1_32
+// -> sm1_30
// -> entropy_src
-// -> sm1_33
+// -> sm1_31
// -> csrng
-// -> sm1_34
+// -> sm1_32
// -> edn0
-// -> sm1_35
+// -> sm1_33
// -> edn1
-// -> sm1_36
+// -> sm1_34
// -> hmac
-// -> sm1_37
+// -> sm1_35
// -> rv_plic
-// -> sm1_38
-// -> pinmux
-// -> sm1_39
-// -> padctrl
-// -> sm1_40
+// -> sm1_36
// -> otbn
-// -> sm1_41
+// -> sm1_37
// -> kmac
-// -> sm1_42
+// -> sm1_38
// -> sram_ctrl_main
module xbar_main (
@@ -137,10 +129,6 @@
input tlul_pkg::tl_d2h_t tl_edn1_i,
output tlul_pkg::tl_h2d_t tl_rv_plic_o,
input tlul_pkg::tl_d2h_t tl_rv_plic_i,
- output tlul_pkg::tl_h2d_t tl_pinmux_o,
- input tlul_pkg::tl_d2h_t tl_pinmux_i,
- output tlul_pkg::tl_h2d_t tl_padctrl_o,
- input tlul_pkg::tl_d2h_t tl_padctrl_i,
output tlul_pkg::tl_h2d_t tl_otbn_o,
input tlul_pkg::tl_d2h_t tl_otbn_i,
output tlul_pkg::tl_h2d_t tl_keymgr_o,
@@ -159,15 +147,29 @@
logic unused_scanmode;
assign unused_scanmode = scanmode_i;
- tl_h2d_t tl_s1n_22_us_h2d ;
- tl_d2h_t tl_s1n_22_us_d2h ;
+ tl_h2d_t tl_s1n_20_us_h2d ;
+ tl_d2h_t tl_s1n_20_us_d2h ;
- tl_h2d_t tl_s1n_22_ds_h2d [4];
- tl_d2h_t tl_s1n_22_ds_d2h [4];
+ tl_h2d_t tl_s1n_20_ds_h2d [4];
+ tl_d2h_t tl_s1n_20_ds_d2h [4];
// Create steering signal
- logic [2:0] dev_sel_s1n_22;
+ logic [2:0] dev_sel_s1n_20;
+
+
+ tl_h2d_t tl_sm1_21_us_h2d [3];
+ tl_d2h_t tl_sm1_21_us_d2h [3];
+
+ tl_h2d_t tl_sm1_21_ds_h2d ;
+ tl_d2h_t tl_sm1_21_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_22_us_h2d [2];
+ tl_d2h_t tl_sm1_22_us_d2h [2];
+
+ tl_h2d_t tl_sm1_22_ds_h2d ;
+ tl_d2h_t tl_sm1_22_ds_d2h ;
tl_h2d_t tl_sm1_23_us_h2d [3];
@@ -177,40 +179,40 @@
tl_d2h_t tl_sm1_23_ds_d2h ;
- tl_h2d_t tl_sm1_24_us_h2d [2];
- tl_d2h_t tl_sm1_24_us_d2h [2];
+ tl_h2d_t tl_sm1_24_us_h2d [3];
+ tl_d2h_t tl_sm1_24_us_d2h [3];
tl_h2d_t tl_sm1_24_ds_h2d ;
tl_d2h_t tl_sm1_24_ds_d2h ;
-
- tl_h2d_t tl_sm1_25_us_h2d [3];
- tl_d2h_t tl_sm1_25_us_d2h [3];
-
- tl_h2d_t tl_sm1_25_ds_h2d ;
- tl_d2h_t tl_sm1_25_ds_d2h ;
+ tl_h2d_t tl_s1n_25_us_h2d ;
+ tl_d2h_t tl_s1n_25_us_d2h ;
- tl_h2d_t tl_sm1_26_us_h2d [3];
- tl_d2h_t tl_sm1_26_us_d2h [3];
-
- tl_h2d_t tl_sm1_26_ds_h2d ;
- tl_d2h_t tl_sm1_26_ds_d2h ;
-
- tl_h2d_t tl_s1n_27_us_h2d ;
- tl_d2h_t tl_s1n_27_us_d2h ;
-
-
- tl_h2d_t tl_s1n_27_ds_h2d [19];
- tl_d2h_t tl_s1n_27_ds_d2h [19];
+ tl_h2d_t tl_s1n_25_ds_h2d [17];
+ tl_d2h_t tl_s1n_25_ds_d2h [17];
// Create steering signal
- logic [4:0] dev_sel_s1n_27;
+ logic [4:0] dev_sel_s1n_25;
- tl_h2d_t tl_asf_28_us_h2d ;
- tl_d2h_t tl_asf_28_us_d2h ;
- tl_h2d_t tl_asf_28_ds_h2d ;
- tl_d2h_t tl_asf_28_ds_d2h ;
+ tl_h2d_t tl_asf_26_us_h2d ;
+ tl_d2h_t tl_asf_26_us_d2h ;
+ tl_h2d_t tl_asf_26_ds_h2d ;
+ tl_d2h_t tl_asf_26_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_27_us_h2d [2];
+ tl_d2h_t tl_sm1_27_us_d2h [2];
+
+ tl_h2d_t tl_sm1_27_ds_h2d ;
+ tl_d2h_t tl_sm1_27_ds_d2h ;
+
+
+ tl_h2d_t tl_sm1_28_us_h2d [2];
+ tl_d2h_t tl_sm1_28_us_d2h [2];
+
+ tl_h2d_t tl_sm1_28_ds_h2d ;
+ tl_d2h_t tl_sm1_28_ds_d2h ;
tl_h2d_t tl_sm1_29_us_h2d [2];
@@ -282,374 +284,306 @@
tl_h2d_t tl_sm1_38_ds_h2d ;
tl_d2h_t tl_sm1_38_ds_d2h ;
-
- tl_h2d_t tl_sm1_39_us_h2d [2];
- tl_d2h_t tl_sm1_39_us_d2h [2];
-
- tl_h2d_t tl_sm1_39_ds_h2d ;
- tl_d2h_t tl_sm1_39_ds_d2h ;
+ tl_h2d_t tl_s1n_39_us_h2d ;
+ tl_d2h_t tl_s1n_39_us_d2h ;
- tl_h2d_t tl_sm1_40_us_h2d [2];
- tl_d2h_t tl_sm1_40_us_d2h [2];
-
- tl_h2d_t tl_sm1_40_ds_h2d ;
- tl_d2h_t tl_sm1_40_ds_d2h ;
-
-
- tl_h2d_t tl_sm1_41_us_h2d [2];
- tl_d2h_t tl_sm1_41_us_d2h [2];
-
- tl_h2d_t tl_sm1_41_ds_h2d ;
- tl_d2h_t tl_sm1_41_ds_d2h ;
-
-
- tl_h2d_t tl_sm1_42_us_h2d [2];
- tl_d2h_t tl_sm1_42_us_d2h [2];
-
- tl_h2d_t tl_sm1_42_ds_h2d ;
- tl_d2h_t tl_sm1_42_ds_d2h ;
-
- tl_h2d_t tl_s1n_43_us_h2d ;
- tl_d2h_t tl_s1n_43_us_d2h ;
-
-
- tl_h2d_t tl_s1n_43_ds_h2d [17];
- tl_d2h_t tl_s1n_43_ds_d2h [17];
+ tl_h2d_t tl_s1n_39_ds_h2d [15];
+ tl_d2h_t tl_s1n_39_ds_d2h [15];
// Create steering signal
- logic [4:0] dev_sel_s1n_43;
+ logic [3:0] dev_sel_s1n_39;
- assign tl_sm1_23_us_h2d[0] = tl_s1n_22_ds_h2d[0];
- assign tl_s1n_22_ds_d2h[0] = tl_sm1_23_us_d2h[0];
+ assign tl_sm1_21_us_h2d[0] = tl_s1n_20_ds_h2d[0];
+ assign tl_s1n_20_ds_d2h[0] = tl_sm1_21_us_d2h[0];
- assign tl_sm1_24_us_h2d[0] = tl_s1n_22_ds_h2d[1];
- assign tl_s1n_22_ds_d2h[1] = tl_sm1_24_us_d2h[0];
+ assign tl_sm1_22_us_h2d[0] = tl_s1n_20_ds_h2d[1];
+ assign tl_s1n_20_ds_d2h[1] = tl_sm1_22_us_d2h[0];
- assign tl_sm1_25_us_h2d[0] = tl_s1n_22_ds_h2d[2];
- assign tl_s1n_22_ds_d2h[2] = tl_sm1_25_us_d2h[0];
+ assign tl_sm1_23_us_h2d[0] = tl_s1n_20_ds_h2d[2];
+ assign tl_s1n_20_ds_d2h[2] = tl_sm1_23_us_d2h[0];
- assign tl_sm1_26_us_h2d[0] = tl_s1n_22_ds_h2d[3];
- assign tl_s1n_22_ds_d2h[3] = tl_sm1_26_us_d2h[0];
+ assign tl_sm1_24_us_h2d[0] = tl_s1n_20_ds_h2d[3];
+ assign tl_s1n_20_ds_d2h[3] = tl_sm1_24_us_d2h[0];
- assign tl_sm1_23_us_h2d[1] = tl_s1n_27_ds_h2d[0];
- assign tl_s1n_27_ds_d2h[0] = tl_sm1_23_us_d2h[1];
+ assign tl_sm1_21_us_h2d[1] = tl_s1n_25_ds_h2d[0];
+ assign tl_s1n_25_ds_d2h[0] = tl_sm1_21_us_d2h[1];
- assign tl_sm1_24_us_h2d[1] = tl_s1n_27_ds_h2d[1];
- assign tl_s1n_27_ds_d2h[1] = tl_sm1_24_us_d2h[1];
+ assign tl_sm1_22_us_h2d[1] = tl_s1n_25_ds_h2d[1];
+ assign tl_s1n_25_ds_d2h[1] = tl_sm1_22_us_d2h[1];
- assign tl_sm1_25_us_h2d[1] = tl_s1n_27_ds_h2d[2];
- assign tl_s1n_27_ds_d2h[2] = tl_sm1_25_us_d2h[1];
+ assign tl_sm1_23_us_h2d[1] = tl_s1n_25_ds_h2d[2];
+ assign tl_s1n_25_ds_d2h[2] = tl_sm1_23_us_d2h[1];
- assign tl_sm1_26_us_h2d[1] = tl_s1n_27_ds_h2d[3];
- assign tl_s1n_27_ds_d2h[3] = tl_sm1_26_us_d2h[1];
+ assign tl_sm1_24_us_h2d[1] = tl_s1n_25_ds_h2d[3];
+ assign tl_s1n_25_ds_d2h[3] = tl_sm1_24_us_d2h[1];
- assign tl_sm1_29_us_h2d[0] = tl_s1n_27_ds_h2d[4];
- assign tl_s1n_27_ds_d2h[4] = tl_sm1_29_us_d2h[0];
+ assign tl_sm1_27_us_h2d[0] = tl_s1n_25_ds_h2d[4];
+ assign tl_s1n_25_ds_d2h[4] = tl_sm1_27_us_d2h[0];
- assign tl_sm1_30_us_h2d[0] = tl_s1n_27_ds_h2d[5];
- assign tl_s1n_27_ds_d2h[5] = tl_sm1_30_us_d2h[0];
+ assign tl_sm1_28_us_h2d[0] = tl_s1n_25_ds_h2d[5];
+ assign tl_s1n_25_ds_d2h[5] = tl_sm1_28_us_d2h[0];
- assign tl_sm1_31_us_h2d[0] = tl_s1n_27_ds_h2d[6];
- assign tl_s1n_27_ds_d2h[6] = tl_sm1_31_us_d2h[0];
+ assign tl_sm1_29_us_h2d[0] = tl_s1n_25_ds_h2d[6];
+ assign tl_s1n_25_ds_d2h[6] = tl_sm1_29_us_d2h[0];
- assign tl_sm1_32_us_h2d[0] = tl_s1n_27_ds_h2d[7];
- assign tl_s1n_27_ds_d2h[7] = tl_sm1_32_us_d2h[0];
+ assign tl_sm1_30_us_h2d[0] = tl_s1n_25_ds_h2d[7];
+ assign tl_s1n_25_ds_d2h[7] = tl_sm1_30_us_d2h[0];
- assign tl_sm1_33_us_h2d[0] = tl_s1n_27_ds_h2d[8];
- assign tl_s1n_27_ds_d2h[8] = tl_sm1_33_us_d2h[0];
+ assign tl_sm1_31_us_h2d[0] = tl_s1n_25_ds_h2d[8];
+ assign tl_s1n_25_ds_d2h[8] = tl_sm1_31_us_d2h[0];
- assign tl_sm1_34_us_h2d[0] = tl_s1n_27_ds_h2d[9];
- assign tl_s1n_27_ds_d2h[9] = tl_sm1_34_us_d2h[0];
+ assign tl_sm1_32_us_h2d[0] = tl_s1n_25_ds_h2d[9];
+ assign tl_s1n_25_ds_d2h[9] = tl_sm1_32_us_d2h[0];
- assign tl_sm1_35_us_h2d[0] = tl_s1n_27_ds_h2d[10];
- assign tl_s1n_27_ds_d2h[10] = tl_sm1_35_us_d2h[0];
+ assign tl_sm1_33_us_h2d[0] = tl_s1n_25_ds_h2d[10];
+ assign tl_s1n_25_ds_d2h[10] = tl_sm1_33_us_d2h[0];
- assign tl_sm1_36_us_h2d[0] = tl_s1n_27_ds_h2d[11];
- assign tl_s1n_27_ds_d2h[11] = tl_sm1_36_us_d2h[0];
+ assign tl_sm1_34_us_h2d[0] = tl_s1n_25_ds_h2d[11];
+ assign tl_s1n_25_ds_d2h[11] = tl_sm1_34_us_d2h[0];
- assign tl_sm1_37_us_h2d[0] = tl_s1n_27_ds_h2d[12];
- assign tl_s1n_27_ds_d2h[12] = tl_sm1_37_us_d2h[0];
+ assign tl_sm1_35_us_h2d[0] = tl_s1n_25_ds_h2d[12];
+ assign tl_s1n_25_ds_d2h[12] = tl_sm1_35_us_d2h[0];
- assign tl_sm1_38_us_h2d[0] = tl_s1n_27_ds_h2d[13];
- assign tl_s1n_27_ds_d2h[13] = tl_sm1_38_us_d2h[0];
+ assign tl_sm1_36_us_h2d[0] = tl_s1n_25_ds_h2d[13];
+ assign tl_s1n_25_ds_d2h[13] = tl_sm1_36_us_d2h[0];
- assign tl_sm1_39_us_h2d[0] = tl_s1n_27_ds_h2d[14];
- assign tl_s1n_27_ds_d2h[14] = tl_sm1_39_us_d2h[0];
+ assign tl_keymgr_o = tl_s1n_25_ds_h2d[14];
+ assign tl_s1n_25_ds_d2h[14] = tl_keymgr_i;
- assign tl_sm1_40_us_h2d[0] = tl_s1n_27_ds_h2d[15];
- assign tl_s1n_27_ds_d2h[15] = tl_sm1_40_us_d2h[0];
+ assign tl_sm1_37_us_h2d[0] = tl_s1n_25_ds_h2d[15];
+ assign tl_s1n_25_ds_d2h[15] = tl_sm1_37_us_d2h[0];
- assign tl_keymgr_o = tl_s1n_27_ds_h2d[16];
- assign tl_s1n_27_ds_d2h[16] = tl_keymgr_i;
+ assign tl_sm1_38_us_h2d[0] = tl_s1n_25_ds_h2d[16];
+ assign tl_s1n_25_ds_d2h[16] = tl_sm1_38_us_d2h[0];
- assign tl_sm1_41_us_h2d[0] = tl_s1n_27_ds_h2d[17];
- assign tl_s1n_27_ds_d2h[17] = tl_sm1_41_us_d2h[0];
+ assign tl_sm1_21_us_h2d[2] = tl_s1n_39_ds_h2d[0];
+ assign tl_s1n_39_ds_d2h[0] = tl_sm1_21_us_d2h[2];
- assign tl_sm1_42_us_h2d[0] = tl_s1n_27_ds_h2d[18];
- assign tl_s1n_27_ds_d2h[18] = tl_sm1_42_us_d2h[0];
+ assign tl_sm1_23_us_h2d[2] = tl_s1n_39_ds_h2d[1];
+ assign tl_s1n_39_ds_d2h[1] = tl_sm1_23_us_d2h[2];
- assign tl_sm1_23_us_h2d[2] = tl_s1n_43_ds_h2d[0];
- assign tl_s1n_43_ds_d2h[0] = tl_sm1_23_us_d2h[2];
+ assign tl_sm1_24_us_h2d[2] = tl_s1n_39_ds_h2d[2];
+ assign tl_s1n_39_ds_d2h[2] = tl_sm1_24_us_d2h[2];
- assign tl_sm1_25_us_h2d[2] = tl_s1n_43_ds_h2d[1];
- assign tl_s1n_43_ds_d2h[1] = tl_sm1_25_us_d2h[2];
+ assign tl_sm1_27_us_h2d[1] = tl_s1n_39_ds_h2d[3];
+ assign tl_s1n_39_ds_d2h[3] = tl_sm1_27_us_d2h[1];
- assign tl_sm1_26_us_h2d[2] = tl_s1n_43_ds_h2d[2];
- assign tl_s1n_43_ds_d2h[2] = tl_sm1_26_us_d2h[2];
+ assign tl_sm1_28_us_h2d[1] = tl_s1n_39_ds_h2d[4];
+ assign tl_s1n_39_ds_d2h[4] = tl_sm1_28_us_d2h[1];
- assign tl_sm1_29_us_h2d[1] = tl_s1n_43_ds_h2d[3];
- assign tl_s1n_43_ds_d2h[3] = tl_sm1_29_us_d2h[1];
+ assign tl_sm1_29_us_h2d[1] = tl_s1n_39_ds_h2d[5];
+ assign tl_s1n_39_ds_d2h[5] = tl_sm1_29_us_d2h[1];
- assign tl_sm1_30_us_h2d[1] = tl_s1n_43_ds_h2d[4];
- assign tl_s1n_43_ds_d2h[4] = tl_sm1_30_us_d2h[1];
+ assign tl_sm1_30_us_h2d[1] = tl_s1n_39_ds_h2d[6];
+ assign tl_s1n_39_ds_d2h[6] = tl_sm1_30_us_d2h[1];
- assign tl_sm1_31_us_h2d[1] = tl_s1n_43_ds_h2d[5];
- assign tl_s1n_43_ds_d2h[5] = tl_sm1_31_us_d2h[1];
+ assign tl_sm1_31_us_h2d[1] = tl_s1n_39_ds_h2d[7];
+ assign tl_s1n_39_ds_d2h[7] = tl_sm1_31_us_d2h[1];
- assign tl_sm1_32_us_h2d[1] = tl_s1n_43_ds_h2d[6];
- assign tl_s1n_43_ds_d2h[6] = tl_sm1_32_us_d2h[1];
+ assign tl_sm1_32_us_h2d[1] = tl_s1n_39_ds_h2d[8];
+ assign tl_s1n_39_ds_d2h[8] = tl_sm1_32_us_d2h[1];
- assign tl_sm1_33_us_h2d[1] = tl_s1n_43_ds_h2d[7];
- assign tl_s1n_43_ds_d2h[7] = tl_sm1_33_us_d2h[1];
+ assign tl_sm1_33_us_h2d[1] = tl_s1n_39_ds_h2d[9];
+ assign tl_s1n_39_ds_d2h[9] = tl_sm1_33_us_d2h[1];
- assign tl_sm1_34_us_h2d[1] = tl_s1n_43_ds_h2d[8];
- assign tl_s1n_43_ds_d2h[8] = tl_sm1_34_us_d2h[1];
+ assign tl_sm1_34_us_h2d[1] = tl_s1n_39_ds_h2d[10];
+ assign tl_s1n_39_ds_d2h[10] = tl_sm1_34_us_d2h[1];
- assign tl_sm1_35_us_h2d[1] = tl_s1n_43_ds_h2d[9];
- assign tl_s1n_43_ds_d2h[9] = tl_sm1_35_us_d2h[1];
+ assign tl_sm1_35_us_h2d[1] = tl_s1n_39_ds_h2d[11];
+ assign tl_s1n_39_ds_d2h[11] = tl_sm1_35_us_d2h[1];
- assign tl_sm1_36_us_h2d[1] = tl_s1n_43_ds_h2d[10];
- assign tl_s1n_43_ds_d2h[10] = tl_sm1_36_us_d2h[1];
+ assign tl_sm1_36_us_h2d[1] = tl_s1n_39_ds_h2d[12];
+ assign tl_s1n_39_ds_d2h[12] = tl_sm1_36_us_d2h[1];
- assign tl_sm1_37_us_h2d[1] = tl_s1n_43_ds_h2d[11];
- assign tl_s1n_43_ds_d2h[11] = tl_sm1_37_us_d2h[1];
+ assign tl_sm1_37_us_h2d[1] = tl_s1n_39_ds_h2d[13];
+ assign tl_s1n_39_ds_d2h[13] = tl_sm1_37_us_d2h[1];
- assign tl_sm1_38_us_h2d[1] = tl_s1n_43_ds_h2d[12];
- assign tl_s1n_43_ds_d2h[12] = tl_sm1_38_us_d2h[1];
+ assign tl_sm1_38_us_h2d[1] = tl_s1n_39_ds_h2d[14];
+ assign tl_s1n_39_ds_d2h[14] = tl_sm1_38_us_d2h[1];
- assign tl_sm1_39_us_h2d[1] = tl_s1n_43_ds_h2d[13];
- assign tl_s1n_43_ds_d2h[13] = tl_sm1_39_us_d2h[1];
+ assign tl_s1n_20_us_h2d = tl_corei_i;
+ assign tl_corei_o = tl_s1n_20_us_d2h;
- assign tl_sm1_40_us_h2d[1] = tl_s1n_43_ds_h2d[14];
- assign tl_s1n_43_ds_d2h[14] = tl_sm1_40_us_d2h[1];
+ assign tl_rom_o = tl_sm1_21_ds_h2d;
+ assign tl_sm1_21_ds_d2h = tl_rom_i;
- assign tl_sm1_41_us_h2d[1] = tl_s1n_43_ds_h2d[15];
- assign tl_s1n_43_ds_d2h[15] = tl_sm1_41_us_d2h[1];
+ assign tl_debug_mem_o = tl_sm1_22_ds_h2d;
+ assign tl_sm1_22_ds_d2h = tl_debug_mem_i;
- assign tl_sm1_42_us_h2d[1] = tl_s1n_43_ds_h2d[16];
- assign tl_s1n_43_ds_d2h[16] = tl_sm1_42_us_d2h[1];
+ assign tl_ram_main_o = tl_sm1_23_ds_h2d;
+ assign tl_sm1_23_ds_d2h = tl_ram_main_i;
- assign tl_s1n_22_us_h2d = tl_corei_i;
- assign tl_corei_o = tl_s1n_22_us_d2h;
+ assign tl_eflash_o = tl_sm1_24_ds_h2d;
+ assign tl_sm1_24_ds_d2h = tl_eflash_i;
- assign tl_rom_o = tl_sm1_23_ds_h2d;
- assign tl_sm1_23_ds_d2h = tl_rom_i;
+ assign tl_s1n_25_us_h2d = tl_cored_i;
+ assign tl_cored_o = tl_s1n_25_us_d2h;
- assign tl_debug_mem_o = tl_sm1_24_ds_h2d;
- assign tl_sm1_24_ds_d2h = tl_debug_mem_i;
+ assign tl_peri_o = tl_asf_26_ds_h2d;
+ assign tl_asf_26_ds_d2h = tl_peri_i;
- assign tl_ram_main_o = tl_sm1_25_ds_h2d;
- assign tl_sm1_25_ds_d2h = tl_ram_main_i;
+ assign tl_asf_26_us_h2d = tl_sm1_27_ds_h2d;
+ assign tl_sm1_27_ds_d2h = tl_asf_26_us_d2h;
- assign tl_eflash_o = tl_sm1_26_ds_h2d;
- assign tl_sm1_26_ds_d2h = tl_eflash_i;
+ assign tl_flash_ctrl_o = tl_sm1_28_ds_h2d;
+ assign tl_sm1_28_ds_d2h = tl_flash_ctrl_i;
- assign tl_s1n_27_us_h2d = tl_cored_i;
- assign tl_cored_o = tl_s1n_27_us_d2h;
+ assign tl_aes_o = tl_sm1_29_ds_h2d;
+ assign tl_sm1_29_ds_d2h = tl_aes_i;
- assign tl_peri_o = tl_asf_28_ds_h2d;
- assign tl_asf_28_ds_d2h = tl_peri_i;
+ assign tl_entropy_src_o = tl_sm1_30_ds_h2d;
+ assign tl_sm1_30_ds_d2h = tl_entropy_src_i;
- assign tl_asf_28_us_h2d = tl_sm1_29_ds_h2d;
- assign tl_sm1_29_ds_d2h = tl_asf_28_us_d2h;
+ assign tl_csrng_o = tl_sm1_31_ds_h2d;
+ assign tl_sm1_31_ds_d2h = tl_csrng_i;
- assign tl_flash_ctrl_o = tl_sm1_30_ds_h2d;
- assign tl_sm1_30_ds_d2h = tl_flash_ctrl_i;
+ assign tl_edn0_o = tl_sm1_32_ds_h2d;
+ assign tl_sm1_32_ds_d2h = tl_edn0_i;
- assign tl_aes_o = tl_sm1_31_ds_h2d;
- assign tl_sm1_31_ds_d2h = tl_aes_i;
+ assign tl_edn1_o = tl_sm1_33_ds_h2d;
+ assign tl_sm1_33_ds_d2h = tl_edn1_i;
- assign tl_entropy_src_o = tl_sm1_32_ds_h2d;
- assign tl_sm1_32_ds_d2h = tl_entropy_src_i;
+ assign tl_hmac_o = tl_sm1_34_ds_h2d;
+ assign tl_sm1_34_ds_d2h = tl_hmac_i;
- assign tl_csrng_o = tl_sm1_33_ds_h2d;
- assign tl_sm1_33_ds_d2h = tl_csrng_i;
+ assign tl_rv_plic_o = tl_sm1_35_ds_h2d;
+ assign tl_sm1_35_ds_d2h = tl_rv_plic_i;
- assign tl_edn0_o = tl_sm1_34_ds_h2d;
- assign tl_sm1_34_ds_d2h = tl_edn0_i;
+ assign tl_otbn_o = tl_sm1_36_ds_h2d;
+ assign tl_sm1_36_ds_d2h = tl_otbn_i;
- assign tl_edn1_o = tl_sm1_35_ds_h2d;
- assign tl_sm1_35_ds_d2h = tl_edn1_i;
+ assign tl_kmac_o = tl_sm1_37_ds_h2d;
+ assign tl_sm1_37_ds_d2h = tl_kmac_i;
- assign tl_hmac_o = tl_sm1_36_ds_h2d;
- assign tl_sm1_36_ds_d2h = tl_hmac_i;
+ assign tl_sram_ctrl_main_o = tl_sm1_38_ds_h2d;
+ assign tl_sm1_38_ds_d2h = tl_sram_ctrl_main_i;
- assign tl_rv_plic_o = tl_sm1_37_ds_h2d;
- assign tl_sm1_37_ds_d2h = tl_rv_plic_i;
-
- assign tl_pinmux_o = tl_sm1_38_ds_h2d;
- assign tl_sm1_38_ds_d2h = tl_pinmux_i;
-
- assign tl_padctrl_o = tl_sm1_39_ds_h2d;
- assign tl_sm1_39_ds_d2h = tl_padctrl_i;
-
- assign tl_otbn_o = tl_sm1_40_ds_h2d;
- assign tl_sm1_40_ds_d2h = tl_otbn_i;
-
- assign tl_kmac_o = tl_sm1_41_ds_h2d;
- assign tl_sm1_41_ds_d2h = tl_kmac_i;
-
- assign tl_sram_ctrl_main_o = tl_sm1_42_ds_h2d;
- assign tl_sm1_42_ds_d2h = tl_sram_ctrl_main_i;
-
- assign tl_s1n_43_us_h2d = tl_dm_sba_i;
- assign tl_dm_sba_o = tl_s1n_43_us_d2h;
+ assign tl_s1n_39_us_h2d = tl_dm_sba_i;
+ assign tl_dm_sba_o = tl_s1n_39_us_d2h;
always_comb begin
// default steering to generate error response if address is not within the range
- dev_sel_s1n_22 = 3'd4;
- if ((tl_s1n_22_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
- dev_sel_s1n_22 = 3'd0;
+ dev_sel_s1n_20 = 3'd4;
+ if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
+ dev_sel_s1n_20 = 3'd0;
- end else if ((tl_s1n_22_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin
- dev_sel_s1n_22 = 3'd1;
+ end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin
+ dev_sel_s1n_20 = 3'd1;
- end else if ((tl_s1n_22_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
- dev_sel_s1n_22 = 3'd2;
+ end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
+ dev_sel_s1n_20 = 3'd2;
- end else if ((tl_s1n_22_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
- dev_sel_s1n_22 = 3'd3;
+ end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
+ dev_sel_s1n_20 = 3'd3;
end
end
always_comb begin
// default steering to generate error response if address is not within the range
- dev_sel_s1n_27 = 5'd19;
- if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
- dev_sel_s1n_27 = 5'd0;
+ dev_sel_s1n_25 = 5'd17;
+ if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
+ dev_sel_s1n_25 = 5'd0;
- end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin
- dev_sel_s1n_27 = 5'd1;
+ end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin
+ dev_sel_s1n_25 = 5'd1;
- end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
- dev_sel_s1n_27 = 5'd2;
+ end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
+ dev_sel_s1n_25 = 5'd2;
- end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
- dev_sel_s1n_27 = 5'd3;
+ end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
+ dev_sel_s1n_25 = 5'd3;
- end else if (
- ((tl_s1n_27_us_h2d.a_address <= (ADDR_MASK_PERI[0] + ADDR_SPACE_PERI[0])) &&
- (tl_s1n_27_us_h2d.a_address >= ADDR_SPACE_PERI[0])) ||
- ((tl_s1n_27_us_h2d.a_address <= (ADDR_MASK_PERI[1] + ADDR_SPACE_PERI[1])) &&
- (tl_s1n_27_us_h2d.a_address >= ADDR_SPACE_PERI[1]))
- ) begin
- dev_sel_s1n_27 = 5'd4;
+ end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_PERI)) == ADDR_SPACE_PERI) begin
+ dev_sel_s1n_25 = 5'd4;
- end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin
- dev_sel_s1n_27 = 5'd5;
+ end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin
+ dev_sel_s1n_25 = 5'd5;
- end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
- dev_sel_s1n_27 = 5'd6;
+ end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
+ dev_sel_s1n_25 = 5'd6;
- end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_ENTROPY_SRC)) == ADDR_SPACE_ENTROPY_SRC) begin
- dev_sel_s1n_27 = 5'd7;
+ end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_ENTROPY_SRC)) == ADDR_SPACE_ENTROPY_SRC) begin
+ dev_sel_s1n_25 = 5'd7;
- end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_CSRNG)) == ADDR_SPACE_CSRNG) begin
- dev_sel_s1n_27 = 5'd8;
+ end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_CSRNG)) == ADDR_SPACE_CSRNG) begin
+ dev_sel_s1n_25 = 5'd8;
- end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_EDN0)) == ADDR_SPACE_EDN0) begin
- dev_sel_s1n_27 = 5'd9;
+ end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_EDN0)) == ADDR_SPACE_EDN0) begin
+ dev_sel_s1n_25 = 5'd9;
- end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_EDN1)) == ADDR_SPACE_EDN1) begin
- dev_sel_s1n_27 = 5'd10;
+ end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_EDN1)) == ADDR_SPACE_EDN1) begin
+ dev_sel_s1n_25 = 5'd10;
- end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
- dev_sel_s1n_27 = 5'd11;
+ end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
+ dev_sel_s1n_25 = 5'd11;
- end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
- dev_sel_s1n_27 = 5'd12;
+ end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
+ dev_sel_s1n_25 = 5'd12;
- end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin
- dev_sel_s1n_27 = 5'd13;
+ end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin
+ dev_sel_s1n_25 = 5'd13;
- end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_PADCTRL)) == ADDR_SPACE_PADCTRL) begin
- dev_sel_s1n_27 = 5'd14;
+ end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_KEYMGR)) == ADDR_SPACE_KEYMGR) begin
+ dev_sel_s1n_25 = 5'd14;
- end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin
- dev_sel_s1n_27 = 5'd15;
+ end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin
+ dev_sel_s1n_25 = 5'd15;
- end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_KEYMGR)) == ADDR_SPACE_KEYMGR) begin
- dev_sel_s1n_27 = 5'd16;
-
- end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin
- dev_sel_s1n_27 = 5'd17;
-
- end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_MAIN)) == ADDR_SPACE_SRAM_CTRL_MAIN) begin
- dev_sel_s1n_27 = 5'd18;
+ end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_MAIN)) == ADDR_SPACE_SRAM_CTRL_MAIN) begin
+ dev_sel_s1n_25 = 5'd16;
end
end
always_comb begin
// default steering to generate error response if address is not within the range
- dev_sel_s1n_43 = 5'd17;
- if ((tl_s1n_43_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
- dev_sel_s1n_43 = 5'd0;
+ dev_sel_s1n_39 = 4'd15;
+ if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
+ dev_sel_s1n_39 = 4'd0;
- end else if ((tl_s1n_43_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
- dev_sel_s1n_43 = 5'd1;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
+ dev_sel_s1n_39 = 4'd1;
- end else if ((tl_s1n_43_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
- dev_sel_s1n_43 = 5'd2;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
+ dev_sel_s1n_39 = 4'd2;
- end else if (
- ((tl_s1n_43_us_h2d.a_address <= (ADDR_MASK_PERI[0] + ADDR_SPACE_PERI[0])) &&
- (tl_s1n_43_us_h2d.a_address >= ADDR_SPACE_PERI[0])) ||
- ((tl_s1n_43_us_h2d.a_address <= (ADDR_MASK_PERI[1] + ADDR_SPACE_PERI[1])) &&
- (tl_s1n_43_us_h2d.a_address >= ADDR_SPACE_PERI[1]))
- ) begin
- dev_sel_s1n_43 = 5'd3;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_PERI)) == ADDR_SPACE_PERI) begin
+ dev_sel_s1n_39 = 4'd3;
- end else if ((tl_s1n_43_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin
- dev_sel_s1n_43 = 5'd4;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin
+ dev_sel_s1n_39 = 4'd4;
- end else if ((tl_s1n_43_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
- dev_sel_s1n_43 = 5'd5;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
+ dev_sel_s1n_39 = 4'd5;
- end else if ((tl_s1n_43_us_h2d.a_address & ~(ADDR_MASK_ENTROPY_SRC)) == ADDR_SPACE_ENTROPY_SRC) begin
- dev_sel_s1n_43 = 5'd6;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_ENTROPY_SRC)) == ADDR_SPACE_ENTROPY_SRC) begin
+ dev_sel_s1n_39 = 4'd6;
- end else if ((tl_s1n_43_us_h2d.a_address & ~(ADDR_MASK_CSRNG)) == ADDR_SPACE_CSRNG) begin
- dev_sel_s1n_43 = 5'd7;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_CSRNG)) == ADDR_SPACE_CSRNG) begin
+ dev_sel_s1n_39 = 4'd7;
- end else if ((tl_s1n_43_us_h2d.a_address & ~(ADDR_MASK_EDN0)) == ADDR_SPACE_EDN0) begin
- dev_sel_s1n_43 = 5'd8;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_EDN0)) == ADDR_SPACE_EDN0) begin
+ dev_sel_s1n_39 = 4'd8;
- end else if ((tl_s1n_43_us_h2d.a_address & ~(ADDR_MASK_EDN1)) == ADDR_SPACE_EDN1) begin
- dev_sel_s1n_43 = 5'd9;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_EDN1)) == ADDR_SPACE_EDN1) begin
+ dev_sel_s1n_39 = 4'd9;
- end else if ((tl_s1n_43_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
- dev_sel_s1n_43 = 5'd10;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
+ dev_sel_s1n_39 = 4'd10;
- end else if ((tl_s1n_43_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
- dev_sel_s1n_43 = 5'd11;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
+ dev_sel_s1n_39 = 4'd11;
- end else if ((tl_s1n_43_us_h2d.a_address & ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin
- dev_sel_s1n_43 = 5'd12;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin
+ dev_sel_s1n_39 = 4'd12;
- end else if ((tl_s1n_43_us_h2d.a_address & ~(ADDR_MASK_PADCTRL)) == ADDR_SPACE_PADCTRL) begin
- dev_sel_s1n_43 = 5'd13;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin
+ dev_sel_s1n_39 = 4'd13;
- end else if ((tl_s1n_43_us_h2d.a_address & ~(ADDR_MASK_OTBN)) == ADDR_SPACE_OTBN) begin
- dev_sel_s1n_43 = 5'd14;
-
- end else if ((tl_s1n_43_us_h2d.a_address & ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin
- dev_sel_s1n_43 = 5'd15;
-
- end else if ((tl_s1n_43_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_MAIN)) == ADDR_SPACE_SRAM_CTRL_MAIN) begin
- dev_sel_s1n_43 = 5'd16;
+ end else if ((tl_s1n_39_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_MAIN)) == ADDR_SPACE_SRAM_CTRL_MAIN) begin
+ dev_sel_s1n_39 = 4'd14;
end
end
@@ -661,14 +595,42 @@
.DReqDepth (16'h0),
.DRspDepth (16'h0),
.N (4)
- ) u_s1n_22 (
+ ) u_s1n_20 (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
- .tl_h_i (tl_s1n_22_us_h2d),
- .tl_h_o (tl_s1n_22_us_d2h),
- .tl_d_o (tl_s1n_22_ds_h2d),
- .tl_d_i (tl_s1n_22_ds_d2h),
- .dev_select_i (dev_sel_s1n_22)
+ .tl_h_i (tl_s1n_20_us_h2d),
+ .tl_h_o (tl_s1n_20_us_d2h),
+ .tl_d_o (tl_s1n_20_ds_h2d),
+ .tl_d_i (tl_s1n_20_ds_d2h),
+ .dev_select_i (dev_sel_s1n_20)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (12'h0),
+ .HRspDepth (12'h0),
+ .DReqDepth (4'h0),
+ .DRspDepth (4'h0),
+ .M (3)
+ ) u_sm1_21 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_21_us_h2d),
+ .tl_h_o (tl_sm1_21_us_d2h),
+ .tl_d_o (tl_sm1_21_ds_h2d),
+ .tl_d_i (tl_sm1_21_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_22 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_22_us_h2d),
+ .tl_h_o (tl_sm1_22_us_d2h),
+ .tl_d_o (tl_sm1_22_ds_h2d),
+ .tl_d_i (tl_sm1_22_ds_d2h)
);
tlul_socket_m1 #(
.HReqDepth (12'h0),
@@ -685,11 +647,11 @@
.tl_d_i (tl_sm1_23_ds_d2h)
);
tlul_socket_m1 #(
- .HReqDepth (8'h0),
- .HRspDepth (8'h0),
- .DReqPass (1'b0),
- .DRspPass (1'b0),
- .M (2)
+ .HReqDepth (12'h0),
+ .HRspDepth (12'h0),
+ .DReqDepth (4'h0),
+ .DRspDepth (4'h0),
+ .M (3)
) u_sm1_24 (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
@@ -698,63 +660,35 @@
.tl_d_o (tl_sm1_24_ds_h2d),
.tl_d_i (tl_sm1_24_ds_d2h)
);
- tlul_socket_m1 #(
- .HReqDepth (12'h0),
- .HRspDepth (12'h0),
- .DReqDepth (4'h0),
- .DRspDepth (4'h0),
- .M (3)
- ) u_sm1_25 (
- .clk_i (clk_main_i),
- .rst_ni (rst_main_ni),
- .tl_h_i (tl_sm1_25_us_h2d),
- .tl_h_o (tl_sm1_25_us_d2h),
- .tl_d_o (tl_sm1_25_ds_h2d),
- .tl_d_i (tl_sm1_25_ds_d2h)
- );
- tlul_socket_m1 #(
- .HReqDepth (12'h0),
- .HRspDepth (12'h0),
- .DReqDepth (4'h0),
- .DRspDepth (4'h0),
- .M (3)
- ) u_sm1_26 (
- .clk_i (clk_main_i),
- .rst_ni (rst_main_ni),
- .tl_h_i (tl_sm1_26_us_h2d),
- .tl_h_o (tl_sm1_26_us_d2h),
- .tl_d_o (tl_sm1_26_ds_h2d),
- .tl_d_i (tl_sm1_26_ds_d2h)
- );
tlul_socket_1n #(
.HReqDepth (4'h0),
.HRspDepth (4'h0),
- .DReqPass (19'h6ffff),
- .DRspPass (19'h6ffff),
- .DReqDepth (76'h20000000000000000),
- .DRspDepth (76'h20000000000000000),
- .N (19)
- ) u_s1n_27 (
+ .DReqPass (17'h1bfff),
+ .DRspPass (17'h1bfff),
+ .DReqDepth (68'h200000000000000),
+ .DRspDepth (68'h200000000000000),
+ .N (17)
+ ) u_s1n_25 (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
- .tl_h_i (tl_s1n_27_us_h2d),
- .tl_h_o (tl_s1n_27_us_d2h),
- .tl_d_o (tl_s1n_27_ds_h2d),
- .tl_d_i (tl_s1n_27_ds_d2h),
- .dev_select_i (dev_sel_s1n_27)
+ .tl_h_i (tl_s1n_25_us_h2d),
+ .tl_h_o (tl_s1n_25_us_d2h),
+ .tl_d_o (tl_s1n_25_ds_h2d),
+ .tl_d_i (tl_s1n_25_ds_d2h),
+ .dev_select_i (dev_sel_s1n_25)
);
tlul_fifo_async #(
.ReqDepth (4),// At least 4 to make async work
.RspDepth (4) // At least 4 to make async work
- ) u_asf_28 (
+ ) u_asf_26 (
.clk_h_i (clk_main_i),
.rst_h_ni (rst_main_ni),
.clk_d_i (clk_fixed_i),
.rst_d_ni (rst_fixed_ni),
- .tl_h_i (tl_asf_28_us_h2d),
- .tl_h_o (tl_asf_28_us_d2h),
- .tl_d_o (tl_asf_28_ds_h2d),
- .tl_d_i (tl_asf_28_ds_d2h)
+ .tl_h_i (tl_asf_26_us_h2d),
+ .tl_h_o (tl_asf_26_us_d2h),
+ .tl_d_o (tl_asf_26_ds_h2d),
+ .tl_d_i (tl_asf_26_ds_d2h)
);
tlul_socket_m1 #(
.HReqDepth (8'h0),
@@ -762,6 +696,34 @@
.DReqDepth (4'h0),
.DRspDepth (4'h0),
.M (2)
+ ) u_sm1_27 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_27_us_h2d),
+ .tl_h_o (tl_sm1_27_us_d2h),
+ .tl_d_o (tl_sm1_27_ds_h2d),
+ .tl_d_i (tl_sm1_27_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
+ ) u_sm1_28 (
+ .clk_i (clk_main_i),
+ .rst_ni (rst_main_ni),
+ .tl_h_i (tl_sm1_28_us_h2d),
+ .tl_h_o (tl_sm1_28_us_d2h),
+ .tl_d_o (tl_sm1_28_ds_h2d),
+ .tl_d_i (tl_sm1_28_ds_d2h)
+ );
+ tlul_socket_m1 #(
+ .HReqDepth (8'h0),
+ .HRspDepth (8'h0),
+ .DReqPass (1'b0),
+ .DRspPass (1'b0),
+ .M (2)
) u_sm1_29 (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
@@ -885,8 +847,8 @@
tlul_socket_m1 #(
.HReqDepth (8'h0),
.HRspDepth (8'h0),
- .DReqPass (1'b0),
- .DRspPass (1'b0),
+ .DReqDepth (4'h0),
+ .DRspDepth (4'h0),
.M (2)
) u_sm1_38 (
.clk_i (clk_main_i),
@@ -896,76 +858,20 @@
.tl_d_o (tl_sm1_38_ds_h2d),
.tl_d_i (tl_sm1_38_ds_d2h)
);
- tlul_socket_m1 #(
- .HReqDepth (8'h0),
- .HRspDepth (8'h0),
- .DReqPass (1'b0),
- .DRspPass (1'b0),
- .M (2)
- ) u_sm1_39 (
- .clk_i (clk_main_i),
- .rst_ni (rst_main_ni),
- .tl_h_i (tl_sm1_39_us_h2d),
- .tl_h_o (tl_sm1_39_us_d2h),
- .tl_d_o (tl_sm1_39_ds_h2d),
- .tl_d_i (tl_sm1_39_ds_d2h)
- );
- tlul_socket_m1 #(
- .HReqDepth (8'h0),
- .HRspDepth (8'h0),
- .DReqPass (1'b0),
- .DRspPass (1'b0),
- .M (2)
- ) u_sm1_40 (
- .clk_i (clk_main_i),
- .rst_ni (rst_main_ni),
- .tl_h_i (tl_sm1_40_us_h2d),
- .tl_h_o (tl_sm1_40_us_d2h),
- .tl_d_o (tl_sm1_40_ds_h2d),
- .tl_d_i (tl_sm1_40_ds_d2h)
- );
- tlul_socket_m1 #(
- .HReqDepth (8'h0),
- .HRspDepth (8'h0),
- .DReqPass (1'b0),
- .DRspPass (1'b0),
- .M (2)
- ) u_sm1_41 (
- .clk_i (clk_main_i),
- .rst_ni (rst_main_ni),
- .tl_h_i (tl_sm1_41_us_h2d),
- .tl_h_o (tl_sm1_41_us_d2h),
- .tl_d_o (tl_sm1_41_ds_h2d),
- .tl_d_i (tl_sm1_41_ds_d2h)
- );
- tlul_socket_m1 #(
- .HReqDepth (8'h0),
- .HRspDepth (8'h0),
- .DReqDepth (4'h0),
- .DRspDepth (4'h0),
- .M (2)
- ) u_sm1_42 (
- .clk_i (clk_main_i),
- .rst_ni (rst_main_ni),
- .tl_h_i (tl_sm1_42_us_h2d),
- .tl_h_o (tl_sm1_42_us_d2h),
- .tl_d_o (tl_sm1_42_ds_h2d),
- .tl_d_i (tl_sm1_42_ds_d2h)
- );
tlul_socket_1n #(
.HReqPass (1'b0),
.HRspPass (1'b0),
- .DReqDepth (68'h0),
- .DRspDepth (68'h0),
- .N (17)
- ) u_s1n_43 (
+ .DReqDepth (60'h0),
+ .DRspDepth (60'h0),
+ .N (15)
+ ) u_s1n_39 (
.clk_i (clk_main_i),
.rst_ni (rst_main_ni),
- .tl_h_i (tl_s1n_43_us_h2d),
- .tl_h_o (tl_s1n_43_us_d2h),
- .tl_d_o (tl_s1n_43_ds_h2d),
- .tl_d_i (tl_s1n_43_ds_d2h),
- .dev_select_i (dev_sel_s1n_43)
+ .tl_h_i (tl_s1n_39_us_h2d),
+ .tl_h_o (tl_s1n_39_us_d2h),
+ .tl_d_o (tl_s1n_39_ds_h2d),
+ .tl_d_i (tl_s1n_39_ds_d2h),
+ .dev_select_i (dev_sel_s1n_39)
);
endmodule
diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
index ec2845d..38d9cb3 100644
--- a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
+++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
@@ -16,11 +16,11 @@
reset: rst_peri_ni
reset_connections:
{
- rst_peri_ni: rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
+ rst_peri_ni: rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]
}
clock_connections:
{
- clk_peri_i: clkmgr_clocks.clk_io_div4_infra
+ clk_peri_i: clkmgr_aon_clocks.clk_io_div4_infra
}
domain: "0"
connections:
@@ -39,17 +39,19 @@
spi_device
rv_timer
usbdev
- pwrmgr
- rstmgr
- clkmgr
- ram_ret
+ pwrmgr_aon
+ rstmgr_aon
+ clkmgr_aon
+ pinmux_aon
+ padctrl_aon
+ ram_ret_aon
otp_ctrl
lc_ctrl
- sensor_ctrl
+ sensor_ctrl_aon
alert_handler
nmi_gen
ast_wrapper
- sram_ctrl_ret
+ sram_ctrl_ret_aon
]
}
nodes:
@@ -273,7 +275,7 @@
addr_range:
[
{
- base_addr: 0x40500000
+ base_addr: 0x40110000
size_byte: 0x1000
}
]
@@ -282,7 +284,7 @@
pipeline_byp: "true"
}
{
- name: pwrmgr
+ name: pwrmgr_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
@@ -300,7 +302,7 @@
pipeline_byp: "true"
}
{
- name: rstmgr
+ name: rstmgr_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
@@ -318,7 +320,7 @@
pipeline_byp: "true"
}
{
- name: clkmgr
+ name: clkmgr_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
@@ -336,7 +338,43 @@
pipeline_byp: "true"
}
{
- name: ram_ret
+ name: pinmux_aon
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: "false"
+ inst_type: pinmux
+ addr_range:
+ [
+ {
+ base_addr: 0x40460000
+ size_byte: 0x1000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline_byp: "true"
+ }
+ {
+ name: padctrl_aon
+ type: device
+ clock: clk_peri_i
+ reset: rst_peri_ni
+ pipeline: "false"
+ inst_type: padctrl
+ addr_range:
+ [
+ {
+ base_addr: 0x40470000
+ size_byte: 0x1000
+ }
+ ]
+ xbar: false
+ stub: false
+ pipeline_byp: "true"
+ }
+ {
+ name: ram_ret_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
@@ -390,7 +428,7 @@
pipeline_byp: "true"
}
{
- name: sensor_ctrl
+ name: sensor_ctrl_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
@@ -399,7 +437,7 @@
addr_range:
[
{
- base_addr: 0x40110000
+ base_addr: 0x40500000
size_byte: 0x1000
}
]
@@ -426,7 +464,7 @@
pipeline_byp: "true"
}
{
- name: sram_ctrl_ret
+ name: sram_ctrl_ret_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
@@ -471,7 +509,7 @@
addr_range:
[
{
- base_addr: 0x40180000
+ base_addr: 0x40490000
size_byte: 0x1000
}
]
diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson
index 55a3129..56369d3 100644
--- a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson
+++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson
@@ -93,25 +93,37 @@
}
{ struct: "tl"
type: "req_rsp"
- name: "tl_pwrmgr"
+ name: "tl_pwrmgr_aon"
act: "req"
package: "tlul_pkg"
}
{ struct: "tl"
type: "req_rsp"
- name: "tl_rstmgr"
+ name: "tl_rstmgr_aon"
act: "req"
package: "tlul_pkg"
}
{ struct: "tl"
type: "req_rsp"
- name: "tl_clkmgr"
+ name: "tl_clkmgr_aon"
act: "req"
package: "tlul_pkg"
}
{ struct: "tl"
type: "req_rsp"
- name: "tl_ram_ret"
+ name: "tl_pinmux_aon"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_padctrl_aon"
+ act: "req"
+ package: "tlul_pkg"
+ }
+ { struct: "tl"
+ type: "req_rsp"
+ name: "tl_ram_ret_aon"
act: "req"
package: "tlul_pkg"
}
@@ -129,7 +141,7 @@
}
{ struct: "tl"
type: "req_rsp"
- name: "tl_sensor_ctrl"
+ name: "tl_sensor_ctrl_aon"
act: "req"
package: "tlul_pkg"
}
@@ -141,7 +153,7 @@
}
{ struct: "tl"
type: "req_rsp"
- name: "tl_sram_ctrl_ret"
+ name: "tl_sram_ctrl_ret_aon"
act: "req"
package: "tlul_pkg"
}
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv
index db1fe10..90bf821 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv
@@ -29,14 +29,16 @@
`CONNECT_TL_DEVICE_IF(spi_device, dut, clk_peri_i, rst_n)
`CONNECT_TL_DEVICE_IF(rv_timer, dut, clk_peri_i, rst_n)
`CONNECT_TL_DEVICE_IF(usbdev, dut, clk_peri_i, rst_n)
-`CONNECT_TL_DEVICE_IF(pwrmgr, dut, clk_peri_i, rst_n)
-`CONNECT_TL_DEVICE_IF(rstmgr, dut, clk_peri_i, rst_n)
-`CONNECT_TL_DEVICE_IF(clkmgr, dut, clk_peri_i, rst_n)
-`CONNECT_TL_DEVICE_IF(ram_ret, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(pwrmgr_aon, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(rstmgr_aon, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(clkmgr_aon, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(pinmux_aon, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(padctrl_aon, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(ram_ret_aon, dut, clk_peri_i, rst_n)
`CONNECT_TL_DEVICE_IF(otp_ctrl, dut, clk_peri_i, rst_n)
`CONNECT_TL_DEVICE_IF(lc_ctrl, dut, clk_peri_i, rst_n)
-`CONNECT_TL_DEVICE_IF(sensor_ctrl, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(sensor_ctrl_aon, dut, clk_peri_i, rst_n)
`CONNECT_TL_DEVICE_IF(alert_handler, dut, clk_peri_i, rst_n)
-`CONNECT_TL_DEVICE_IF(sram_ctrl_ret, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(sram_ctrl_ret_aon, dut, clk_peri_i, rst_n)
`CONNECT_TL_DEVICE_IF(nmi_gen, dut, clk_peri_i, rst_n)
`CONNECT_TL_DEVICE_IF(ast_wrapper, dut, clk_peri_i, rst_n)
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg
index a8657e2..c139457 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg
@@ -51,26 +51,34 @@
-node tb.dut tl_rv_timer_o.a_address[19:12]
-node tb.dut tl_rv_timer_o.a_address[29:21]
-node tb.dut tl_rv_timer_o.a_address[31:31]
--node tb.dut tl_usbdev_o.a_address[19:12]
--node tb.dut tl_usbdev_o.a_address[21:21]
--node tb.dut tl_usbdev_o.a_address[29:23]
+-node tb.dut tl_usbdev_o.a_address[15:12]
+-node tb.dut tl_usbdev_o.a_address[19:17]
+-node tb.dut tl_usbdev_o.a_address[29:21]
-node tb.dut tl_usbdev_o.a_address[31:31]
--node tb.dut tl_pwrmgr_o.a_address[21:12]
--node tb.dut tl_pwrmgr_o.a_address[29:23]
--node tb.dut tl_pwrmgr_o.a_address[31:31]
--node tb.dut tl_rstmgr_o.a_address[15:12]
--node tb.dut tl_rstmgr_o.a_address[21:17]
--node tb.dut tl_rstmgr_o.a_address[29:23]
--node tb.dut tl_rstmgr_o.a_address[31:31]
--node tb.dut tl_clkmgr_o.a_address[16:12]
--node tb.dut tl_clkmgr_o.a_address[21:18]
--node tb.dut tl_clkmgr_o.a_address[29:23]
--node tb.dut tl_clkmgr_o.a_address[31:31]
--node tb.dut tl_ram_ret_o.a_address[16:12]
--node tb.dut tl_ram_ret_o.a_address[19:18]
--node tb.dut tl_ram_ret_o.a_address[21:21]
--node tb.dut tl_ram_ret_o.a_address[29:23]
--node tb.dut tl_ram_ret_o.a_address[31:31]
+-node tb.dut tl_pwrmgr_aon_o.a_address[21:12]
+-node tb.dut tl_pwrmgr_aon_o.a_address[29:23]
+-node tb.dut tl_pwrmgr_aon_o.a_address[31:31]
+-node tb.dut tl_rstmgr_aon_o.a_address[15:12]
+-node tb.dut tl_rstmgr_aon_o.a_address[21:17]
+-node tb.dut tl_rstmgr_aon_o.a_address[29:23]
+-node tb.dut tl_rstmgr_aon_o.a_address[31:31]
+-node tb.dut tl_clkmgr_aon_o.a_address[16:12]
+-node tb.dut tl_clkmgr_aon_o.a_address[21:18]
+-node tb.dut tl_clkmgr_aon_o.a_address[29:23]
+-node tb.dut tl_clkmgr_aon_o.a_address[31:31]
+-node tb.dut tl_pinmux_aon_o.a_address[16:12]
+-node tb.dut tl_pinmux_aon_o.a_address[21:19]
+-node tb.dut tl_pinmux_aon_o.a_address[29:23]
+-node tb.dut tl_pinmux_aon_o.a_address[31:31]
+-node tb.dut tl_padctrl_aon_o.a_address[15:12]
+-node tb.dut tl_padctrl_aon_o.a_address[21:19]
+-node tb.dut tl_padctrl_aon_o.a_address[29:23]
+-node tb.dut tl_padctrl_aon_o.a_address[31:31]
+-node tb.dut tl_ram_ret_aon_o.a_address[16:12]
+-node tb.dut tl_ram_ret_aon_o.a_address[19:18]
+-node tb.dut tl_ram_ret_aon_o.a_address[21:21]
+-node tb.dut tl_ram_ret_aon_o.a_address[29:23]
+-node tb.dut tl_ram_ret_aon_o.a_address[31:31]
-node tb.dut tl_otp_ctrl_o.a_address[15:14]
-node tb.dut tl_otp_ctrl_o.a_address[19:18]
-node tb.dut tl_otp_ctrl_o.a_address[29:21]
@@ -79,26 +87,28 @@
-node tb.dut tl_lc_ctrl_o.a_address[19:19]
-node tb.dut tl_lc_ctrl_o.a_address[29:21]
-node tb.dut tl_lc_ctrl_o.a_address[31:31]
--node tb.dut tl_sensor_ctrl_o.a_address[15:12]
--node tb.dut tl_sensor_ctrl_o.a_address[19:17]
--node tb.dut tl_sensor_ctrl_o.a_address[29:21]
--node tb.dut tl_sensor_ctrl_o.a_address[31:31]
+-node tb.dut tl_sensor_ctrl_aon_o.a_address[19:12]
+-node tb.dut tl_sensor_ctrl_aon_o.a_address[21:21]
+-node tb.dut tl_sensor_ctrl_aon_o.a_address[29:23]
+-node tb.dut tl_sensor_ctrl_aon_o.a_address[31:31]
-node tb.dut tl_alert_handler_o.a_address[15:12]
-node tb.dut tl_alert_handler_o.a_address[17:17]
-node tb.dut tl_alert_handler_o.a_address[19:19]
-node tb.dut tl_alert_handler_o.a_address[29:21]
-node tb.dut tl_alert_handler_o.a_address[31:31]
--node tb.dut tl_sram_ctrl_ret_o.a_address[15:12]
--node tb.dut tl_sram_ctrl_ret_o.a_address[19:17]
--node tb.dut tl_sram_ctrl_ret_o.a_address[21:21]
--node tb.dut tl_sram_ctrl_ret_o.a_address[29:23]
--node tb.dut tl_sram_ctrl_ret_o.a_address[31:31]
+-node tb.dut tl_sram_ctrl_ret_aon_o.a_address[15:12]
+-node tb.dut tl_sram_ctrl_ret_aon_o.a_address[19:17]
+-node tb.dut tl_sram_ctrl_ret_aon_o.a_address[21:21]
+-node tb.dut tl_sram_ctrl_ret_aon_o.a_address[29:23]
+-node tb.dut tl_sram_ctrl_ret_aon_o.a_address[31:31]
-node tb.dut tl_nmi_gen_o.a_address[16:12]
-node tb.dut tl_nmi_gen_o.a_address[19:19]
-node tb.dut tl_nmi_gen_o.a_address[29:21]
-node tb.dut tl_nmi_gen_o.a_address[31:31]
--node tb.dut tl_ast_wrapper_o.a_address[18:12]
--node tb.dut tl_ast_wrapper_o.a_address[29:21]
+-node tb.dut tl_ast_wrapper_o.a_address[15:12]
+-node tb.dut tl_ast_wrapper_o.a_address[18:17]
+-node tb.dut tl_ast_wrapper_o.a_address[21:20]
+-node tb.dut tl_ast_wrapper_o.a_address[29:23]
-node tb.dut tl_ast_wrapper_o.a_address[31:31]
begin tgl
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
index 69bde58..1c4346b 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
@@ -41,18 +41,24 @@
'{32'h40100000, 32'h40100fff}
}},
'{"usbdev", '{
- '{32'h40500000, 32'h40500fff}
+ '{32'h40110000, 32'h40110fff}
}},
- '{"pwrmgr", '{
+ '{"pwrmgr_aon", '{
'{32'h40400000, 32'h40400fff}
}},
- '{"rstmgr", '{
+ '{"rstmgr_aon", '{
'{32'h40410000, 32'h40410fff}
}},
- '{"clkmgr", '{
+ '{"clkmgr_aon", '{
'{32'h40420000, 32'h40420fff}
}},
- '{"ram_ret", '{
+ '{"pinmux_aon", '{
+ '{32'h40460000, 32'h40460fff}
+ }},
+ '{"padctrl_aon", '{
+ '{32'h40470000, 32'h40470fff}
+ }},
+ '{"ram_ret_aon", '{
'{32'h40520000, 32'h40520fff}
}},
'{"otp_ctrl", '{
@@ -61,20 +67,20 @@
'{"lc_ctrl", '{
'{32'h40140000, 32'h40140fff}
}},
- '{"sensor_ctrl", '{
- '{32'h40110000, 32'h40110fff}
+ '{"sensor_ctrl_aon", '{
+ '{32'h40500000, 32'h40500fff}
}},
'{"alert_handler", '{
'{32'h40150000, 32'h40150fff}
}},
- '{"sram_ctrl_ret", '{
+ '{"sram_ctrl_ret_aon", '{
'{32'h40510000, 32'h40510fff}
}},
'{"nmi_gen", '{
'{32'h40160000, 32'h40160fff}
}},
'{"ast_wrapper", '{
- '{32'h40180000, 32'h40180fff}
+ '{32'h40490000, 32'h40490fff}
}}};
// List of Xbar hosts
@@ -92,15 +98,17 @@
"spi_device",
"rv_timer",
"usbdev",
- "pwrmgr",
- "rstmgr",
- "clkmgr",
- "ram_ret",
+ "pwrmgr_aon",
+ "rstmgr_aon",
+ "clkmgr_aon",
+ "pinmux_aon",
+ "padctrl_aon",
+ "ram_ret_aon",
"otp_ctrl",
"lc_ctrl",
- "sensor_ctrl",
+ "sensor_ctrl_aon",
"alert_handler",
"nmi_gen",
"ast_wrapper",
- "sram_ctrl_ret"}}
+ "sram_ctrl_ret_aon"}}
};
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
index 3945cf9..9001b17 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
@@ -86,29 +86,41 @@
.h2d (tl_usbdev_o),
.d2h (tl_usbdev_i)
);
- bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_pwrmgr (
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_pwrmgr_aon (
.clk_i (clk_peri_i),
.rst_ni (rst_peri_ni),
- .h2d (tl_pwrmgr_o),
- .d2h (tl_pwrmgr_i)
+ .h2d (tl_pwrmgr_aon_o),
+ .d2h (tl_pwrmgr_aon_i)
);
- bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_rstmgr (
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_rstmgr_aon (
.clk_i (clk_peri_i),
.rst_ni (rst_peri_ni),
- .h2d (tl_rstmgr_o),
- .d2h (tl_rstmgr_i)
+ .h2d (tl_rstmgr_aon_o),
+ .d2h (tl_rstmgr_aon_i)
);
- bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_clkmgr (
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_clkmgr_aon (
.clk_i (clk_peri_i),
.rst_ni (rst_peri_ni),
- .h2d (tl_clkmgr_o),
- .d2h (tl_clkmgr_i)
+ .h2d (tl_clkmgr_aon_o),
+ .d2h (tl_clkmgr_aon_i)
);
- bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_ram_ret (
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_pinmux_aon (
.clk_i (clk_peri_i),
.rst_ni (rst_peri_ni),
- .h2d (tl_ram_ret_o),
- .d2h (tl_ram_ret_i)
+ .h2d (tl_pinmux_aon_o),
+ .d2h (tl_pinmux_aon_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_padctrl_aon (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_padctrl_aon_o),
+ .d2h (tl_padctrl_aon_i)
+ );
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_ram_ret_aon (
+ .clk_i (clk_peri_i),
+ .rst_ni (rst_peri_ni),
+ .h2d (tl_ram_ret_aon_o),
+ .d2h (tl_ram_ret_aon_i)
);
bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_otp_ctrl (
.clk_i (clk_peri_i),
@@ -122,11 +134,11 @@
.h2d (tl_lc_ctrl_o),
.d2h (tl_lc_ctrl_i)
);
- bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_sensor_ctrl (
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_sensor_ctrl_aon (
.clk_i (clk_peri_i),
.rst_ni (rst_peri_ni),
- .h2d (tl_sensor_ctrl_o),
- .d2h (tl_sensor_ctrl_i)
+ .h2d (tl_sensor_ctrl_aon_o),
+ .d2h (tl_sensor_ctrl_aon_i)
);
bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_alert_handler (
.clk_i (clk_peri_i),
@@ -134,11 +146,11 @@
.h2d (tl_alert_handler_o),
.d2h (tl_alert_handler_i)
);
- bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_sram_ctrl_ret (
+ bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_sram_ctrl_ret_aon (
.clk_i (clk_peri_i),
.rst_ni (rst_peri_ni),
- .h2d (tl_sram_ctrl_ret_o),
- .d2h (tl_sram_ctrl_ret_i)
+ .h2d (tl_sram_ctrl_ret_aon_o),
+ .d2h (tl_sram_ctrl_ret_aon_i)
);
bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_nmi_gen (
.clk_i (clk_peri_i),
diff --git a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
index 74639fc..4052f45 100644
--- a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
@@ -6,56 +6,60 @@
package tl_peri_pkg;
- localparam logic [31:0] ADDR_SPACE_UART0 = 32'h 40000000;
- localparam logic [31:0] ADDR_SPACE_UART1 = 32'h 40010000;
- localparam logic [31:0] ADDR_SPACE_UART2 = 32'h 40020000;
- localparam logic [31:0] ADDR_SPACE_UART3 = 32'h 40030000;
- localparam logic [31:0] ADDR_SPACE_I2C0 = 32'h 40080000;
- localparam logic [31:0] ADDR_SPACE_I2C1 = 32'h 40090000;
- localparam logic [31:0] ADDR_SPACE_I2C2 = 32'h 400a0000;
- localparam logic [31:0] ADDR_SPACE_PATTGEN = 32'h 400e0000;
- localparam logic [31:0] ADDR_SPACE_GPIO = 32'h 40040000;
- localparam logic [31:0] ADDR_SPACE_SPI_DEVICE = 32'h 40050000;
- localparam logic [31:0] ADDR_SPACE_RV_TIMER = 32'h 40100000;
- localparam logic [31:0] ADDR_SPACE_USBDEV = 32'h 40500000;
- localparam logic [31:0] ADDR_SPACE_PWRMGR = 32'h 40400000;
- localparam logic [31:0] ADDR_SPACE_RSTMGR = 32'h 40410000;
- localparam logic [31:0] ADDR_SPACE_CLKMGR = 32'h 40420000;
- localparam logic [31:0] ADDR_SPACE_RAM_RET = 32'h 40520000;
- localparam logic [31:0] ADDR_SPACE_OTP_CTRL = 32'h 40130000;
- localparam logic [31:0] ADDR_SPACE_LC_CTRL = 32'h 40140000;
- localparam logic [31:0] ADDR_SPACE_SENSOR_CTRL = 32'h 40110000;
- localparam logic [31:0] ADDR_SPACE_ALERT_HANDLER = 32'h 40150000;
- localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_RET = 32'h 40510000;
- localparam logic [31:0] ADDR_SPACE_NMI_GEN = 32'h 40160000;
- localparam logic [31:0] ADDR_SPACE_AST_WRAPPER = 32'h 40180000;
+ localparam logic [31:0] ADDR_SPACE_UART0 = 32'h 40000000;
+ localparam logic [31:0] ADDR_SPACE_UART1 = 32'h 40010000;
+ localparam logic [31:0] ADDR_SPACE_UART2 = 32'h 40020000;
+ localparam logic [31:0] ADDR_SPACE_UART3 = 32'h 40030000;
+ localparam logic [31:0] ADDR_SPACE_I2C0 = 32'h 40080000;
+ localparam logic [31:0] ADDR_SPACE_I2C1 = 32'h 40090000;
+ localparam logic [31:0] ADDR_SPACE_I2C2 = 32'h 400a0000;
+ localparam logic [31:0] ADDR_SPACE_PATTGEN = 32'h 400e0000;
+ localparam logic [31:0] ADDR_SPACE_GPIO = 32'h 40040000;
+ localparam logic [31:0] ADDR_SPACE_SPI_DEVICE = 32'h 40050000;
+ localparam logic [31:0] ADDR_SPACE_RV_TIMER = 32'h 40100000;
+ localparam logic [31:0] ADDR_SPACE_USBDEV = 32'h 40110000;
+ localparam logic [31:0] ADDR_SPACE_PWRMGR_AON = 32'h 40400000;
+ localparam logic [31:0] ADDR_SPACE_RSTMGR_AON = 32'h 40410000;
+ localparam logic [31:0] ADDR_SPACE_CLKMGR_AON = 32'h 40420000;
+ localparam logic [31:0] ADDR_SPACE_PINMUX_AON = 32'h 40460000;
+ localparam logic [31:0] ADDR_SPACE_PADCTRL_AON = 32'h 40470000;
+ localparam logic [31:0] ADDR_SPACE_RAM_RET_AON = 32'h 40520000;
+ localparam logic [31:0] ADDR_SPACE_OTP_CTRL = 32'h 40130000;
+ localparam logic [31:0] ADDR_SPACE_LC_CTRL = 32'h 40140000;
+ localparam logic [31:0] ADDR_SPACE_SENSOR_CTRL_AON = 32'h 40500000;
+ localparam logic [31:0] ADDR_SPACE_ALERT_HANDLER = 32'h 40150000;
+ localparam logic [31:0] ADDR_SPACE_SRAM_CTRL_RET_AON = 32'h 40510000;
+ localparam logic [31:0] ADDR_SPACE_NMI_GEN = 32'h 40160000;
+ localparam logic [31:0] ADDR_SPACE_AST_WRAPPER = 32'h 40490000;
- localparam logic [31:0] ADDR_MASK_UART0 = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_UART1 = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_UART2 = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_UART3 = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_I2C0 = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_I2C1 = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_I2C2 = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_PATTGEN = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_GPIO = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_SPI_DEVICE = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_RV_TIMER = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_USBDEV = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_PWRMGR = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_RSTMGR = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_CLKMGR = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_RAM_RET = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_OTP_CTRL = 32'h 00003fff;
- localparam logic [31:0] ADDR_MASK_LC_CTRL = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_SENSOR_CTRL = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_ALERT_HANDLER = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_SRAM_CTRL_RET = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_NMI_GEN = 32'h 00000fff;
- localparam logic [31:0] ADDR_MASK_AST_WRAPPER = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_UART0 = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_UART1 = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_UART2 = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_UART3 = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_I2C0 = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_I2C1 = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_I2C2 = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_PATTGEN = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_GPIO = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_SPI_DEVICE = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_RV_TIMER = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_USBDEV = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_PWRMGR_AON = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_RSTMGR_AON = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_CLKMGR_AON = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_PINMUX_AON = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_PADCTRL_AON = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_RAM_RET_AON = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_OTP_CTRL = 32'h 00003fff;
+ localparam logic [31:0] ADDR_MASK_LC_CTRL = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_SENSOR_CTRL_AON = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_ALERT_HANDLER = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_SRAM_CTRL_RET_AON = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_NMI_GEN = 32'h 00000fff;
+ localparam logic [31:0] ADDR_MASK_AST_WRAPPER = 32'h 00000fff;
localparam int N_HOST = 1;
- localparam int N_DEVICE = 23;
+ localparam int N_DEVICE = 25;
typedef enum int {
TlUart0 = 0,
@@ -70,17 +74,19 @@
TlSpiDevice = 9,
TlRvTimer = 10,
TlUsbdev = 11,
- TlPwrmgr = 12,
- TlRstmgr = 13,
- TlClkmgr = 14,
- TlRamRet = 15,
- TlOtpCtrl = 16,
- TlLcCtrl = 17,
- TlSensorCtrl = 18,
- TlAlertHandler = 19,
- TlSramCtrlRet = 20,
- TlNmiGen = 21,
- TlAstWrapper = 22
+ TlPwrmgrAon = 12,
+ TlRstmgrAon = 13,
+ TlClkmgrAon = 14,
+ TlPinmuxAon = 15,
+ TlPadctrlAon = 16,
+ TlRamRetAon = 17,
+ TlOtpCtrl = 18,
+ TlLcCtrl = 19,
+ TlSensorCtrlAon = 20,
+ TlAlertHandler = 21,
+ TlSramCtrlRetAon = 22,
+ TlNmiGen = 23,
+ TlAstWrapper = 24
} tl_device_e;
typedef enum int {
diff --git a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv
index c6cfcbd..47b79d4 100644
--- a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv
@@ -7,7 +7,7 @@
//
// Interconnect
// main
-// -> s1n_24
+// -> s1n_26
// -> uart0
// -> uart1
// -> uart2
@@ -20,17 +20,19 @@
// -> spi_device
// -> rv_timer
// -> usbdev
-// -> pwrmgr
-// -> rstmgr
-// -> clkmgr
-// -> ram_ret
+// -> pwrmgr_aon
+// -> rstmgr_aon
+// -> clkmgr_aon
+// -> pinmux_aon
+// -> padctrl_aon
+// -> ram_ret_aon
// -> otp_ctrl
// -> lc_ctrl
-// -> sensor_ctrl
+// -> sensor_ctrl_aon
// -> alert_handler
// -> nmi_gen
// -> ast_wrapper
-// -> sram_ctrl_ret
+// -> sram_ctrl_ret_aon
module xbar_peri (
input clk_peri_i,
@@ -65,24 +67,28 @@
input tlul_pkg::tl_d2h_t tl_rv_timer_i,
output tlul_pkg::tl_h2d_t tl_usbdev_o,
input tlul_pkg::tl_d2h_t tl_usbdev_i,
- output tlul_pkg::tl_h2d_t tl_pwrmgr_o,
- input tlul_pkg::tl_d2h_t tl_pwrmgr_i,
- output tlul_pkg::tl_h2d_t tl_rstmgr_o,
- input tlul_pkg::tl_d2h_t tl_rstmgr_i,
- output tlul_pkg::tl_h2d_t tl_clkmgr_o,
- input tlul_pkg::tl_d2h_t tl_clkmgr_i,
- output tlul_pkg::tl_h2d_t tl_ram_ret_o,
- input tlul_pkg::tl_d2h_t tl_ram_ret_i,
+ output tlul_pkg::tl_h2d_t tl_pwrmgr_aon_o,
+ input tlul_pkg::tl_d2h_t tl_pwrmgr_aon_i,
+ output tlul_pkg::tl_h2d_t tl_rstmgr_aon_o,
+ input tlul_pkg::tl_d2h_t tl_rstmgr_aon_i,
+ output tlul_pkg::tl_h2d_t tl_clkmgr_aon_o,
+ input tlul_pkg::tl_d2h_t tl_clkmgr_aon_i,
+ output tlul_pkg::tl_h2d_t tl_pinmux_aon_o,
+ input tlul_pkg::tl_d2h_t tl_pinmux_aon_i,
+ output tlul_pkg::tl_h2d_t tl_padctrl_aon_o,
+ input tlul_pkg::tl_d2h_t tl_padctrl_aon_i,
+ output tlul_pkg::tl_h2d_t tl_ram_ret_aon_o,
+ input tlul_pkg::tl_d2h_t tl_ram_ret_aon_i,
output tlul_pkg::tl_h2d_t tl_otp_ctrl_o,
input tlul_pkg::tl_d2h_t tl_otp_ctrl_i,
output tlul_pkg::tl_h2d_t tl_lc_ctrl_o,
input tlul_pkg::tl_d2h_t tl_lc_ctrl_i,
- output tlul_pkg::tl_h2d_t tl_sensor_ctrl_o,
- input tlul_pkg::tl_d2h_t tl_sensor_ctrl_i,
+ output tlul_pkg::tl_h2d_t tl_sensor_ctrl_aon_o,
+ input tlul_pkg::tl_d2h_t tl_sensor_ctrl_aon_i,
output tlul_pkg::tl_h2d_t tl_alert_handler_o,
input tlul_pkg::tl_d2h_t tl_alert_handler_i,
- output tlul_pkg::tl_h2d_t tl_sram_ctrl_ret_o,
- input tlul_pkg::tl_d2h_t tl_sram_ctrl_ret_i,
+ output tlul_pkg::tl_h2d_t tl_sram_ctrl_ret_aon_o,
+ input tlul_pkg::tl_d2h_t tl_sram_ctrl_ret_aon_i,
output tlul_pkg::tl_h2d_t tl_nmi_gen_o,
input tlul_pkg::tl_d2h_t tl_nmi_gen_i,
output tlul_pkg::tl_h2d_t tl_ast_wrapper_o,
@@ -99,161 +105,173 @@
logic unused_scanmode;
assign unused_scanmode = scanmode_i;
- tl_h2d_t tl_s1n_24_us_h2d ;
- tl_d2h_t tl_s1n_24_us_d2h ;
+ tl_h2d_t tl_s1n_26_us_h2d ;
+ tl_d2h_t tl_s1n_26_us_d2h ;
- tl_h2d_t tl_s1n_24_ds_h2d [23];
- tl_d2h_t tl_s1n_24_ds_d2h [23];
+ tl_h2d_t tl_s1n_26_ds_h2d [25];
+ tl_d2h_t tl_s1n_26_ds_d2h [25];
// Create steering signal
- logic [4:0] dev_sel_s1n_24;
+ logic [4:0] dev_sel_s1n_26;
- assign tl_uart0_o = tl_s1n_24_ds_h2d[0];
- assign tl_s1n_24_ds_d2h[0] = tl_uart0_i;
+ assign tl_uart0_o = tl_s1n_26_ds_h2d[0];
+ assign tl_s1n_26_ds_d2h[0] = tl_uart0_i;
- assign tl_uart1_o = tl_s1n_24_ds_h2d[1];
- assign tl_s1n_24_ds_d2h[1] = tl_uart1_i;
+ assign tl_uart1_o = tl_s1n_26_ds_h2d[1];
+ assign tl_s1n_26_ds_d2h[1] = tl_uart1_i;
- assign tl_uart2_o = tl_s1n_24_ds_h2d[2];
- assign tl_s1n_24_ds_d2h[2] = tl_uart2_i;
+ assign tl_uart2_o = tl_s1n_26_ds_h2d[2];
+ assign tl_s1n_26_ds_d2h[2] = tl_uart2_i;
- assign tl_uart3_o = tl_s1n_24_ds_h2d[3];
- assign tl_s1n_24_ds_d2h[3] = tl_uart3_i;
+ assign tl_uart3_o = tl_s1n_26_ds_h2d[3];
+ assign tl_s1n_26_ds_d2h[3] = tl_uart3_i;
- assign tl_i2c0_o = tl_s1n_24_ds_h2d[4];
- assign tl_s1n_24_ds_d2h[4] = tl_i2c0_i;
+ assign tl_i2c0_o = tl_s1n_26_ds_h2d[4];
+ assign tl_s1n_26_ds_d2h[4] = tl_i2c0_i;
- assign tl_i2c1_o = tl_s1n_24_ds_h2d[5];
- assign tl_s1n_24_ds_d2h[5] = tl_i2c1_i;
+ assign tl_i2c1_o = tl_s1n_26_ds_h2d[5];
+ assign tl_s1n_26_ds_d2h[5] = tl_i2c1_i;
- assign tl_i2c2_o = tl_s1n_24_ds_h2d[6];
- assign tl_s1n_24_ds_d2h[6] = tl_i2c2_i;
+ assign tl_i2c2_o = tl_s1n_26_ds_h2d[6];
+ assign tl_s1n_26_ds_d2h[6] = tl_i2c2_i;
- assign tl_pattgen_o = tl_s1n_24_ds_h2d[7];
- assign tl_s1n_24_ds_d2h[7] = tl_pattgen_i;
+ assign tl_pattgen_o = tl_s1n_26_ds_h2d[7];
+ assign tl_s1n_26_ds_d2h[7] = tl_pattgen_i;
- assign tl_gpio_o = tl_s1n_24_ds_h2d[8];
- assign tl_s1n_24_ds_d2h[8] = tl_gpio_i;
+ assign tl_gpio_o = tl_s1n_26_ds_h2d[8];
+ assign tl_s1n_26_ds_d2h[8] = tl_gpio_i;
- assign tl_spi_device_o = tl_s1n_24_ds_h2d[9];
- assign tl_s1n_24_ds_d2h[9] = tl_spi_device_i;
+ assign tl_spi_device_o = tl_s1n_26_ds_h2d[9];
+ assign tl_s1n_26_ds_d2h[9] = tl_spi_device_i;
- assign tl_rv_timer_o = tl_s1n_24_ds_h2d[10];
- assign tl_s1n_24_ds_d2h[10] = tl_rv_timer_i;
+ assign tl_rv_timer_o = tl_s1n_26_ds_h2d[10];
+ assign tl_s1n_26_ds_d2h[10] = tl_rv_timer_i;
- assign tl_usbdev_o = tl_s1n_24_ds_h2d[11];
- assign tl_s1n_24_ds_d2h[11] = tl_usbdev_i;
+ assign tl_usbdev_o = tl_s1n_26_ds_h2d[11];
+ assign tl_s1n_26_ds_d2h[11] = tl_usbdev_i;
- assign tl_pwrmgr_o = tl_s1n_24_ds_h2d[12];
- assign tl_s1n_24_ds_d2h[12] = tl_pwrmgr_i;
+ assign tl_pwrmgr_aon_o = tl_s1n_26_ds_h2d[12];
+ assign tl_s1n_26_ds_d2h[12] = tl_pwrmgr_aon_i;
- assign tl_rstmgr_o = tl_s1n_24_ds_h2d[13];
- assign tl_s1n_24_ds_d2h[13] = tl_rstmgr_i;
+ assign tl_rstmgr_aon_o = tl_s1n_26_ds_h2d[13];
+ assign tl_s1n_26_ds_d2h[13] = tl_rstmgr_aon_i;
- assign tl_clkmgr_o = tl_s1n_24_ds_h2d[14];
- assign tl_s1n_24_ds_d2h[14] = tl_clkmgr_i;
+ assign tl_clkmgr_aon_o = tl_s1n_26_ds_h2d[14];
+ assign tl_s1n_26_ds_d2h[14] = tl_clkmgr_aon_i;
- assign tl_ram_ret_o = tl_s1n_24_ds_h2d[15];
- assign tl_s1n_24_ds_d2h[15] = tl_ram_ret_i;
+ assign tl_pinmux_aon_o = tl_s1n_26_ds_h2d[15];
+ assign tl_s1n_26_ds_d2h[15] = tl_pinmux_aon_i;
- assign tl_otp_ctrl_o = tl_s1n_24_ds_h2d[16];
- assign tl_s1n_24_ds_d2h[16] = tl_otp_ctrl_i;
+ assign tl_padctrl_aon_o = tl_s1n_26_ds_h2d[16];
+ assign tl_s1n_26_ds_d2h[16] = tl_padctrl_aon_i;
- assign tl_lc_ctrl_o = tl_s1n_24_ds_h2d[17];
- assign tl_s1n_24_ds_d2h[17] = tl_lc_ctrl_i;
+ assign tl_ram_ret_aon_o = tl_s1n_26_ds_h2d[17];
+ assign tl_s1n_26_ds_d2h[17] = tl_ram_ret_aon_i;
- assign tl_sensor_ctrl_o = tl_s1n_24_ds_h2d[18];
- assign tl_s1n_24_ds_d2h[18] = tl_sensor_ctrl_i;
+ assign tl_otp_ctrl_o = tl_s1n_26_ds_h2d[18];
+ assign tl_s1n_26_ds_d2h[18] = tl_otp_ctrl_i;
- assign tl_alert_handler_o = tl_s1n_24_ds_h2d[19];
- assign tl_s1n_24_ds_d2h[19] = tl_alert_handler_i;
+ assign tl_lc_ctrl_o = tl_s1n_26_ds_h2d[19];
+ assign tl_s1n_26_ds_d2h[19] = tl_lc_ctrl_i;
- assign tl_nmi_gen_o = tl_s1n_24_ds_h2d[20];
- assign tl_s1n_24_ds_d2h[20] = tl_nmi_gen_i;
+ assign tl_sensor_ctrl_aon_o = tl_s1n_26_ds_h2d[20];
+ assign tl_s1n_26_ds_d2h[20] = tl_sensor_ctrl_aon_i;
- assign tl_ast_wrapper_o = tl_s1n_24_ds_h2d[21];
- assign tl_s1n_24_ds_d2h[21] = tl_ast_wrapper_i;
+ assign tl_alert_handler_o = tl_s1n_26_ds_h2d[21];
+ assign tl_s1n_26_ds_d2h[21] = tl_alert_handler_i;
- assign tl_sram_ctrl_ret_o = tl_s1n_24_ds_h2d[22];
- assign tl_s1n_24_ds_d2h[22] = tl_sram_ctrl_ret_i;
+ assign tl_nmi_gen_o = tl_s1n_26_ds_h2d[22];
+ assign tl_s1n_26_ds_d2h[22] = tl_nmi_gen_i;
- assign tl_s1n_24_us_h2d = tl_main_i;
- assign tl_main_o = tl_s1n_24_us_d2h;
+ assign tl_ast_wrapper_o = tl_s1n_26_ds_h2d[23];
+ assign tl_s1n_26_ds_d2h[23] = tl_ast_wrapper_i;
+
+ assign tl_sram_ctrl_ret_aon_o = tl_s1n_26_ds_h2d[24];
+ assign tl_s1n_26_ds_d2h[24] = tl_sram_ctrl_ret_aon_i;
+
+ assign tl_s1n_26_us_h2d = tl_main_i;
+ assign tl_main_o = tl_s1n_26_us_d2h;
always_comb begin
// default steering to generate error response if address is not within the range
- dev_sel_s1n_24 = 5'd23;
- if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_UART0)) == ADDR_SPACE_UART0) begin
- dev_sel_s1n_24 = 5'd0;
+ dev_sel_s1n_26 = 5'd25;
+ if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_UART0)) == ADDR_SPACE_UART0) begin
+ dev_sel_s1n_26 = 5'd0;
- end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_UART1)) == ADDR_SPACE_UART1) begin
- dev_sel_s1n_24 = 5'd1;
+ end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_UART1)) == ADDR_SPACE_UART1) begin
+ dev_sel_s1n_26 = 5'd1;
- end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_UART2)) == ADDR_SPACE_UART2) begin
- dev_sel_s1n_24 = 5'd2;
+ end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_UART2)) == ADDR_SPACE_UART2) begin
+ dev_sel_s1n_26 = 5'd2;
- end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_UART3)) == ADDR_SPACE_UART3) begin
- dev_sel_s1n_24 = 5'd3;
+ end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_UART3)) == ADDR_SPACE_UART3) begin
+ dev_sel_s1n_26 = 5'd3;
- end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_I2C0)) == ADDR_SPACE_I2C0) begin
- dev_sel_s1n_24 = 5'd4;
+ end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_I2C0)) == ADDR_SPACE_I2C0) begin
+ dev_sel_s1n_26 = 5'd4;
- end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_I2C1)) == ADDR_SPACE_I2C1) begin
- dev_sel_s1n_24 = 5'd5;
+ end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_I2C1)) == ADDR_SPACE_I2C1) begin
+ dev_sel_s1n_26 = 5'd5;
- end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_I2C2)) == ADDR_SPACE_I2C2) begin
- dev_sel_s1n_24 = 5'd6;
+ end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_I2C2)) == ADDR_SPACE_I2C2) begin
+ dev_sel_s1n_26 = 5'd6;
- end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_PATTGEN)) == ADDR_SPACE_PATTGEN) begin
- dev_sel_s1n_24 = 5'd7;
+ end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_PATTGEN)) == ADDR_SPACE_PATTGEN) begin
+ dev_sel_s1n_26 = 5'd7;
- end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
- dev_sel_s1n_24 = 5'd8;
+ end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
+ dev_sel_s1n_26 = 5'd8;
- end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin
- dev_sel_s1n_24 = 5'd9;
+ end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin
+ dev_sel_s1n_26 = 5'd9;
- end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin
- dev_sel_s1n_24 = 5'd10;
+ end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin
+ dev_sel_s1n_26 = 5'd10;
- end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin
- dev_sel_s1n_24 = 5'd11;
+ end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin
+ dev_sel_s1n_26 = 5'd11;
- end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_PWRMGR)) == ADDR_SPACE_PWRMGR) begin
- dev_sel_s1n_24 = 5'd12;
+ end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_PWRMGR_AON)) == ADDR_SPACE_PWRMGR_AON) begin
+ dev_sel_s1n_26 = 5'd12;
- end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_RSTMGR)) == ADDR_SPACE_RSTMGR) begin
- dev_sel_s1n_24 = 5'd13;
+ end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_RSTMGR_AON)) == ADDR_SPACE_RSTMGR_AON) begin
+ dev_sel_s1n_26 = 5'd13;
- end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_CLKMGR)) == ADDR_SPACE_CLKMGR) begin
- dev_sel_s1n_24 = 5'd14;
+ end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_CLKMGR_AON)) == ADDR_SPACE_CLKMGR_AON) begin
+ dev_sel_s1n_26 = 5'd14;
- end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_RAM_RET)) == ADDR_SPACE_RAM_RET) begin
- dev_sel_s1n_24 = 5'd15;
+ end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_PINMUX_AON)) == ADDR_SPACE_PINMUX_AON) begin
+ dev_sel_s1n_26 = 5'd15;
- end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_OTP_CTRL)) == ADDR_SPACE_OTP_CTRL) begin
- dev_sel_s1n_24 = 5'd16;
+ end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_PADCTRL_AON)) == ADDR_SPACE_PADCTRL_AON) begin
+ dev_sel_s1n_26 = 5'd16;
- end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_LC_CTRL)) == ADDR_SPACE_LC_CTRL) begin
- dev_sel_s1n_24 = 5'd17;
+ end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_RAM_RET_AON)) == ADDR_SPACE_RAM_RET_AON) begin
+ dev_sel_s1n_26 = 5'd17;
- end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_SENSOR_CTRL)) == ADDR_SPACE_SENSOR_CTRL) begin
- dev_sel_s1n_24 = 5'd18;
+ end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_OTP_CTRL)) == ADDR_SPACE_OTP_CTRL) begin
+ dev_sel_s1n_26 = 5'd18;
- end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin
- dev_sel_s1n_24 = 5'd19;
+ end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_LC_CTRL)) == ADDR_SPACE_LC_CTRL) begin
+ dev_sel_s1n_26 = 5'd19;
- end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin
- dev_sel_s1n_24 = 5'd20;
+ end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_SENSOR_CTRL_AON)) == ADDR_SPACE_SENSOR_CTRL_AON) begin
+ dev_sel_s1n_26 = 5'd20;
- end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_AST_WRAPPER)) == ADDR_SPACE_AST_WRAPPER) begin
- dev_sel_s1n_24 = 5'd21;
+ end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin
+ dev_sel_s1n_26 = 5'd21;
- end else if ((tl_s1n_24_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_RET)) == ADDR_SPACE_SRAM_CTRL_RET) begin
- dev_sel_s1n_24 = 5'd22;
+ end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin
+ dev_sel_s1n_26 = 5'd22;
+
+ end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_AST_WRAPPER)) == ADDR_SPACE_AST_WRAPPER) begin
+ dev_sel_s1n_26 = 5'd23;
+
+ end else if ((tl_s1n_26_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_RET_AON)) == ADDR_SPACE_SRAM_CTRL_RET_AON) begin
+ dev_sel_s1n_26 = 5'd24;
end
end
@@ -262,17 +280,17 @@
tlul_socket_1n #(
.HReqDepth (4'h0),
.HRspDepth (4'h0),
- .DReqDepth (92'h0),
- .DRspDepth (92'h0),
- .N (23)
- ) u_s1n_24 (
+ .DReqDepth (100'h0),
+ .DRspDepth (100'h0),
+ .N (25)
+ ) u_s1n_26 (
.clk_i (clk_peri_i),
.rst_ni (rst_peri_ni),
- .tl_h_i (tl_s1n_24_us_h2d),
- .tl_h_o (tl_s1n_24_us_d2h),
- .tl_d_o (tl_s1n_24_ds_h2d),
- .tl_d_i (tl_s1n_24_ds_d2h),
- .dev_select_i (dev_sel_s1n_24)
+ .tl_h_i (tl_s1n_26_us_h2d),
+ .tl_h_o (tl_s1n_26_us_d2h),
+ .tl_d_o (tl_s1n_26_ds_h2d),
+ .tl_d_i (tl_s1n_26_ds_d2h),
+ .dev_select_i (dev_sel_s1n_26)
);
endmodule
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 953c7a1..93ab59a 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -59,8 +59,8 @@
input logic clk_usb_i,
input logic clk_aon_i,
input rstmgr_pkg::rstmgr_ast_t rstmgr_ast_i,
- output pwrmgr_pkg::pwr_ast_req_t pwrmgr_pwr_ast_req_o,
- input pwrmgr_pkg::pwr_ast_rsp_t pwrmgr_pwr_ast_rsp_i,
+ output pwrmgr_pkg::pwr_ast_req_t pwrmgr_ast_req_o,
+ input pwrmgr_pkg::pwr_ast_rsp_t pwrmgr_ast_rsp_i,
input ast_wrapper_pkg::ast_alert_req_t sensor_ctrl_ast_alert_req_i,
output ast_wrapper_pkg::ast_alert_rsp_t sensor_ctrl_ast_alert_rsp_o,
input ast_wrapper_pkg::ast_status_t sensor_ctrl_ast_status_i,
@@ -163,16 +163,6 @@
logic cio_pattgen_pcl1_tx_d2p;
logic cio_pattgen_pcl1_tx_en_d2p;
// rv_timer
- // sensor_ctrl
- // otp_ctrl
- // lc_ctrl
- // alert_handler
- // nmi_gen
- // pwrmgr
- // rstmgr
- // clkmgr
- // pinmux
- // padctrl
// usbdev
logic cio_usbdev_sense_p2d;
logic cio_usbdev_d_p2d;
@@ -194,7 +184,17 @@
logic cio_usbdev_dp_en_d2p;
logic cio_usbdev_dn_d2p;
logic cio_usbdev_dn_en_d2p;
- // sram_ctrl_ret
+ // otp_ctrl
+ // lc_ctrl
+ // alert_handler
+ // nmi_gen
+ // pwrmgr_aon
+ // rstmgr_aon
+ // clkmgr_aon
+ // pinmux_aon
+ // padctrl_aon
+ // sensor_ctrl_aon
+ // sram_ctrl_ret_aon
// flash_ctrl
// rv_plic
// aes
@@ -301,16 +301,6 @@
logic intr_pattgen_done_ch0;
logic intr_pattgen_done_ch1;
logic intr_rv_timer_timer_expired_0_0;
- logic intr_otp_ctrl_otp_operation_done;
- logic intr_otp_ctrl_otp_error;
- logic intr_alert_handler_classa;
- logic intr_alert_handler_classb;
- logic intr_alert_handler_classc;
- logic intr_alert_handler_classd;
- logic intr_nmi_gen_esc0;
- logic intr_nmi_gen_esc1;
- logic intr_nmi_gen_esc2;
- logic intr_pwrmgr_wakeup;
logic intr_usbdev_pkt_received;
logic intr_usbdev_pkt_sent;
logic intr_usbdev_disconnected;
@@ -328,6 +318,16 @@
logic intr_usbdev_frame;
logic intr_usbdev_connected;
logic intr_usbdev_link_out_err;
+ logic intr_otp_ctrl_otp_operation_done;
+ logic intr_otp_ctrl_otp_error;
+ logic intr_alert_handler_classa;
+ logic intr_alert_handler_classb;
+ logic intr_alert_handler_classc;
+ logic intr_alert_handler_classd;
+ logic intr_nmi_gen_esc0;
+ logic intr_nmi_gen_esc1;
+ logic intr_nmi_gen_esc2;
+ logic intr_pwrmgr_aon_wakeup;
logic intr_flash_ctrl_prog_empty;
logic intr_flash_ctrl_prog_lvl;
logic intr_flash_ctrl_rd_full;
@@ -386,31 +386,31 @@
lc_ctrl_pkg::lc_flash_rma_seed_t flash_ctrl_rma_seed;
sram_ctrl_pkg::sram_scr_req_t sram_ctrl_main_sram_scr_req;
sram_ctrl_pkg::sram_scr_rsp_t sram_ctrl_main_sram_scr_rsp;
- sram_ctrl_pkg::sram_scr_req_t sram_ctrl_ret_sram_scr_req;
- sram_ctrl_pkg::sram_scr_rsp_t sram_ctrl_ret_sram_scr_rsp;
+ sram_ctrl_pkg::sram_scr_req_t sram_ctrl_ret_aon_sram_scr_req;
+ sram_ctrl_pkg::sram_scr_rsp_t sram_ctrl_ret_aon_sram_scr_rsp;
otp_ctrl_pkg::sram_otp_key_req_t [1:0] otp_ctrl_sram_otp_key_req;
otp_ctrl_pkg::sram_otp_key_rsp_t [1:0] otp_ctrl_sram_otp_key_rsp;
- pwrmgr_pkg::pwr_flash_req_t pwrmgr_pwr_flash_req;
- pwrmgr_pkg::pwr_flash_rsp_t pwrmgr_pwr_flash_rsp;
- pwrmgr_pkg::pwr_rst_req_t pwrmgr_pwr_rst_req;
- pwrmgr_pkg::pwr_rst_rsp_t pwrmgr_pwr_rst_rsp;
- pwrmgr_pkg::pwr_clk_req_t pwrmgr_pwr_clk_req;
- pwrmgr_pkg::pwr_clk_rsp_t pwrmgr_pwr_clk_rsp;
- pwrmgr_pkg::pwr_otp_req_t pwrmgr_pwr_otp_req;
- pwrmgr_pkg::pwr_otp_rsp_t pwrmgr_pwr_otp_rsp;
- pwrmgr_pkg::pwr_lc_req_t pwrmgr_pwr_lc_req;
- pwrmgr_pkg::pwr_lc_rsp_t pwrmgr_pwr_lc_rsp;
+ pwrmgr_pkg::pwr_flash_req_t pwrmgr_aon_pwr_flash_req;
+ pwrmgr_pkg::pwr_flash_rsp_t pwrmgr_aon_pwr_flash_rsp;
+ pwrmgr_pkg::pwr_rst_req_t pwrmgr_aon_pwr_rst_req;
+ pwrmgr_pkg::pwr_rst_rsp_t pwrmgr_aon_pwr_rst_rsp;
+ pwrmgr_pkg::pwr_clk_req_t pwrmgr_aon_pwr_clk_req;
+ pwrmgr_pkg::pwr_clk_rsp_t pwrmgr_aon_pwr_clk_rsp;
+ pwrmgr_pkg::pwr_otp_req_t pwrmgr_aon_pwr_otp_req;
+ pwrmgr_pkg::pwr_otp_rsp_t pwrmgr_aon_pwr_otp_rsp;
+ pwrmgr_pkg::pwr_lc_req_t pwrmgr_aon_pwr_lc_req;
+ pwrmgr_pkg::pwr_lc_rsp_t pwrmgr_aon_pwr_lc_rsp;
rv_core_ibex_pkg::crashdump_t rv_core_ibex_crashdump;
logic usbdev_usb_out_of_rst;
logic usbdev_usb_aon_wake_en;
logic usbdev_usb_aon_wake_ack;
logic usbdev_usb_suspend;
- usbdev_pkg::awk_state_t pinmux_usb_state_debug;
+ usbdev_pkg::awk_state_t pinmux_aon_usb_state_debug;
otp_ctrl_pkg::otp_keymgr_key_t otp_ctrl_otp_keymgr_key;
keymgr_pkg::hw_key_req_t keymgr_kmac_key;
keymgr_pkg::kmac_data_req_t keymgr_kmac_data_req;
keymgr_pkg::kmac_data_rsp_t keymgr_kmac_data_rsp;
- logic [3:0] clkmgr_idle;
+ logic [3:0] clkmgr_aon_idle;
otp_ctrl_pkg::otp_lc_data_t otp_ctrl_otp_lc_data;
otp_ctrl_pkg::lc_otp_program_req_t lc_ctrl_lc_otp_program_req;
otp_ctrl_pkg::lc_otp_program_rsp_t lc_ctrl_lc_otp_program_rsp;
@@ -431,8 +431,8 @@
lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_iso_part_sw_rd_en;
lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_iso_part_sw_wr_en;
lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_seed_hw_rd_en;
- logic pwrmgr_wakeups;
- logic pwrmgr_rstreqs;
+ logic pwrmgr_aon_wakeups;
+ logic pwrmgr_aon_rstreqs;
tlul_pkg::tl_h2d_t rom_tl_req;
tlul_pkg::tl_d2h_t rom_tl_rsp;
tlul_pkg::tl_h2d_t ram_main_tl_req;
@@ -459,10 +459,6 @@
tlul_pkg::tl_d2h_t edn1_tl_rsp;
tlul_pkg::tl_h2d_t rv_plic_tl_req;
tlul_pkg::tl_d2h_t rv_plic_tl_rsp;
- tlul_pkg::tl_h2d_t pinmux_tl_req;
- tlul_pkg::tl_d2h_t pinmux_tl_rsp;
- tlul_pkg::tl_h2d_t padctrl_tl_req;
- tlul_pkg::tl_d2h_t padctrl_tl_rsp;
tlul_pkg::tl_h2d_t otbn_tl_req;
tlul_pkg::tl_d2h_t otbn_tl_rsp;
tlul_pkg::tl_h2d_t keymgr_tl_req;
@@ -493,30 +489,34 @@
tlul_pkg::tl_d2h_t rv_timer_tl_rsp;
tlul_pkg::tl_h2d_t usbdev_tl_req;
tlul_pkg::tl_d2h_t usbdev_tl_rsp;
- tlul_pkg::tl_h2d_t pwrmgr_tl_req;
- tlul_pkg::tl_d2h_t pwrmgr_tl_rsp;
- tlul_pkg::tl_h2d_t rstmgr_tl_req;
- tlul_pkg::tl_d2h_t rstmgr_tl_rsp;
- tlul_pkg::tl_h2d_t clkmgr_tl_req;
- tlul_pkg::tl_d2h_t clkmgr_tl_rsp;
- tlul_pkg::tl_h2d_t ram_ret_tl_req;
- tlul_pkg::tl_d2h_t ram_ret_tl_rsp;
+ tlul_pkg::tl_h2d_t pwrmgr_aon_tl_req;
+ tlul_pkg::tl_d2h_t pwrmgr_aon_tl_rsp;
+ tlul_pkg::tl_h2d_t rstmgr_aon_tl_req;
+ tlul_pkg::tl_d2h_t rstmgr_aon_tl_rsp;
+ tlul_pkg::tl_h2d_t clkmgr_aon_tl_req;
+ tlul_pkg::tl_d2h_t clkmgr_aon_tl_rsp;
+ tlul_pkg::tl_h2d_t pinmux_aon_tl_req;
+ tlul_pkg::tl_d2h_t pinmux_aon_tl_rsp;
+ tlul_pkg::tl_h2d_t padctrl_aon_tl_req;
+ tlul_pkg::tl_d2h_t padctrl_aon_tl_rsp;
+ tlul_pkg::tl_h2d_t ram_ret_aon_tl_req;
+ tlul_pkg::tl_d2h_t ram_ret_aon_tl_rsp;
tlul_pkg::tl_h2d_t otp_ctrl_tl_req;
tlul_pkg::tl_d2h_t otp_ctrl_tl_rsp;
tlul_pkg::tl_h2d_t lc_ctrl_tl_req;
tlul_pkg::tl_d2h_t lc_ctrl_tl_rsp;
- tlul_pkg::tl_h2d_t sensor_ctrl_tl_req;
- tlul_pkg::tl_d2h_t sensor_ctrl_tl_rsp;
+ tlul_pkg::tl_h2d_t sensor_ctrl_aon_tl_req;
+ tlul_pkg::tl_d2h_t sensor_ctrl_aon_tl_rsp;
tlul_pkg::tl_h2d_t alert_handler_tl_req;
tlul_pkg::tl_d2h_t alert_handler_tl_rsp;
- tlul_pkg::tl_h2d_t sram_ctrl_ret_tl_req;
- tlul_pkg::tl_d2h_t sram_ctrl_ret_tl_rsp;
+ tlul_pkg::tl_h2d_t sram_ctrl_ret_aon_tl_req;
+ tlul_pkg::tl_d2h_t sram_ctrl_ret_aon_tl_rsp;
tlul_pkg::tl_h2d_t nmi_gen_tl_req;
tlul_pkg::tl_d2h_t nmi_gen_tl_rsp;
- rstmgr_pkg::rstmgr_out_t rstmgr_resets;
- rstmgr_pkg::rstmgr_cpu_t rstmgr_cpu;
- pwrmgr_pkg::pwr_cpu_t pwrmgr_pwr_cpu;
- clkmgr_pkg::clkmgr_out_t clkmgr_clocks;
+ rstmgr_pkg::rstmgr_out_t rstmgr_aon_resets;
+ rstmgr_pkg::rstmgr_cpu_t rstmgr_aon_cpu;
+ pwrmgr_pkg::pwr_cpu_t pwrmgr_aon_pwr_cpu;
+ clkmgr_pkg::clkmgr_out_t clkmgr_aon_clocks;
tlul_pkg::tl_h2d_t main_tl_corei_req;
tlul_pkg::tl_d2h_t main_tl_corei_rsp;
tlul_pkg::tl_h2d_t main_tl_cored_req;
@@ -541,19 +541,19 @@
logic unused_daon_rst_i2c0;
logic unused_daon_rst_i2c1;
logic unused_daon_rst_i2c2;
- assign unused_d0_rst_por_aon = rstmgr_resets.rst_por_aon_n[rstmgr_pkg::Domain0Sel];
- assign unused_d0_rst_por = rstmgr_resets.rst_por_n[rstmgr_pkg::Domain0Sel];
- assign unused_d0_rst_por_io = rstmgr_resets.rst_por_io_n[rstmgr_pkg::Domain0Sel];
- assign unused_d0_rst_por_io_div2 = rstmgr_resets.rst_por_io_div2_n[rstmgr_pkg::Domain0Sel];
- assign unused_d0_rst_por_io_div4 = rstmgr_resets.rst_por_io_div4_n[rstmgr_pkg::Domain0Sel];
- assign unused_d0_rst_por_usb = rstmgr_resets.rst_por_usb_n[rstmgr_pkg::Domain0Sel];
- assign unused_daon_rst_lc = rstmgr_resets.rst_lc_n[rstmgr_pkg::DomainAonSel];
- assign unused_daon_rst_lc_io_div4 = rstmgr_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel];
- assign unused_daon_rst_spi_device = rstmgr_resets.rst_spi_device_n[rstmgr_pkg::DomainAonSel];
- assign unused_daon_rst_usb = rstmgr_resets.rst_usb_n[rstmgr_pkg::DomainAonSel];
- assign unused_daon_rst_i2c0 = rstmgr_resets.rst_i2c0_n[rstmgr_pkg::DomainAonSel];
- assign unused_daon_rst_i2c1 = rstmgr_resets.rst_i2c1_n[rstmgr_pkg::DomainAonSel];
- assign unused_daon_rst_i2c2 = rstmgr_resets.rst_i2c2_n[rstmgr_pkg::DomainAonSel];
+ assign unused_d0_rst_por_aon = rstmgr_aon_resets.rst_por_aon_n[rstmgr_pkg::Domain0Sel];
+ assign unused_d0_rst_por = rstmgr_aon_resets.rst_por_n[rstmgr_pkg::Domain0Sel];
+ assign unused_d0_rst_por_io = rstmgr_aon_resets.rst_por_io_n[rstmgr_pkg::Domain0Sel];
+ assign unused_d0_rst_por_io_div2 = rstmgr_aon_resets.rst_por_io_div2_n[rstmgr_pkg::Domain0Sel];
+ assign unused_d0_rst_por_io_div4 = rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::Domain0Sel];
+ assign unused_d0_rst_por_usb = rstmgr_aon_resets.rst_por_usb_n[rstmgr_pkg::Domain0Sel];
+ assign unused_daon_rst_lc = rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::DomainAonSel];
+ assign unused_daon_rst_lc_io_div4 = rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel];
+ assign unused_daon_rst_spi_device = rstmgr_aon_resets.rst_spi_device_n[rstmgr_pkg::DomainAonSel];
+ assign unused_daon_rst_usb = rstmgr_aon_resets.rst_usb_n[rstmgr_pkg::DomainAonSel];
+ assign unused_daon_rst_i2c0 = rstmgr_aon_resets.rst_i2c0_n[rstmgr_pkg::DomainAonSel];
+ assign unused_daon_rst_i2c1 = rstmgr_aon_resets.rst_i2c1_n[rstmgr_pkg::DomainAonSel];
+ assign unused_daon_rst_i2c2 = rstmgr_aon_resets.rst_i2c2_n[rstmgr_pkg::DomainAonSel];
// Non-debug module reset == reset for everything except for the debug module
logic ndmreset_req;
@@ -584,10 +584,10 @@
.PipeLine (IbexPipeLine)
) u_rv_core_ibex (
// clock and reset
- .clk_i (clkmgr_clocks.clk_proc_main),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
- .clk_esc_i (clkmgr_clocks.clk_io_div4_timers),
- .rst_esc_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]),
+ .clk_i (clkmgr_aon_clocks.clk_proc_main),
+ .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
+ .clk_esc_i (clkmgr_aon_clocks.clk_io_div4_timers),
+ .rst_esc_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]),
.test_en_i (1'b0),
// static pinning
.hart_id_i (32'b0),
@@ -610,7 +610,7 @@
.crash_dump_o (rv_core_ibex_crashdump),
// CPU control signals
.fetch_enable_i (1'b1),
- .core_sleep_o (pwrmgr_pwr_cpu.core_sleeping)
+ .core_sleep_o (pwrmgr_aon_pwr_cpu.core_sleeping)
);
// Debug Module (RISC-V Debug Spec 0.13)
@@ -633,8 +633,8 @@
.NrHarts (1),
.IdcodeValue (JTAG_IDCODE)
) u_dm_top (
- .clk_i (clkmgr_clocks.clk_proc_main),
- .rst_ni (rstmgr_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
+ .clk_i (clkmgr_aon_clocks.clk_proc_main),
+ .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
.testmode_i (1'b0),
.ndmreset_o (ndmreset_req),
.dmactive_o (),
@@ -654,8 +654,8 @@
.jtag_rsp_o (jtag_rsp)
);
- assign rstmgr_cpu.ndmreset_req = ndmreset_req;
- assign rstmgr_cpu.rst_cpu_n = rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel];
+ assign rstmgr_aon_cpu.ndmreset_req = ndmreset_req;
+ assign rstmgr_aon_cpu.rst_cpu_n = rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel];
// ROM device
logic rom_req;
@@ -669,8 +669,8 @@
.Outstanding(2),
.ErrOnWrite(1)
) u_tl_adapter_rom (
- .clk_i (clkmgr_clocks.clk_main_infra),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
+ .clk_i (clkmgr_aon_clocks.clk_main_infra),
+ .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
.tl_i (rom_tl_req),
.tl_o (rom_tl_rsp),
@@ -691,8 +691,8 @@
.Depth(4096),
.MemInitFile(BootRomInitFile)
) u_rom_rom (
- .clk_i (clkmgr_clocks.clk_main_infra),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
+ .clk_i (clkmgr_aon_clocks.clk_main_infra),
+ .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
.req_i (rom_req),
.addr_i (rom_addr),
.rdata_o (rom_rdata),
@@ -716,8 +716,8 @@
.SramDw(32),
.Outstanding(2)
) u_tl_adapter_ram_main (
- .clk_i (clkmgr_clocks.clk_main_infra),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
+ .clk_i (clkmgr_aon_clocks.clk_main_infra),
+ .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
.tl_i (ram_main_tl_req),
.tl_o (ram_main_tl_rsp),
@@ -737,8 +737,8 @@
.Depth(32768),
.CfgWidth(8)
) u_ram1p_ram_main (
- .clk_i (clkmgr_clocks.clk_main_infra),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
+ .clk_i (clkmgr_aon_clocks.clk_main_infra),
+ .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
.key_valid_i ( sram_ctrl_main_sram_scr_req.valid ),
.key_i ( sram_ctrl_main_sram_scr_req.key ),
@@ -760,63 +760,63 @@
assign sram_ctrl_main_sram_scr_rsp.rerror = ram_main_rerror;
// sram device
- logic ram_ret_req;
- logic ram_ret_gnt;
- logic ram_ret_we;
- logic [9:0] ram_ret_addr;
- logic [31:0] ram_ret_wdata;
- logic [31:0] ram_ret_wmask;
- logic [31:0] ram_ret_rdata;
- logic ram_ret_rvalid;
- logic [1:0] ram_ret_rerror;
+ logic ram_ret_aon_req;
+ logic ram_ret_aon_gnt;
+ logic ram_ret_aon_we;
+ logic [9:0] ram_ret_aon_addr;
+ logic [31:0] ram_ret_aon_wdata;
+ logic [31:0] ram_ret_aon_wmask;
+ logic [31:0] ram_ret_aon_rdata;
+ logic ram_ret_aon_rvalid;
+ logic [1:0] ram_ret_aon_rerror;
tlul_adapter_sram #(
.SramAw(10),
.SramDw(32),
.Outstanding(2)
- ) u_tl_adapter_ram_ret (
- .clk_i (clkmgr_clocks.clk_io_div4_infra),
- .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]),
- .tl_i (ram_ret_tl_req),
- .tl_o (ram_ret_tl_rsp),
+ ) u_tl_adapter_ram_ret_aon (
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_infra),
+ .rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]),
+ .tl_i (ram_ret_aon_tl_req),
+ .tl_o (ram_ret_aon_tl_rsp),
- .req_o (ram_ret_req),
- .gnt_i (ram_ret_gnt),
- .we_o (ram_ret_we),
- .addr_o (ram_ret_addr),
- .wdata_o (ram_ret_wdata),
- .wmask_o (ram_ret_wmask),
- .rdata_i (ram_ret_rdata),
- .rvalid_i (ram_ret_rvalid),
- .rerror_i (ram_ret_rerror)
+ .req_o (ram_ret_aon_req),
+ .gnt_i (ram_ret_aon_gnt),
+ .we_o (ram_ret_aon_we),
+ .addr_o (ram_ret_aon_addr),
+ .wdata_o (ram_ret_aon_wdata),
+ .wmask_o (ram_ret_aon_wmask),
+ .rdata_i (ram_ret_aon_rdata),
+ .rvalid_i (ram_ret_aon_rvalid),
+ .rerror_i (ram_ret_aon_rerror)
);
prim_ram_1p_scr #(
.Width(32),
.Depth(1024),
.CfgWidth(8)
- ) u_ram1p_ram_ret (
- .clk_i (clkmgr_clocks.clk_io_div4_infra),
- .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]),
+ ) u_ram1p_ram_ret_aon (
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_infra),
+ .rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]),
- .key_valid_i ( sram_ctrl_ret_sram_scr_req.valid ),
- .key_i ( sram_ctrl_ret_sram_scr_req.key ),
- .nonce_i ( sram_ctrl_ret_sram_scr_req.nonce ),
+ .key_valid_i ( sram_ctrl_ret_aon_sram_scr_req.valid ),
+ .key_i ( sram_ctrl_ret_aon_sram_scr_req.key ),
+ .nonce_i ( sram_ctrl_ret_aon_sram_scr_req.nonce ),
- .req_i (ram_ret_req),
- .gnt_o (ram_ret_gnt),
- .write_i (ram_ret_we),
- .addr_i (ram_ret_addr),
- .wdata_i (ram_ret_wdata),
- .wmask_i (ram_ret_wmask),
- .rdata_o (ram_ret_rdata),
- .rvalid_o (ram_ret_rvalid),
- .rerror_o (ram_ret_rerror),
- .raddr_o ( sram_ctrl_ret_sram_scr_rsp.raddr ),
+ .req_i (ram_ret_aon_req),
+ .gnt_o (ram_ret_aon_gnt),
+ .write_i (ram_ret_aon_we),
+ .addr_i (ram_ret_aon_addr),
+ .wdata_i (ram_ret_aon_wdata),
+ .wmask_i (ram_ret_aon_wmask),
+ .rdata_o (ram_ret_aon_rdata),
+ .rvalid_o (ram_ret_aon_rvalid),
+ .rerror_o (ram_ret_aon_rerror),
+ .raddr_o ( sram_ctrl_ret_aon_sram_scr_rsp.raddr ),
.cfg_i ( '0 )
);
- assign sram_ctrl_ret_sram_scr_rsp.rerror = ram_ret_rerror;
+ assign sram_ctrl_ret_aon_sram_scr_rsp.rerror = ram_ret_aon_rerror;
// host to flash communication
@@ -834,8 +834,8 @@
.ByteAccess(0),
.ErrOnWrite(1)
) u_tl_adapter_eflash (
- .clk_i (clkmgr_clocks.clk_main_infra),
- .rst_ni (rstmgr_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
+ .clk_i (clkmgr_aon_clocks.clk_main_infra),
+ .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
.tl_i (eflash_tl_req),
.tl_o (eflash_tl_rsp),
@@ -852,8 +852,8 @@
);
flash_phy u_flash_eflash (
- .clk_i (clkmgr_clocks.clk_main_infra),
- .rst_ni (rstmgr_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
+ .clk_i (clkmgr_aon_clocks.clk_main_infra),
+ .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
.host_req_i (flash_host_req),
.host_addr_i (flash_host_addr),
.host_req_rdy_o (flash_host_req_rdy),
@@ -900,8 +900,8 @@
.tl_o(uart0_tl_rsp),
// Clock and reset connections
- .clk_i (clkmgr_clocks.clk_io_div4_secure),
- .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_secure),
+ .rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
);
uart u_uart1 (
@@ -928,8 +928,8 @@
.tl_o(uart1_tl_rsp),
// Clock and reset connections
- .clk_i (clkmgr_clocks.clk_io_div4_secure),
- .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_secure),
+ .rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
);
uart u_uart2 (
@@ -956,8 +956,8 @@
.tl_o(uart2_tl_rsp),
// Clock and reset connections
- .clk_i (clkmgr_clocks.clk_io_div4_secure),
- .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_secure),
+ .rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
);
uart u_uart3 (
@@ -984,8 +984,8 @@
.tl_o(uart3_tl_rsp),
// Clock and reset connections
- .clk_i (clkmgr_clocks.clk_io_div4_secure),
- .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_secure),
+ .rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
);
gpio u_gpio (
@@ -1005,8 +1005,8 @@
.tl_o(gpio_tl_rsp),
// Clock and reset connections
- .clk_i (clkmgr_clocks.clk_io_div4_peri),
- .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
);
spi_device u_spi_device (
@@ -1034,8 +1034,8 @@
.scanmode_i (scanmode_i),
// Clock and reset connections
- .clk_i (clkmgr_clocks.clk_io_div4_peri),
- .rst_ni (rstmgr_resets.rst_spi_device_n[rstmgr_pkg::Domain0Sel])
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .rst_ni (rstmgr_aon_resets.rst_spi_device_n[rstmgr_pkg::Domain0Sel])
);
i2c u_i2c0 (
@@ -1073,8 +1073,8 @@
.tl_o(i2c0_tl_rsp),
// Clock and reset connections
- .clk_i (clkmgr_clocks.clk_io_div4_peri),
- .rst_ni (rstmgr_resets.rst_i2c0_n[rstmgr_pkg::Domain0Sel])
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .rst_ni (rstmgr_aon_resets.rst_i2c0_n[rstmgr_pkg::Domain0Sel])
);
i2c u_i2c1 (
@@ -1112,8 +1112,8 @@
.tl_o(i2c1_tl_rsp),
// Clock and reset connections
- .clk_i (clkmgr_clocks.clk_io_div4_peri),
- .rst_ni (rstmgr_resets.rst_i2c1_n[rstmgr_pkg::Domain0Sel])
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .rst_ni (rstmgr_aon_resets.rst_i2c1_n[rstmgr_pkg::Domain0Sel])
);
i2c u_i2c2 (
@@ -1151,8 +1151,8 @@
.tl_o(i2c2_tl_rsp),
// Clock and reset connections
- .clk_i (clkmgr_clocks.clk_io_div4_peri),
- .rst_ni (rstmgr_resets.rst_i2c2_n[rstmgr_pkg::Domain0Sel])
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .rst_ni (rstmgr_aon_resets.rst_i2c2_n[rstmgr_pkg::Domain0Sel])
);
pattgen u_pattgen (
@@ -1176,8 +1176,8 @@
.tl_o(pattgen_tl_rsp),
// Clock and reset connections
- .clk_i (clkmgr_clocks.clk_io_div4_peri),
- .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
);
rv_timer u_rv_timer (
@@ -1190,323 +1190,8 @@
.tl_o(rv_timer_tl_rsp),
// Clock and reset connections
- .clk_i (clkmgr_clocks.clk_io_div4_timers),
- .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
- );
-
- sensor_ctrl u_sensor_ctrl (
-
- // [0]: recov_as
- // [1]: recov_cg
- // [2]: recov_gd
- // [3]: recov_ts_hi
- // [4]: recov_ts_lo
- // [5]: recov_ls
- // [6]: recov_ot
- .alert_tx_o ( alert_tx[6:0] ),
- .alert_rx_i ( alert_rx[6:0] ),
-
- // Inter-module signals
- .ast_alert_i(sensor_ctrl_ast_alert_req_i),
- .ast_alert_o(sensor_ctrl_ast_alert_rsp_o),
- .ast_status_i(sensor_ctrl_ast_status_i),
- .tl_i(sensor_ctrl_tl_req),
- .tl_o(sensor_ctrl_tl_rsp),
-
- // Clock and reset connections
- .clk_i (clkmgr_clocks.clk_io_div4_secure),
- .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel])
- );
-
- otp_ctrl #(
- .RndCnstLfsrSeed(RndCnstOtpCtrlLfsrSeed),
- .RndCnstLfsrPerm(RndCnstOtpCtrlLfsrPerm)
- ) u_otp_ctrl (
-
- // Interrupt
- .intr_otp_operation_done_o (intr_otp_ctrl_otp_operation_done),
- .intr_otp_error_o (intr_otp_ctrl_otp_error),
-
- // [7]: fatal_macro_error
- // [8]: fatal_check_error
- .alert_tx_o ( alert_tx[8:7] ),
- .alert_rx_i ( alert_rx[8:7] ),
-
- // Inter-module signals
- .otp_ast_pwr_seq_o(otp_ctrl_otp_ast_pwr_seq_o),
- .otp_ast_pwr_seq_h_i(otp_ctrl_otp_ast_pwr_seq_h_i),
- .edn_o(),
- .edn_i(edn_pkg::EDN_RSP_DEFAULT),
- .pwr_otp_i(pwrmgr_pwr_otp_req),
- .pwr_otp_o(pwrmgr_pwr_otp_rsp),
- .lc_otp_program_i(lc_ctrl_lc_otp_program_req),
- .lc_otp_program_o(lc_ctrl_lc_otp_program_rsp),
- .lc_otp_token_i(lc_ctrl_lc_otp_token_req),
- .lc_otp_token_o(lc_ctrl_lc_otp_token_rsp),
- .otp_lc_data_o(otp_ctrl_otp_lc_data),
- .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
- .lc_creator_seed_sw_rw_en_i(lc_ctrl_lc_creator_seed_sw_rw_en),
- .lc_seed_hw_rd_en_i(lc_ctrl_lc_seed_hw_rd_en),
- .lc_dft_en_i(lc_ctrl_lc_dft_en),
- .lc_check_byp_en_i(lc_ctrl_lc_check_byp_en),
- .otp_keymgr_key_o(otp_ctrl_otp_keymgr_key),
- .flash_otp_key_i(flash_ctrl_otp_req),
- .flash_otp_key_o(flash_ctrl_otp_rsp),
- .sram_otp_key_i(otp_ctrl_sram_otp_key_req),
- .sram_otp_key_o(otp_ctrl_sram_otp_key_rsp),
- .otbn_otp_key_i('0),
- .otbn_otp_key_o(),
- .otp_hw_cfg_o(otp_ctrl_otp_hw_cfg),
- .tl_i(otp_ctrl_tl_req),
- .tl_o(otp_ctrl_tl_rsp),
-
- // Clock and reset connections
- .clk_i (clkmgr_clocks.clk_io_div4_timers),
- .clk_edn_i (clkmgr_clocks.clk_main_timers),
- .rst_ni (rstmgr_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
- .rst_edn_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
- );
-
- lc_ctrl #(
- .RndCnstLcKeymgrDivInvalid(RndCnstLcCtrlLcKeymgrDivInvalid),
- .RndCnstLcKeymgrDivTestDevRma(RndCnstLcCtrlLcKeymgrDivTestDevRma),
- .RndCnstLcKeymgrDivProduction(RndCnstLcCtrlLcKeymgrDivProduction)
- ) u_lc_ctrl (
-
- // [9]: fatal_prog_error
- // [10]: fatal_state_error
- .alert_tx_o ( alert_tx[10:9] ),
- .alert_rx_i ( alert_rx[10:9] ),
-
- // Inter-module signals
- .jtag_i(jtag_pkg::JTAG_REQ_DEFAULT),
- .jtag_o(),
- .esc_wipe_secrets_tx_i(alert_handler_esc_tx[1]),
- .esc_wipe_secrets_rx_o(alert_handler_esc_rx[1]),
- .esc_scrap_state_tx_i(alert_handler_esc_tx[2]),
- .esc_scrap_state_rx_o(alert_handler_esc_rx[2]),
- .pwr_lc_i(pwrmgr_pwr_lc_req),
- .pwr_lc_o(pwrmgr_pwr_lc_rsp),
- .otp_lc_data_i(otp_ctrl_otp_lc_data),
- .lc_otp_program_o(lc_ctrl_lc_otp_program_req),
- .lc_otp_program_i(lc_ctrl_lc_otp_program_rsp),
- .lc_otp_token_o(lc_ctrl_lc_otp_token_req),
- .lc_otp_token_i(lc_ctrl_lc_otp_token_rsp),
- .lc_dft_en_o(lc_ctrl_lc_dft_en),
- .lc_nvm_debug_en_o(lc_ctrl_lc_nvm_debug_en),
- .lc_hw_debug_en_o(lc_ctrl_lc_hw_debug_en),
- .lc_cpu_en_o(lc_ctrl_lc_cpu_en),
- .lc_keymgr_en_o(),
- .lc_escalate_en_o(lc_ctrl_lc_escalate_en),
- .lc_clk_byp_req_o(lc_ctrl_lc_clk_byp_req),
- .lc_clk_byp_ack_i(lc_ctrl_lc_clk_byp_ack),
- .lc_flash_rma_req_o(flash_ctrl_rma_req),
- .lc_flash_rma_seed_o(flash_ctrl_rma_seed),
- .lc_flash_rma_ack_i(flash_ctrl_rma_ack),
- .lc_check_byp_en_o(lc_ctrl_lc_check_byp_en),
- .lc_creator_seed_sw_rw_en_o(lc_ctrl_lc_creator_seed_sw_rw_en),
- .lc_owner_seed_sw_rw_en_o(lc_ctrl_lc_owner_seed_sw_rw_en),
- .lc_iso_part_sw_rd_en_o(lc_ctrl_lc_iso_part_sw_rd_en),
- .lc_iso_part_sw_wr_en_o(lc_ctrl_lc_iso_part_sw_wr_en),
- .lc_seed_hw_rd_en_o(lc_ctrl_lc_seed_hw_rd_en),
- .lc_keymgr_div_o(lc_ctrl_lc_keymgr_div),
- .otp_hw_cfg_i(otp_ctrl_otp_hw_cfg),
- .tl_i(lc_ctrl_tl_req),
- .tl_o(lc_ctrl_tl_rsp),
- .scanmode_i (scanmode_i),
-
- // Clock and reset connections
- .clk_i (clkmgr_clocks.clk_io_div4_timers),
- .rst_ni (rstmgr_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
- );
-
- alert_handler #(
- .RndCnstLfsrSeed(RndCnstAlertHandlerLfsrSeed),
- .RndCnstLfsrPerm(RndCnstAlertHandlerLfsrPerm)
- ) u_alert_handler (
-
- // Interrupt
- .intr_classa_o (intr_alert_handler_classa),
- .intr_classb_o (intr_alert_handler_classb),
- .intr_classc_o (intr_alert_handler_classc),
- .intr_classd_o (intr_alert_handler_classd),
-
- // Inter-module signals
- .crashdump_o(alert_handler_crashdump),
- .entropy_i( 1'b0),
- .esc_rx_i(alert_handler_esc_rx),
- .esc_tx_o(alert_handler_esc_tx),
- .tl_i(alert_handler_tl_req),
- .tl_o(alert_handler_tl_rsp),
- // alert signals
- .alert_rx_o ( alert_rx ),
- .alert_tx_i ( alert_tx ),
-
- // Clock and reset connections
- .clk_i (clkmgr_clocks.clk_io_div4_timers),
- .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
- );
-
- nmi_gen u_nmi_gen (
-
- // Interrupt
- .intr_esc0_o (intr_nmi_gen_esc0),
- .intr_esc1_o (intr_nmi_gen_esc1),
- .intr_esc2_o (intr_nmi_gen_esc2),
-
- // Inter-module signals
- .nmi_rst_req_o(pwrmgr_rstreqs),
- .esc_tx_i({3{prim_esc_pkg::ESC_TX_DEFAULT}}),
- .esc_rx_o(),
- .tl_i(nmi_gen_tl_req),
- .tl_o(nmi_gen_tl_rsp),
-
- // Clock and reset connections
- .clk_i (clkmgr_clocks.clk_io_div4_timers),
- .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
- );
-
- pwrmgr u_pwrmgr (
-
- // Interrupt
- .intr_wakeup_o (intr_pwrmgr_wakeup),
-
- // Inter-module signals
- .pwr_ast_o(pwrmgr_pwr_ast_req_o),
- .pwr_ast_i(pwrmgr_pwr_ast_rsp_i),
- .pwr_rst_o(pwrmgr_pwr_rst_req),
- .pwr_rst_i(pwrmgr_pwr_rst_rsp),
- .pwr_clk_o(pwrmgr_pwr_clk_req),
- .pwr_clk_i(pwrmgr_pwr_clk_rsp),
- .pwr_otp_o(pwrmgr_pwr_otp_req),
- .pwr_otp_i(pwrmgr_pwr_otp_rsp),
- .pwr_lc_o(pwrmgr_pwr_lc_req),
- .pwr_lc_i(pwrmgr_pwr_lc_rsp),
- .pwr_flash_o(pwrmgr_pwr_flash_req),
- .pwr_flash_i(pwrmgr_pwr_flash_rsp),
- .esc_rst_tx_i(alert_handler_esc_tx[3]),
- .esc_rst_rx_o(alert_handler_esc_rx[3]),
- .pwr_cpu_i(pwrmgr_pwr_cpu),
- .wakeups_i(pwrmgr_wakeups),
- .rstreqs_i(pwrmgr_rstreqs),
- .tl_i(pwrmgr_tl_req),
- .tl_o(pwrmgr_tl_rsp),
-
- // Clock and reset connections
- .clk_i (clkmgr_clocks.clk_io_div4_powerup),
- .clk_slow_i (clkmgr_clocks.clk_aon_powerup),
- .rst_ni (rstmgr_resets.rst_por_n[rstmgr_pkg::DomainAonSel]),
- .rst_slow_ni (rstmgr_resets.rst_por_aon_n[rstmgr_pkg::DomainAonSel])
- );
-
- rstmgr u_rstmgr (
-
- // Inter-module signals
- .pwr_i(pwrmgr_pwr_rst_req),
- .pwr_o(pwrmgr_pwr_rst_rsp),
- .resets_o(rstmgr_resets),
- .ast_i(rstmgr_ast_i),
- .cpu_i(rstmgr_cpu),
- .alert_dump_i(alert_handler_crashdump),
- .cpu_dump_i(rv_core_ibex_crashdump),
- .resets_ast_o(rsts_ast_o),
- .tl_i(rstmgr_tl_req),
- .tl_o(rstmgr_tl_rsp),
- .scanmode_i (scanmode_i),
- .scan_rst_ni (scan_rst_ni),
-
- // Clock and reset connections
- .clk_i (clkmgr_clocks.clk_io_div4_powerup),
- .clk_aon_i (clkmgr_clocks.clk_aon_powerup),
- .clk_main_i (clkmgr_clocks.clk_main_powerup),
- .clk_io_i (clkmgr_clocks.clk_io_powerup),
- .clk_usb_i (clkmgr_clocks.clk_usb_powerup),
- .clk_io_div2_i (clkmgr_clocks.clk_io_div2_powerup),
- .clk_io_div4_i (clkmgr_clocks.clk_io_div4_powerup),
- .rst_ni (rst_ni)
- );
-
- clkmgr u_clkmgr (
-
- // Inter-module signals
- .clocks_o(clkmgr_clocks),
- .ast_clk_bypass_ack_i(lc_ctrl_pkg::LC_TX_DEFAULT),
- .lc_clk_bypass_ack_o(lc_ctrl_lc_clk_byp_ack),
- .clk_main_i(clk_main_i),
- .clk_io_i(clk_io_i),
- .clk_usb_i(clk_usb_i),
- .clk_aon_i(clk_aon_i),
- .clocks_ast_o(clks_ast_o),
- .pwr_i(pwrmgr_pwr_clk_req),
- .pwr_o(pwrmgr_pwr_clk_rsp),
- .idle_i(clkmgr_idle),
- .tl_i(clkmgr_tl_req),
- .tl_o(clkmgr_tl_rsp),
- .scanmode_i (scanmode_i),
-
- // Clock and reset connections
- .clk_i (clkmgr_clocks.clk_io_div4_powerup),
- .rst_ni (rstmgr_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]),
- .rst_main_ni (rstmgr_resets.rst_por_n[rstmgr_pkg::DomainAonSel]),
- .rst_io_ni (rstmgr_resets.rst_por_io_n[rstmgr_pkg::DomainAonSel]),
- .rst_usb_ni (rstmgr_resets.rst_por_usb_n[rstmgr_pkg::DomainAonSel]),
- .rst_io_div2_ni (rstmgr_resets.rst_por_io_div2_n[rstmgr_pkg::DomainAonSel]),
- .rst_io_div4_ni (rstmgr_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel])
- );
-
- pinmux u_pinmux (
-
- // Inter-module signals
- .lc_pinmux_strap_i('0),
- .lc_pinmux_strap_o(),
- .dft_strap_test_o(),
- .io_pok_i({pinmux_pkg::NIOPokSignals{1'b1}}),
- .sleep_en_i(1'b0),
- .aon_wkup_req_o(pwrmgr_wakeups),
- .usb_wkup_req_o(),
- .usb_out_of_rst_i(usbdev_usb_out_of_rst),
- .usb_aon_wake_en_i(usbdev_usb_aon_wake_en),
- .usb_aon_wake_ack_i(usbdev_usb_aon_wake_ack),
- .usb_suspend_i(usbdev_usb_suspend),
- .usb_state_debug_o(pinmux_usb_state_debug),
- .tl_i(pinmux_tl_req),
- .tl_o(pinmux_tl_rsp),
-
- .periph_to_mio_i (mio_d2p ),
- .periph_to_mio_oe_i (mio_d2p_en ),
- .mio_to_periph_o (mio_p2d ),
-
- .mio_out_o,
- .mio_oe_o,
- .mio_in_i,
-
- .periph_to_dio_i (dio_d2p ),
- .periph_to_dio_oe_i (dio_d2p_en ),
- .dio_to_periph_o (dio_p2d ),
-
- .dio_out_o,
- .dio_oe_o,
- .dio_in_i,
-
- // Clock and reset connections
- .clk_i (clkmgr_clocks.clk_main_secure),
- .clk_aon_i (clkmgr_clocks.clk_aon_secure),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::DomainAonSel]),
- .rst_aon_ni (rstmgr_resets.rst_sys_aon_n[rstmgr_pkg::DomainAonSel])
- );
-
- padctrl u_padctrl (
-
- // Inter-module signals
- .tl_i(padctrl_tl_req),
- .tl_o(padctrl_tl_rsp),
-
- .mio_attr_o,
- .dio_attr_o,
-
- // Clock and reset connections
- .clk_i (clkmgr_clocks.clk_main_secure),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::DomainAonSel])
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_timers),
+ .rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
);
usbdev u_usbdev (
@@ -1561,23 +1246,338 @@
.usb_aon_wake_en_o(usbdev_usb_aon_wake_en),
.usb_aon_wake_ack_o(usbdev_usb_aon_wake_ack),
.usb_suspend_o(usbdev_usb_suspend),
- .usb_state_debug_i(pinmux_usb_state_debug),
+ .usb_state_debug_i(pinmux_aon_usb_state_debug),
.tl_i(usbdev_tl_req),
.tl_o(usbdev_tl_rsp),
// Clock and reset connections
- .clk_i (clkmgr_clocks.clk_io_div4_peri),
- .clk_aon_i (clkmgr_clocks.clk_aon_peri),
- .clk_usb_48mhz_i (clkmgr_clocks.clk_usb_peri),
- .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]),
- .rst_aon_ni (rstmgr_resets.rst_sys_aon_n[rstmgr_pkg::Domain0Sel]),
- .rst_usb_48mhz_ni (rstmgr_resets.rst_usb_n[rstmgr_pkg::Domain0Sel])
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .clk_aon_i (clkmgr_aon_clocks.clk_aon_peri),
+ .clk_usb_48mhz_i (clkmgr_aon_clocks.clk_usb_peri),
+ .rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]),
+ .rst_aon_ni (rstmgr_aon_resets.rst_sys_aon_n[rstmgr_pkg::Domain0Sel]),
+ .rst_usb_48mhz_ni (rstmgr_aon_resets.rst_usb_n[rstmgr_pkg::Domain0Sel])
+ );
+
+ otp_ctrl #(
+ .RndCnstLfsrSeed(RndCnstOtpCtrlLfsrSeed),
+ .RndCnstLfsrPerm(RndCnstOtpCtrlLfsrPerm)
+ ) u_otp_ctrl (
+
+ // Interrupt
+ .intr_otp_operation_done_o (intr_otp_ctrl_otp_operation_done),
+ .intr_otp_error_o (intr_otp_ctrl_otp_error),
+
+ // [0]: fatal_macro_error
+ // [1]: fatal_check_error
+ .alert_tx_o ( alert_tx[1:0] ),
+ .alert_rx_i ( alert_rx[1:0] ),
+
+ // Inter-module signals
+ .otp_ast_pwr_seq_o(otp_ctrl_otp_ast_pwr_seq_o),
+ .otp_ast_pwr_seq_h_i(otp_ctrl_otp_ast_pwr_seq_h_i),
+ .edn_o(),
+ .edn_i(edn_pkg::EDN_RSP_DEFAULT),
+ .pwr_otp_i(pwrmgr_aon_pwr_otp_req),
+ .pwr_otp_o(pwrmgr_aon_pwr_otp_rsp),
+ .lc_otp_program_i(lc_ctrl_lc_otp_program_req),
+ .lc_otp_program_o(lc_ctrl_lc_otp_program_rsp),
+ .lc_otp_token_i(lc_ctrl_lc_otp_token_req),
+ .lc_otp_token_o(lc_ctrl_lc_otp_token_rsp),
+ .otp_lc_data_o(otp_ctrl_otp_lc_data),
+ .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
+ .lc_creator_seed_sw_rw_en_i(lc_ctrl_lc_creator_seed_sw_rw_en),
+ .lc_seed_hw_rd_en_i(lc_ctrl_lc_seed_hw_rd_en),
+ .lc_dft_en_i(lc_ctrl_lc_dft_en),
+ .lc_check_byp_en_i(lc_ctrl_lc_check_byp_en),
+ .otp_keymgr_key_o(otp_ctrl_otp_keymgr_key),
+ .flash_otp_key_i(flash_ctrl_otp_req),
+ .flash_otp_key_o(flash_ctrl_otp_rsp),
+ .sram_otp_key_i(otp_ctrl_sram_otp_key_req),
+ .sram_otp_key_o(otp_ctrl_sram_otp_key_rsp),
+ .otbn_otp_key_i('0),
+ .otbn_otp_key_o(),
+ .otp_hw_cfg_o(otp_ctrl_otp_hw_cfg),
+ .tl_i(otp_ctrl_tl_req),
+ .tl_o(otp_ctrl_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_timers),
+ .clk_edn_i (clkmgr_aon_clocks.clk_main_timers),
+ .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
+ .rst_edn_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
+ );
+
+ lc_ctrl #(
+ .RndCnstLcKeymgrDivInvalid(RndCnstLcCtrlLcKeymgrDivInvalid),
+ .RndCnstLcKeymgrDivTestDevRma(RndCnstLcCtrlLcKeymgrDivTestDevRma),
+ .RndCnstLcKeymgrDivProduction(RndCnstLcCtrlLcKeymgrDivProduction)
+ ) u_lc_ctrl (
+
+ // [2]: fatal_prog_error
+ // [3]: fatal_state_error
+ .alert_tx_o ( alert_tx[3:2] ),
+ .alert_rx_i ( alert_rx[3:2] ),
+
+ // Inter-module signals
+ .jtag_i(jtag_pkg::JTAG_REQ_DEFAULT),
+ .jtag_o(),
+ .esc_wipe_secrets_tx_i(alert_handler_esc_tx[1]),
+ .esc_wipe_secrets_rx_o(alert_handler_esc_rx[1]),
+ .esc_scrap_state_tx_i(alert_handler_esc_tx[2]),
+ .esc_scrap_state_rx_o(alert_handler_esc_rx[2]),
+ .pwr_lc_i(pwrmgr_aon_pwr_lc_req),
+ .pwr_lc_o(pwrmgr_aon_pwr_lc_rsp),
+ .otp_lc_data_i(otp_ctrl_otp_lc_data),
+ .lc_otp_program_o(lc_ctrl_lc_otp_program_req),
+ .lc_otp_program_i(lc_ctrl_lc_otp_program_rsp),
+ .lc_otp_token_o(lc_ctrl_lc_otp_token_req),
+ .lc_otp_token_i(lc_ctrl_lc_otp_token_rsp),
+ .lc_dft_en_o(lc_ctrl_lc_dft_en),
+ .lc_nvm_debug_en_o(lc_ctrl_lc_nvm_debug_en),
+ .lc_hw_debug_en_o(lc_ctrl_lc_hw_debug_en),
+ .lc_cpu_en_o(lc_ctrl_lc_cpu_en),
+ .lc_keymgr_en_o(),
+ .lc_escalate_en_o(lc_ctrl_lc_escalate_en),
+ .lc_clk_byp_req_o(lc_ctrl_lc_clk_byp_req),
+ .lc_clk_byp_ack_i(lc_ctrl_lc_clk_byp_ack),
+ .lc_flash_rma_req_o(flash_ctrl_rma_req),
+ .lc_flash_rma_seed_o(flash_ctrl_rma_seed),
+ .lc_flash_rma_ack_i(flash_ctrl_rma_ack),
+ .lc_check_byp_en_o(lc_ctrl_lc_check_byp_en),
+ .lc_creator_seed_sw_rw_en_o(lc_ctrl_lc_creator_seed_sw_rw_en),
+ .lc_owner_seed_sw_rw_en_o(lc_ctrl_lc_owner_seed_sw_rw_en),
+ .lc_iso_part_sw_rd_en_o(lc_ctrl_lc_iso_part_sw_rd_en),
+ .lc_iso_part_sw_wr_en_o(lc_ctrl_lc_iso_part_sw_wr_en),
+ .lc_seed_hw_rd_en_o(lc_ctrl_lc_seed_hw_rd_en),
+ .lc_keymgr_div_o(lc_ctrl_lc_keymgr_div),
+ .otp_hw_cfg_i(otp_ctrl_otp_hw_cfg),
+ .tl_i(lc_ctrl_tl_req),
+ .tl_o(lc_ctrl_tl_rsp),
+ .scanmode_i (scanmode_i),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_timers),
+ .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
+ );
+
+ alert_handler #(
+ .RndCnstLfsrSeed(RndCnstAlertHandlerLfsrSeed),
+ .RndCnstLfsrPerm(RndCnstAlertHandlerLfsrPerm)
+ ) u_alert_handler (
+
+ // Interrupt
+ .intr_classa_o (intr_alert_handler_classa),
+ .intr_classb_o (intr_alert_handler_classb),
+ .intr_classc_o (intr_alert_handler_classc),
+ .intr_classd_o (intr_alert_handler_classd),
+
+ // Inter-module signals
+ .crashdump_o(alert_handler_crashdump),
+ .entropy_i( 1'b0),
+ .esc_rx_i(alert_handler_esc_rx),
+ .esc_tx_o(alert_handler_esc_tx),
+ .tl_i(alert_handler_tl_req),
+ .tl_o(alert_handler_tl_rsp),
+ // alert signals
+ .alert_rx_o ( alert_rx ),
+ .alert_tx_i ( alert_tx ),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_timers),
+ .rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
+ );
+
+ nmi_gen u_nmi_gen (
+
+ // Interrupt
+ .intr_esc0_o (intr_nmi_gen_esc0),
+ .intr_esc1_o (intr_nmi_gen_esc1),
+ .intr_esc2_o (intr_nmi_gen_esc2),
+
+ // Inter-module signals
+ .nmi_rst_req_o(pwrmgr_aon_rstreqs),
+ .esc_tx_i({3{prim_esc_pkg::ESC_TX_DEFAULT}}),
+ .esc_rx_o(),
+ .tl_i(nmi_gen_tl_req),
+ .tl_o(nmi_gen_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_timers),
+ .rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel])
+ );
+
+ pwrmgr u_pwrmgr_aon (
+
+ // Interrupt
+ .intr_wakeup_o (intr_pwrmgr_aon_wakeup),
+
+ // Inter-module signals
+ .pwr_ast_o(pwrmgr_ast_req_o),
+ .pwr_ast_i(pwrmgr_ast_rsp_i),
+ .pwr_rst_o(pwrmgr_aon_pwr_rst_req),
+ .pwr_rst_i(pwrmgr_aon_pwr_rst_rsp),
+ .pwr_clk_o(pwrmgr_aon_pwr_clk_req),
+ .pwr_clk_i(pwrmgr_aon_pwr_clk_rsp),
+ .pwr_otp_o(pwrmgr_aon_pwr_otp_req),
+ .pwr_otp_i(pwrmgr_aon_pwr_otp_rsp),
+ .pwr_lc_o(pwrmgr_aon_pwr_lc_req),
+ .pwr_lc_i(pwrmgr_aon_pwr_lc_rsp),
+ .pwr_flash_o(pwrmgr_aon_pwr_flash_req),
+ .pwr_flash_i(pwrmgr_aon_pwr_flash_rsp),
+ .esc_rst_tx_i(alert_handler_esc_tx[3]),
+ .esc_rst_rx_o(alert_handler_esc_rx[3]),
+ .pwr_cpu_i(pwrmgr_aon_pwr_cpu),
+ .wakeups_i(pwrmgr_aon_wakeups),
+ .rstreqs_i(pwrmgr_aon_rstreqs),
+ .tl_i(pwrmgr_aon_tl_req),
+ .tl_o(pwrmgr_aon_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup),
+ .clk_slow_i (clkmgr_aon_clocks.clk_aon_powerup),
+ .rst_ni (rstmgr_aon_resets.rst_por_n[rstmgr_pkg::DomainAonSel]),
+ .rst_slow_ni (rstmgr_aon_resets.rst_por_aon_n[rstmgr_pkg::DomainAonSel])
+ );
+
+ rstmgr u_rstmgr_aon (
+
+ // Inter-module signals
+ .pwr_i(pwrmgr_aon_pwr_rst_req),
+ .pwr_o(pwrmgr_aon_pwr_rst_rsp),
+ .resets_o(rstmgr_aon_resets),
+ .ast_i(rstmgr_ast_i),
+ .cpu_i(rstmgr_aon_cpu),
+ .alert_dump_i(alert_handler_crashdump),
+ .cpu_dump_i(rv_core_ibex_crashdump),
+ .resets_ast_o(rsts_ast_o),
+ .tl_i(rstmgr_aon_tl_req),
+ .tl_o(rstmgr_aon_tl_rsp),
+ .scanmode_i (scanmode_i),
+ .scan_rst_ni (scan_rst_ni),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup),
+ .clk_aon_i (clkmgr_aon_clocks.clk_aon_powerup),
+ .clk_main_i (clkmgr_aon_clocks.clk_main_powerup),
+ .clk_io_i (clkmgr_aon_clocks.clk_io_powerup),
+ .clk_usb_i (clkmgr_aon_clocks.clk_usb_powerup),
+ .clk_io_div2_i (clkmgr_aon_clocks.clk_io_div2_powerup),
+ .clk_io_div4_i (clkmgr_aon_clocks.clk_io_div4_powerup),
+ .rst_ni (rst_ni)
+ );
+
+ clkmgr u_clkmgr_aon (
+
+ // Inter-module signals
+ .clocks_o(clkmgr_aon_clocks),
+ .ast_clk_bypass_ack_i(lc_ctrl_pkg::LC_TX_DEFAULT),
+ .lc_clk_bypass_ack_o(lc_ctrl_lc_clk_byp_ack),
+ .clk_main_i(clk_main_i),
+ .clk_io_i(clk_io_i),
+ .clk_usb_i(clk_usb_i),
+ .clk_aon_i(clk_aon_i),
+ .clocks_ast_o(clks_ast_o),
+ .pwr_i(pwrmgr_aon_pwr_clk_req),
+ .pwr_o(pwrmgr_aon_pwr_clk_rsp),
+ .idle_i(clkmgr_aon_idle),
+ .tl_i(clkmgr_aon_tl_req),
+ .tl_o(clkmgr_aon_tl_rsp),
+ .scanmode_i (scanmode_i),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup),
+ .rst_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]),
+ .rst_main_ni (rstmgr_aon_resets.rst_por_n[rstmgr_pkg::DomainAonSel]),
+ .rst_io_ni (rstmgr_aon_resets.rst_por_io_n[rstmgr_pkg::DomainAonSel]),
+ .rst_usb_ni (rstmgr_aon_resets.rst_por_usb_n[rstmgr_pkg::DomainAonSel]),
+ .rst_io_div2_ni (rstmgr_aon_resets.rst_por_io_div2_n[rstmgr_pkg::DomainAonSel]),
+ .rst_io_div4_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel])
+ );
+
+ pinmux u_pinmux_aon (
+
+ // Inter-module signals
+ .lc_pinmux_strap_i('0),
+ .lc_pinmux_strap_o(),
+ .dft_strap_test_o(),
+ .io_pok_i({pinmux_pkg::NIOPokSignals{1'b1}}),
+ .sleep_en_i(1'b0),
+ .aon_wkup_req_o(pwrmgr_aon_wakeups),
+ .usb_wkup_req_o(),
+ .usb_out_of_rst_i(usbdev_usb_out_of_rst),
+ .usb_aon_wake_en_i(usbdev_usb_aon_wake_en),
+ .usb_aon_wake_ack_i(usbdev_usb_aon_wake_ack),
+ .usb_suspend_i(usbdev_usb_suspend),
+ .usb_state_debug_o(pinmux_aon_usb_state_debug),
+ .tl_i(pinmux_aon_tl_req),
+ .tl_o(pinmux_aon_tl_rsp),
+
+ .periph_to_mio_i (mio_d2p ),
+ .periph_to_mio_oe_i (mio_d2p_en ),
+ .mio_to_periph_o (mio_p2d ),
+
+ .mio_out_o,
+ .mio_oe_o,
+ .mio_in_i,
+
+ .periph_to_dio_i (dio_d2p ),
+ .periph_to_dio_oe_i (dio_d2p_en ),
+ .dio_to_periph_o (dio_p2d ),
+
+ .dio_out_o,
+ .dio_oe_o,
+ .dio_in_i,
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_secure),
+ .clk_aon_i (clkmgr_aon_clocks.clk_aon_secure),
+ .rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]),
+ .rst_aon_ni (rstmgr_aon_resets.rst_sys_aon_n[rstmgr_pkg::DomainAonSel])
+ );
+
+ padctrl u_padctrl_aon (
+
+ // Inter-module signals
+ .tl_i(padctrl_aon_tl_req),
+ .tl_o(padctrl_aon_tl_rsp),
+
+ .mio_attr_o,
+ .dio_attr_o,
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_secure),
+ .rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel])
+ );
+
+ sensor_ctrl u_sensor_ctrl_aon (
+
+ // [4]: recov_as
+ // [5]: recov_cg
+ // [6]: recov_gd
+ // [7]: recov_ts_hi
+ // [8]: recov_ts_lo
+ // [9]: recov_ls
+ // [10]: recov_ot
+ .alert_tx_o ( alert_tx[10:4] ),
+ .alert_rx_i ( alert_rx[10:4] ),
+
+ // Inter-module signals
+ .ast_alert_i(sensor_ctrl_ast_alert_req_i),
+ .ast_alert_o(sensor_ctrl_ast_alert_rsp_o),
+ .ast_status_i(sensor_ctrl_ast_status_i),
+ .tl_i(sensor_ctrl_aon_tl_req),
+ .tl_o(sensor_ctrl_aon_tl_rsp),
+
+ // Clock and reset connections
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_secure),
+ .rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel])
);
sram_ctrl #(
- .RndCnstSramKey(RndCnstSramCtrlRetSramKey),
- .RndCnstSramNonce(RndCnstSramCtrlRetSramNonce)
- ) u_sram_ctrl_ret (
+ .RndCnstSramKey(RndCnstSramCtrlRetAonSramKey),
+ .RndCnstSramNonce(RndCnstSramCtrlRetAonSramNonce)
+ ) u_sram_ctrl_ret_aon (
// [11]: fatal_parity_error
.alert_tx_o ( alert_tx[11:11] ),
@@ -1586,17 +1586,17 @@
// Inter-module signals
.sram_otp_key_o(otp_ctrl_sram_otp_key_req[1]),
.sram_otp_key_i(otp_ctrl_sram_otp_key_rsp[1]),
- .sram_scr_o(sram_ctrl_ret_sram_scr_req),
- .sram_scr_i(sram_ctrl_ret_sram_scr_rsp),
+ .sram_scr_o(sram_ctrl_ret_aon_sram_scr_req),
+ .sram_scr_i(sram_ctrl_ret_aon_sram_scr_rsp),
.lc_escalate_en_i(lc_ctrl_lc_escalate_en),
- .tl_i(sram_ctrl_ret_tl_req),
- .tl_o(sram_ctrl_ret_tl_rsp),
+ .tl_i(sram_ctrl_ret_aon_tl_req),
+ .tl_o(sram_ctrl_ret_aon_tl_rsp),
// Clock and reset connections
- .clk_i (clkmgr_clocks.clk_io_div4_peri),
- .clk_otp_i (clkmgr_clocks.clk_io_div4_peri),
- .rst_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]),
- .rst_otp_ni (rstmgr_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel])
+ .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_peri),
+ .rst_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel]),
+ .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel])
);
flash_ctrl #(
@@ -1632,17 +1632,17 @@
.rma_req_i(flash_ctrl_rma_req),
.rma_ack_o(flash_ctrl_rma_ack),
.rma_seed_i(flash_ctrl_rma_seed),
- .pwrmgr_i(pwrmgr_pwr_flash_req),
- .pwrmgr_o(pwrmgr_pwr_flash_rsp),
+ .pwrmgr_i(pwrmgr_aon_pwr_flash_req),
+ .pwrmgr_o(pwrmgr_aon_pwr_flash_rsp),
.keymgr_o(flash_ctrl_keymgr),
.tl_i(flash_ctrl_tl_req),
.tl_o(flash_ctrl_tl_rsp),
// Clock and reset connections
- .clk_i (clkmgr_clocks.clk_main_infra),
- .clk_otp_i (clkmgr_clocks.clk_io_div4_infra),
- .rst_ni (rstmgr_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
- .rst_otp_ni (rstmgr_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
+ .clk_i (clkmgr_aon_clocks.clk_main_infra),
+ .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_infra),
+ .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
+ .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
);
rv_plic u_rv_plic (
@@ -1657,8 +1657,8 @@
.msip_o (msip),
// Clock and reset connections
- .clk_i (clkmgr_clocks.clk_main_secure),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
+ .clk_i (clkmgr_aon_clocks.clk_main_secure),
+ .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
aes #(
@@ -1680,13 +1680,13 @@
.alert_rx_i ( alert_rx[16:15] ),
// Inter-module signals
- .idle_o(clkmgr_idle[0]),
+ .idle_o(clkmgr_aon_idle[0]),
.tl_i(aes_tl_req),
.tl_o(aes_tl_rsp),
// Clock and reset connections
- .clk_i (clkmgr_clocks.clk_main_aes),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
+ .clk_i (clkmgr_aon_clocks.clk_main_aes),
+ .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
hmac u_hmac (
@@ -1697,13 +1697,13 @@
.intr_hmac_err_o (intr_hmac_hmac_err),
// Inter-module signals
- .idle_o(clkmgr_idle[1]),
+ .idle_o(clkmgr_aon_idle[1]),
.tl_i(hmac_tl_req),
.tl_o(hmac_tl_rsp),
// Clock and reset connections
- .clk_i (clkmgr_clocks.clk_main_hmac),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
+ .clk_i (clkmgr_aon_clocks.clk_main_hmac),
+ .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
kmac #(
@@ -1722,15 +1722,15 @@
.keymgr_kdf_o(keymgr_kmac_data_rsp),
.entropy_o(),
.entropy_i(edn_pkg::EDN_RSP_DEFAULT),
- .idle_o(clkmgr_idle[2]),
+ .idle_o(clkmgr_aon_idle[2]),
.tl_i(kmac_tl_req),
.tl_o(kmac_tl_rsp),
// Clock and reset connections
- .clk_i (clkmgr_clocks.clk_main_kmac),
- .clk_edn_i (clkmgr_clocks.clk_main_kmac),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
- .rst_edn_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
+ .clk_i (clkmgr_aon_clocks.clk_main_kmac),
+ .clk_edn_i (clkmgr_aon_clocks.clk_main_kmac),
+ .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
+ .rst_edn_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
keymgr #(
@@ -1774,10 +1774,10 @@
.tl_o(keymgr_tl_rsp),
// Clock and reset connections
- .clk_i (clkmgr_clocks.clk_main_secure),
- .clk_edn_i (clkmgr_clocks.clk_main_secure),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
- .rst_edn_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
+ .clk_i (clkmgr_aon_clocks.clk_main_secure),
+ .clk_edn_i (clkmgr_aon_clocks.clk_main_secure),
+ .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
+ .rst_edn_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
csrng #(
@@ -1801,8 +1801,8 @@
.tl_o(csrng_tl_rsp),
// Clock and reset connections
- .clk_i (clkmgr_clocks.clk_main_secure),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
+ .clk_i (clkmgr_aon_clocks.clk_main_secure),
+ .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
entropy_src u_entropy_src (
@@ -1828,8 +1828,8 @@
.tl_o(entropy_src_tl_rsp),
// Clock and reset connections
- .clk_i (clkmgr_clocks.clk_main_secure),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
+ .clk_i (clkmgr_aon_clocks.clk_main_secure),
+ .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
edn u_edn0 (
@@ -1847,8 +1847,8 @@
.tl_o(edn0_tl_rsp),
// Clock and reset connections
- .clk_i (clkmgr_clocks.clk_main_secure),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
+ .clk_i (clkmgr_aon_clocks.clk_main_secure),
+ .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
edn u_edn1 (
@@ -1866,8 +1866,8 @@
.tl_o(edn1_tl_rsp),
// Clock and reset connections
- .clk_i (clkmgr_clocks.clk_main_secure),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
+ .clk_i (clkmgr_aon_clocks.clk_main_secure),
+ .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
sram_ctrl #(
@@ -1889,10 +1889,10 @@
.tl_o(sram_ctrl_main_tl_rsp),
// Clock and reset connections
- .clk_i (clkmgr_clocks.clk_main_secure),
- .clk_otp_i (clkmgr_clocks.clk_io_div4_secure),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
- .rst_otp_ni (rstmgr_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
+ .clk_i (clkmgr_aon_clocks.clk_main_secure),
+ .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_secure),
+ .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
+ .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
);
otbn #(
@@ -1908,13 +1908,13 @@
.alert_rx_i ( alert_rx[22:21] ),
// Inter-module signals
- .idle_o(clkmgr_idle[3]),
+ .idle_o(clkmgr_aon_idle[3]),
.tl_i(otbn_tl_req),
.tl_o(otbn_tl_rsp),
// Clock and reset connections
- .clk_i (clkmgr_clocks.clk_main_otbn),
- .rst_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
+ .clk_i (clkmgr_aon_clocks.clk_main_otbn),
+ .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel])
);
// interrupt assignments
@@ -1937,7 +1937,7 @@
intr_kmac_kmac_done,
intr_keymgr_op_done,
intr_otbn_done,
- intr_pwrmgr_wakeup,
+ intr_pwrmgr_aon_wakeup,
intr_usbdev_link_out_err,
intr_usbdev_connected,
intr_usbdev_frame,
@@ -2064,10 +2064,10 @@
// TL-UL Crossbar
xbar_main u_xbar_main (
- .clk_main_i (clkmgr_clocks.clk_main_infra),
- .clk_fixed_i (clkmgr_clocks.clk_io_div4_infra),
- .rst_main_ni (rstmgr_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
- .rst_fixed_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]),
+ .clk_main_i (clkmgr_aon_clocks.clk_main_infra),
+ .clk_fixed_i (clkmgr_aon_clocks.clk_io_div4_infra),
+ .rst_main_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
+ .rst_fixed_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]),
// port: tl_corei
.tl_corei_i(main_tl_corei_req),
@@ -2137,14 +2137,6 @@
.tl_rv_plic_o(rv_plic_tl_req),
.tl_rv_plic_i(rv_plic_tl_rsp),
- // port: tl_pinmux
- .tl_pinmux_o(pinmux_tl_req),
- .tl_pinmux_i(pinmux_tl_rsp),
-
- // port: tl_padctrl
- .tl_padctrl_o(padctrl_tl_req),
- .tl_padctrl_i(padctrl_tl_rsp),
-
// port: tl_otbn
.tl_otbn_o(otbn_tl_req),
.tl_otbn_i(otbn_tl_rsp),
@@ -2161,8 +2153,8 @@
.scanmode_i
);
xbar_peri u_xbar_peri (
- .clk_peri_i (clkmgr_clocks.clk_io_div4_infra),
- .rst_peri_ni (rstmgr_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]),
+ .clk_peri_i (clkmgr_aon_clocks.clk_io_div4_infra),
+ .rst_peri_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::Domain0Sel]),
// port: tl_main
.tl_main_i(main_tl_peri_req),
@@ -2216,21 +2208,29 @@
.tl_usbdev_o(usbdev_tl_req),
.tl_usbdev_i(usbdev_tl_rsp),
- // port: tl_pwrmgr
- .tl_pwrmgr_o(pwrmgr_tl_req),
- .tl_pwrmgr_i(pwrmgr_tl_rsp),
+ // port: tl_pwrmgr_aon
+ .tl_pwrmgr_aon_o(pwrmgr_aon_tl_req),
+ .tl_pwrmgr_aon_i(pwrmgr_aon_tl_rsp),
- // port: tl_rstmgr
- .tl_rstmgr_o(rstmgr_tl_req),
- .tl_rstmgr_i(rstmgr_tl_rsp),
+ // port: tl_rstmgr_aon
+ .tl_rstmgr_aon_o(rstmgr_aon_tl_req),
+ .tl_rstmgr_aon_i(rstmgr_aon_tl_rsp),
- // port: tl_clkmgr
- .tl_clkmgr_o(clkmgr_tl_req),
- .tl_clkmgr_i(clkmgr_tl_rsp),
+ // port: tl_clkmgr_aon
+ .tl_clkmgr_aon_o(clkmgr_aon_tl_req),
+ .tl_clkmgr_aon_i(clkmgr_aon_tl_rsp),
- // port: tl_ram_ret
- .tl_ram_ret_o(ram_ret_tl_req),
- .tl_ram_ret_i(ram_ret_tl_rsp),
+ // port: tl_pinmux_aon
+ .tl_pinmux_aon_o(pinmux_aon_tl_req),
+ .tl_pinmux_aon_i(pinmux_aon_tl_rsp),
+
+ // port: tl_padctrl_aon
+ .tl_padctrl_aon_o(padctrl_aon_tl_req),
+ .tl_padctrl_aon_i(padctrl_aon_tl_rsp),
+
+ // port: tl_ram_ret_aon
+ .tl_ram_ret_aon_o(ram_ret_aon_tl_req),
+ .tl_ram_ret_aon_i(ram_ret_aon_tl_rsp),
// port: tl_otp_ctrl
.tl_otp_ctrl_o(otp_ctrl_tl_req),
@@ -2240,17 +2240,17 @@
.tl_lc_ctrl_o(lc_ctrl_tl_req),
.tl_lc_ctrl_i(lc_ctrl_tl_rsp),
- // port: tl_sensor_ctrl
- .tl_sensor_ctrl_o(sensor_ctrl_tl_req),
- .tl_sensor_ctrl_i(sensor_ctrl_tl_rsp),
+ // port: tl_sensor_ctrl_aon
+ .tl_sensor_ctrl_aon_o(sensor_ctrl_aon_tl_req),
+ .tl_sensor_ctrl_aon_i(sensor_ctrl_aon_tl_rsp),
// port: tl_alert_handler
.tl_alert_handler_o(alert_handler_tl_req),
.tl_alert_handler_i(alert_handler_tl_rsp),
- // port: tl_sram_ctrl_ret
- .tl_sram_ctrl_ret_o(sram_ctrl_ret_tl_req),
- .tl_sram_ctrl_ret_i(sram_ctrl_ret_tl_rsp),
+ // port: tl_sram_ctrl_ret_aon
+ .tl_sram_ctrl_ret_aon_o(sram_ctrl_ret_aon_tl_req),
+ .tl_sram_ctrl_ret_aon_i(sram_ctrl_ret_aon_tl_rsp),
// port: tl_nmi_gen
.tl_nmi_gen_o(nmi_gen_tl_req),
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
index 8d872c3..0ef5587 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
@@ -122,14 +122,14 @@
parameter int unsigned TOP_EARLGREY_RV_TIMER_SIZE_BYTES = 32'h1000;
/**
- * Peripheral base address for sensor_ctrl in top earlgrey.
+ * Peripheral base address for usbdev in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR = 32'h40110000;
+ parameter int unsigned TOP_EARLGREY_USBDEV_BASE_ADDR = 32'h40110000;
/**
- * Peripheral size in bytes for sensor_ctrl in top earlgrey.
+ * Peripheral size in bytes for usbdev in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_SENSOR_CTRL_SIZE_BYTES = 32'h1000;
+ parameter int unsigned TOP_EARLGREY_USBDEV_SIZE_BYTES = 32'h1000;
/**
* Peripheral base address for otp_ctrl in top earlgrey.
@@ -172,74 +172,74 @@
parameter int unsigned TOP_EARLGREY_NMI_GEN_SIZE_BYTES = 32'h1000;
/**
- * Peripheral base address for pwrmgr in top earlgrey.
+ * Peripheral base address for pwrmgr_aon in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_PWRMGR_BASE_ADDR = 32'h40400000;
+ parameter int unsigned TOP_EARLGREY_PWRMGR_AON_BASE_ADDR = 32'h40400000;
/**
- * Peripheral size in bytes for pwrmgr in top earlgrey.
+ * Peripheral size in bytes for pwrmgr_aon in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_PWRMGR_SIZE_BYTES = 32'h1000;
+ parameter int unsigned TOP_EARLGREY_PWRMGR_AON_SIZE_BYTES = 32'h1000;
/**
- * Peripheral base address for rstmgr in top earlgrey.
+ * Peripheral base address for rstmgr_aon in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_RSTMGR_BASE_ADDR = 32'h40410000;
+ parameter int unsigned TOP_EARLGREY_RSTMGR_AON_BASE_ADDR = 32'h40410000;
/**
- * Peripheral size in bytes for rstmgr in top earlgrey.
+ * Peripheral size in bytes for rstmgr_aon in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_RSTMGR_SIZE_BYTES = 32'h1000;
+ parameter int unsigned TOP_EARLGREY_RSTMGR_AON_SIZE_BYTES = 32'h1000;
/**
- * Peripheral base address for clkmgr in top earlgrey.
+ * Peripheral base address for clkmgr_aon in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_CLKMGR_BASE_ADDR = 32'h40420000;
+ parameter int unsigned TOP_EARLGREY_CLKMGR_AON_BASE_ADDR = 32'h40420000;
/**
- * Peripheral size in bytes for clkmgr in top earlgrey.
+ * Peripheral size in bytes for clkmgr_aon in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_CLKMGR_SIZE_BYTES = 32'h1000;
+ parameter int unsigned TOP_EARLGREY_CLKMGR_AON_SIZE_BYTES = 32'h1000;
/**
- * Peripheral base address for pinmux in top earlgrey.
+ * Peripheral base address for pinmux_aon in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_PINMUX_BASE_ADDR = 32'h40460000;
+ parameter int unsigned TOP_EARLGREY_PINMUX_AON_BASE_ADDR = 32'h40460000;
/**
- * Peripheral size in bytes for pinmux in top earlgrey.
+ * Peripheral size in bytes for pinmux_aon in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_PINMUX_SIZE_BYTES = 32'h1000;
+ parameter int unsigned TOP_EARLGREY_PINMUX_AON_SIZE_BYTES = 32'h1000;
/**
- * Peripheral base address for padctrl in top earlgrey.
+ * Peripheral base address for padctrl_aon in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_PADCTRL_BASE_ADDR = 32'h40470000;
+ parameter int unsigned TOP_EARLGREY_PADCTRL_AON_BASE_ADDR = 32'h40470000;
/**
- * Peripheral size in bytes for padctrl in top earlgrey.
+ * Peripheral size in bytes for padctrl_aon in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_PADCTRL_SIZE_BYTES = 32'h1000;
+ parameter int unsigned TOP_EARLGREY_PADCTRL_AON_SIZE_BYTES = 32'h1000;
/**
- * Peripheral base address for usbdev in top earlgrey.
+ * Peripheral base address for sensor_ctrl_aon in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_USBDEV_BASE_ADDR = 32'h40500000;
+ parameter int unsigned TOP_EARLGREY_SENSOR_CTRL_AON_BASE_ADDR = 32'h40500000;
/**
- * Peripheral size in bytes for usbdev in top earlgrey.
+ * Peripheral size in bytes for sensor_ctrl_aon in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_USBDEV_SIZE_BYTES = 32'h1000;
+ parameter int unsigned TOP_EARLGREY_SENSOR_CTRL_AON_SIZE_BYTES = 32'h1000;
/**
- * Peripheral base address for sram_ctrl_ret in top earlgrey.
+ * Peripheral base address for sram_ctrl_ret_aon in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_SRAM_CTRL_RET_BASE_ADDR = 32'h40510000;
+ parameter int unsigned TOP_EARLGREY_SRAM_CTRL_RET_AON_BASE_ADDR = 32'h40510000;
/**
- * Peripheral size in bytes for sram_ctrl_ret in top earlgrey.
+ * Peripheral size in bytes for sram_ctrl_ret_aon in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_SRAM_CTRL_RET_SIZE_BYTES = 32'h1000;
+ parameter int unsigned TOP_EARLGREY_SRAM_CTRL_RET_AON_SIZE_BYTES = 32'h1000;
/**
* Peripheral base address for flash_ctrl in top earlgrey.
@@ -382,14 +382,14 @@
parameter int unsigned TOP_EARLGREY_RAM_MAIN_SIZE_BYTES = 32'h20000;
/**
- * Memory base address for ram_ret in top earlgrey.
+ * Memory base address for ram_ret_aon in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_RAM_RET_BASE_ADDR = 32'h40520000;
+ parameter int unsigned TOP_EARLGREY_RAM_RET_AON_BASE_ADDR = 32'h40520000;
/**
- * Memory size for ram_ret in top earlgrey.
+ * Memory size for ram_ret_aon in top earlgrey.
*/
- parameter int unsigned TOP_EARLGREY_RAM_RET_SIZE_BYTES = 32'h1000;
+ parameter int unsigned TOP_EARLGREY_RAM_RET_AON_SIZE_BYTES = 32'h1000;
/**
* Memory base address for eflash in top earlgrey.
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_rnd_cnst_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_rnd_cnst_pkg.sv
index 7769690..8649055 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_rnd_cnst_pkg.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_rnd_cnst_pkg.sv
@@ -58,15 +58,15 @@
};
////////////////////////////////////////////
- // sram_ctrl_ret
+ // sram_ctrl_ret_aon
////////////////////////////////////////////
// Compile-time random reset value for SRAM scrambling key.
- parameter otp_ctrl_pkg::sram_key_t RndCnstSramCtrlRetSramKey = {
+ parameter otp_ctrl_pkg::sram_key_t RndCnstSramCtrlRetAonSramKey = {
128'h83D0550B80E84EB1F4C3471C5DEF7861
};
// Compile-time random reset value for SRAM scrambling nonce.
- parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramCtrlRetSramNonce = {
+ parameter otp_ctrl_pkg::sram_nonce_t RndCnstSramCtrlRetAonSramNonce = {
64'h2D73930D4CAC3785
};
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.c b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
index bb96cdf..ac78378 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.c
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.c
@@ -165,7 +165,7 @@
[kTopEarlgreyPlicIrqIdUsbdevFrame] = kTopEarlgreyPlicPeripheralUsbdev,
[kTopEarlgreyPlicIrqIdUsbdevConnected] = kTopEarlgreyPlicPeripheralUsbdev,
[kTopEarlgreyPlicIrqIdUsbdevLinkOutErr] = kTopEarlgreyPlicPeripheralUsbdev,
- [kTopEarlgreyPlicIrqIdPwrmgrWakeup] = kTopEarlgreyPlicPeripheralPwrmgr,
+ [kTopEarlgreyPlicIrqIdPwrmgrAonWakeup] = kTopEarlgreyPlicPeripheralPwrmgrAon,
[kTopEarlgreyPlicIrqIdOtbnDone] = kTopEarlgreyPlicPeripheralOtbn,
[kTopEarlgreyPlicIrqIdKeymgrOpDone] = kTopEarlgreyPlicPeripheralKeymgr,
[kTopEarlgreyPlicIrqIdKmacKmacDone] = kTopEarlgreyPlicPeripheralKmac,
@@ -199,13 +199,13 @@
[kTopEarlgreyAlertIdAesFatalFault] = kTopEarlgreyAlertPeripheralAes,
[kTopEarlgreyAlertIdOtbnFatal] = kTopEarlgreyAlertPeripheralOtbn,
[kTopEarlgreyAlertIdOtbnRecov] = kTopEarlgreyAlertPeripheralOtbn,
- [kTopEarlgreyAlertIdSensorCtrlRecovAs] = kTopEarlgreyAlertPeripheralSensorCtrl,
- [kTopEarlgreyAlertIdSensorCtrlRecovCg] = kTopEarlgreyAlertPeripheralSensorCtrl,
- [kTopEarlgreyAlertIdSensorCtrlRecovGd] = kTopEarlgreyAlertPeripheralSensorCtrl,
- [kTopEarlgreyAlertIdSensorCtrlRecovTsHi] = kTopEarlgreyAlertPeripheralSensorCtrl,
- [kTopEarlgreyAlertIdSensorCtrlRecovTsLo] = kTopEarlgreyAlertPeripheralSensorCtrl,
- [kTopEarlgreyAlertIdSensorCtrlRecovLs] = kTopEarlgreyAlertPeripheralSensorCtrl,
- [kTopEarlgreyAlertIdSensorCtrlRecovOt] = kTopEarlgreyAlertPeripheralSensorCtrl,
+ [kTopEarlgreyAlertIdSensorCtrlAonRecovAs] = kTopEarlgreyAlertPeripheralSensorCtrlAon,
+ [kTopEarlgreyAlertIdSensorCtrlAonRecovCg] = kTopEarlgreyAlertPeripheralSensorCtrlAon,
+ [kTopEarlgreyAlertIdSensorCtrlAonRecovGd] = kTopEarlgreyAlertPeripheralSensorCtrlAon,
+ [kTopEarlgreyAlertIdSensorCtrlAonRecovTsHi] = kTopEarlgreyAlertPeripheralSensorCtrlAon,
+ [kTopEarlgreyAlertIdSensorCtrlAonRecovTsLo] = kTopEarlgreyAlertPeripheralSensorCtrlAon,
+ [kTopEarlgreyAlertIdSensorCtrlAonRecovLs] = kTopEarlgreyAlertPeripheralSensorCtrlAon,
+ [kTopEarlgreyAlertIdSensorCtrlAonRecovOt] = kTopEarlgreyAlertPeripheralSensorCtrlAon,
[kTopEarlgreyAlertIdKeymgrFatalFaultErr] = kTopEarlgreyAlertPeripheralKeymgr,
[kTopEarlgreyAlertIdKeymgrRecovOperationErr] = kTopEarlgreyAlertPeripheralKeymgr,
[kTopEarlgreyAlertIdOtpCtrlFatalMacroError] = kTopEarlgreyAlertPeripheralOtpCtrl,
@@ -214,7 +214,7 @@
[kTopEarlgreyAlertIdLcCtrlFatalStateError] = kTopEarlgreyAlertPeripheralLcCtrl,
[kTopEarlgreyAlertIdEntropySrcRecovAlertCountMet] = kTopEarlgreyAlertPeripheralEntropySrc,
[kTopEarlgreyAlertIdSramCtrlMainFatalParityError] = kTopEarlgreyAlertPeripheralSramCtrlMain,
- [kTopEarlgreyAlertIdSramCtrlRetFatalParityError] = kTopEarlgreyAlertPeripheralSramCtrlRet,
+ [kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError] = kTopEarlgreyAlertPeripheralSramCtrlRetAon,
[kTopEarlgreyAlertIdFlashCtrlRecovErr] = kTopEarlgreyAlertPeripheralFlashCtrl,
[kTopEarlgreyAlertIdFlashCtrlRecovMpErr] = kTopEarlgreyAlertPeripheralFlashCtrl,
[kTopEarlgreyAlertIdFlashCtrlRecovEccErr] = kTopEarlgreyAlertPeripheralFlashCtrl,
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index 9bd5250..c918e74 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -224,22 +224,22 @@
#define TOP_EARLGREY_RV_TIMER_SIZE_BYTES 0x1000u
/**
- * Peripheral base address for sensor_ctrl in top earlgrey.
+ * Peripheral base address for usbdev in top earlgrey.
*
* This should be used with #mmio_region_from_addr to access the memory-mapped
* registers associated with the peripheral (usually via a DIF).
*/
-#define TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR 0x40110000u
+#define TOP_EARLGREY_USBDEV_BASE_ADDR 0x40110000u
/**
- * Peripheral size for sensor_ctrl in top earlgrey.
+ * Peripheral size for usbdev in top earlgrey.
*
* This is the size (in bytes) of the peripheral's reserved memory area. All
* memory-mapped registers associated with this peripheral should have an
- * address between #TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR and
- * `TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR + TOP_EARLGREY_SENSOR_CTRL_SIZE_BYTES`.
+ * address between #TOP_EARLGREY_USBDEV_BASE_ADDR and
+ * `TOP_EARLGREY_USBDEV_BASE_ADDR + TOP_EARLGREY_USBDEV_SIZE_BYTES`.
*/
-#define TOP_EARLGREY_SENSOR_CTRL_SIZE_BYTES 0x1000u
+#define TOP_EARLGREY_USBDEV_SIZE_BYTES 0x1000u
/**
* Peripheral base address for otp_ctrl in top earlgrey.
@@ -314,130 +314,130 @@
#define TOP_EARLGREY_NMI_GEN_SIZE_BYTES 0x1000u
/**
- * Peripheral base address for pwrmgr in top earlgrey.
+ * Peripheral base address for pwrmgr_aon in top earlgrey.
*
* This should be used with #mmio_region_from_addr to access the memory-mapped
* registers associated with the peripheral (usually via a DIF).
*/
-#define TOP_EARLGREY_PWRMGR_BASE_ADDR 0x40400000u
+#define TOP_EARLGREY_PWRMGR_AON_BASE_ADDR 0x40400000u
/**
- * Peripheral size for pwrmgr in top earlgrey.
+ * Peripheral size for pwrmgr_aon in top earlgrey.
*
* This is the size (in bytes) of the peripheral's reserved memory area. All
* memory-mapped registers associated with this peripheral should have an
- * address between #TOP_EARLGREY_PWRMGR_BASE_ADDR and
- * `TOP_EARLGREY_PWRMGR_BASE_ADDR + TOP_EARLGREY_PWRMGR_SIZE_BYTES`.
+ * address between #TOP_EARLGREY_PWRMGR_AON_BASE_ADDR and
+ * `TOP_EARLGREY_PWRMGR_AON_BASE_ADDR + TOP_EARLGREY_PWRMGR_AON_SIZE_BYTES`.
*/
-#define TOP_EARLGREY_PWRMGR_SIZE_BYTES 0x1000u
+#define TOP_EARLGREY_PWRMGR_AON_SIZE_BYTES 0x1000u
/**
- * Peripheral base address for rstmgr in top earlgrey.
+ * Peripheral base address for rstmgr_aon in top earlgrey.
*
* This should be used with #mmio_region_from_addr to access the memory-mapped
* registers associated with the peripheral (usually via a DIF).
*/
-#define TOP_EARLGREY_RSTMGR_BASE_ADDR 0x40410000u
+#define TOP_EARLGREY_RSTMGR_AON_BASE_ADDR 0x40410000u
/**
- * Peripheral size for rstmgr in top earlgrey.
+ * Peripheral size for rstmgr_aon in top earlgrey.
*
* This is the size (in bytes) of the peripheral's reserved memory area. All
* memory-mapped registers associated with this peripheral should have an
- * address between #TOP_EARLGREY_RSTMGR_BASE_ADDR and
- * `TOP_EARLGREY_RSTMGR_BASE_ADDR + TOP_EARLGREY_RSTMGR_SIZE_BYTES`.
+ * address between #TOP_EARLGREY_RSTMGR_AON_BASE_ADDR and
+ * `TOP_EARLGREY_RSTMGR_AON_BASE_ADDR + TOP_EARLGREY_RSTMGR_AON_SIZE_BYTES`.
*/
-#define TOP_EARLGREY_RSTMGR_SIZE_BYTES 0x1000u
+#define TOP_EARLGREY_RSTMGR_AON_SIZE_BYTES 0x1000u
/**
- * Peripheral base address for clkmgr in top earlgrey.
+ * Peripheral base address for clkmgr_aon in top earlgrey.
*
* This should be used with #mmio_region_from_addr to access the memory-mapped
* registers associated with the peripheral (usually via a DIF).
*/
-#define TOP_EARLGREY_CLKMGR_BASE_ADDR 0x40420000u
+#define TOP_EARLGREY_CLKMGR_AON_BASE_ADDR 0x40420000u
/**
- * Peripheral size for clkmgr in top earlgrey.
+ * Peripheral size for clkmgr_aon in top earlgrey.
*
* This is the size (in bytes) of the peripheral's reserved memory area. All
* memory-mapped registers associated with this peripheral should have an
- * address between #TOP_EARLGREY_CLKMGR_BASE_ADDR and
- * `TOP_EARLGREY_CLKMGR_BASE_ADDR + TOP_EARLGREY_CLKMGR_SIZE_BYTES`.
+ * address between #TOP_EARLGREY_CLKMGR_AON_BASE_ADDR and
+ * `TOP_EARLGREY_CLKMGR_AON_BASE_ADDR + TOP_EARLGREY_CLKMGR_AON_SIZE_BYTES`.
*/
-#define TOP_EARLGREY_CLKMGR_SIZE_BYTES 0x1000u
+#define TOP_EARLGREY_CLKMGR_AON_SIZE_BYTES 0x1000u
/**
- * Peripheral base address for pinmux in top earlgrey.
+ * Peripheral base address for pinmux_aon in top earlgrey.
*
* This should be used with #mmio_region_from_addr to access the memory-mapped
* registers associated with the peripheral (usually via a DIF).
*/
-#define TOP_EARLGREY_PINMUX_BASE_ADDR 0x40460000u
+#define TOP_EARLGREY_PINMUX_AON_BASE_ADDR 0x40460000u
/**
- * Peripheral size for pinmux in top earlgrey.
+ * Peripheral size for pinmux_aon in top earlgrey.
*
* This is the size (in bytes) of the peripheral's reserved memory area. All
* memory-mapped registers associated with this peripheral should have an
- * address between #TOP_EARLGREY_PINMUX_BASE_ADDR and
- * `TOP_EARLGREY_PINMUX_BASE_ADDR + TOP_EARLGREY_PINMUX_SIZE_BYTES`.
+ * address between #TOP_EARLGREY_PINMUX_AON_BASE_ADDR and
+ * `TOP_EARLGREY_PINMUX_AON_BASE_ADDR + TOP_EARLGREY_PINMUX_AON_SIZE_BYTES`.
*/
-#define TOP_EARLGREY_PINMUX_SIZE_BYTES 0x1000u
+#define TOP_EARLGREY_PINMUX_AON_SIZE_BYTES 0x1000u
/**
- * Peripheral base address for padctrl in top earlgrey.
+ * Peripheral base address for padctrl_aon in top earlgrey.
*
* This should be used with #mmio_region_from_addr to access the memory-mapped
* registers associated with the peripheral (usually via a DIF).
*/
-#define TOP_EARLGREY_PADCTRL_BASE_ADDR 0x40470000u
+#define TOP_EARLGREY_PADCTRL_AON_BASE_ADDR 0x40470000u
/**
- * Peripheral size for padctrl in top earlgrey.
+ * Peripheral size for padctrl_aon in top earlgrey.
*
* This is the size (in bytes) of the peripheral's reserved memory area. All
* memory-mapped registers associated with this peripheral should have an
- * address between #TOP_EARLGREY_PADCTRL_BASE_ADDR and
- * `TOP_EARLGREY_PADCTRL_BASE_ADDR + TOP_EARLGREY_PADCTRL_SIZE_BYTES`.
+ * address between #TOP_EARLGREY_PADCTRL_AON_BASE_ADDR and
+ * `TOP_EARLGREY_PADCTRL_AON_BASE_ADDR + TOP_EARLGREY_PADCTRL_AON_SIZE_BYTES`.
*/
-#define TOP_EARLGREY_PADCTRL_SIZE_BYTES 0x1000u
+#define TOP_EARLGREY_PADCTRL_AON_SIZE_BYTES 0x1000u
/**
- * Peripheral base address for usbdev in top earlgrey.
+ * Peripheral base address for sensor_ctrl_aon in top earlgrey.
*
* This should be used with #mmio_region_from_addr to access the memory-mapped
* registers associated with the peripheral (usually via a DIF).
*/
-#define TOP_EARLGREY_USBDEV_BASE_ADDR 0x40500000u
+#define TOP_EARLGREY_SENSOR_CTRL_AON_BASE_ADDR 0x40500000u
/**
- * Peripheral size for usbdev in top earlgrey.
+ * Peripheral size for sensor_ctrl_aon in top earlgrey.
*
* This is the size (in bytes) of the peripheral's reserved memory area. All
* memory-mapped registers associated with this peripheral should have an
- * address between #TOP_EARLGREY_USBDEV_BASE_ADDR and
- * `TOP_EARLGREY_USBDEV_BASE_ADDR + TOP_EARLGREY_USBDEV_SIZE_BYTES`.
+ * address between #TOP_EARLGREY_SENSOR_CTRL_AON_BASE_ADDR and
+ * `TOP_EARLGREY_SENSOR_CTRL_AON_BASE_ADDR + TOP_EARLGREY_SENSOR_CTRL_AON_SIZE_BYTES`.
*/
-#define TOP_EARLGREY_USBDEV_SIZE_BYTES 0x1000u
+#define TOP_EARLGREY_SENSOR_CTRL_AON_SIZE_BYTES 0x1000u
/**
- * Peripheral base address for sram_ctrl_ret in top earlgrey.
+ * Peripheral base address for sram_ctrl_ret_aon in top earlgrey.
*
* This should be used with #mmio_region_from_addr to access the memory-mapped
* registers associated with the peripheral (usually via a DIF).
*/
-#define TOP_EARLGREY_SRAM_CTRL_RET_BASE_ADDR 0x40510000u
+#define TOP_EARLGREY_SRAM_CTRL_RET_AON_BASE_ADDR 0x40510000u
/**
- * Peripheral size for sram_ctrl_ret in top earlgrey.
+ * Peripheral size for sram_ctrl_ret_aon in top earlgrey.
*
* This is the size (in bytes) of the peripheral's reserved memory area. All
* memory-mapped registers associated with this peripheral should have an
- * address between #TOP_EARLGREY_SRAM_CTRL_RET_BASE_ADDR and
- * `TOP_EARLGREY_SRAM_CTRL_RET_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_RET_SIZE_BYTES`.
+ * address between #TOP_EARLGREY_SRAM_CTRL_RET_AON_BASE_ADDR and
+ * `TOP_EARLGREY_SRAM_CTRL_RET_AON_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_RET_AON_SIZE_BYTES`.
*/
-#define TOP_EARLGREY_SRAM_CTRL_RET_SIZE_BYTES 0x1000u
+#define TOP_EARLGREY_SRAM_CTRL_RET_AON_SIZE_BYTES 0x1000u
/**
* Peripheral base address for flash_ctrl in top earlgrey.
@@ -677,14 +677,14 @@
#define TOP_EARLGREY_RAM_MAIN_SIZE_BYTES 0x20000u
/**
- * Memory base address for ram_ret in top earlgrey.
+ * Memory base address for ram_ret_aon in top earlgrey.
*/
-#define TOP_EARLGREY_RAM_RET_BASE_ADDR 0x40520000u
+#define TOP_EARLGREY_RAM_RET_AON_BASE_ADDR 0x40520000u
/**
- * Memory size for ram_ret in top earlgrey.
+ * Memory size for ram_ret_aon in top earlgrey.
*/
-#define TOP_EARLGREY_RAM_RET_SIZE_BYTES 0x1000u
+#define TOP_EARLGREY_RAM_RET_AON_SIZE_BYTES 0x1000u
/**
* Memory base address for eflash in top earlgrey.
@@ -720,7 +720,7 @@
kTopEarlgreyPlicPeripheralAlertHandler = 13, /**< alert_handler */
kTopEarlgreyPlicPeripheralNmiGen = 14, /**< nmi_gen */
kTopEarlgreyPlicPeripheralUsbdev = 15, /**< usbdev */
- kTopEarlgreyPlicPeripheralPwrmgr = 16, /**< pwrmgr */
+ kTopEarlgreyPlicPeripheralPwrmgrAon = 16, /**< pwrmgr_aon */
kTopEarlgreyPlicPeripheralOtbn = 17, /**< otbn */
kTopEarlgreyPlicPeripheralKeymgr = 18, /**< keymgr */
kTopEarlgreyPlicPeripheralKmac = 19, /**< kmac */
@@ -892,7 +892,7 @@
kTopEarlgreyPlicIrqIdUsbdevFrame = 150, /**< usbdev_frame */
kTopEarlgreyPlicIrqIdUsbdevConnected = 151, /**< usbdev_connected */
kTopEarlgreyPlicIrqIdUsbdevLinkOutErr = 152, /**< usbdev_link_out_err */
- kTopEarlgreyPlicIrqIdPwrmgrWakeup = 153, /**< pwrmgr_wakeup */
+ kTopEarlgreyPlicIrqIdPwrmgrAonWakeup = 153, /**< pwrmgr_aon_wakeup */
kTopEarlgreyPlicIrqIdOtbnDone = 154, /**< otbn_done */
kTopEarlgreyPlicIrqIdKeymgrOpDone = 155, /**< keymgr_op_done */
kTopEarlgreyPlicIrqIdKmacKmacDone = 156, /**< kmac_kmac_done */
@@ -943,13 +943,13 @@
typedef enum top_earlgrey_alert_peripheral {
kTopEarlgreyAlertPeripheralAes = 0, /**< aes */
kTopEarlgreyAlertPeripheralOtbn = 1, /**< otbn */
- kTopEarlgreyAlertPeripheralSensorCtrl = 2, /**< sensor_ctrl */
+ kTopEarlgreyAlertPeripheralSensorCtrlAon = 2, /**< sensor_ctrl_aon */
kTopEarlgreyAlertPeripheralKeymgr = 3, /**< keymgr */
kTopEarlgreyAlertPeripheralOtpCtrl = 4, /**< otp_ctrl */
kTopEarlgreyAlertPeripheralLcCtrl = 5, /**< lc_ctrl */
kTopEarlgreyAlertPeripheralEntropySrc = 6, /**< entropy_src */
kTopEarlgreyAlertPeripheralSramCtrlMain = 7, /**< sram_ctrl_main */
- kTopEarlgreyAlertPeripheralSramCtrlRet = 8, /**< sram_ctrl_ret */
+ kTopEarlgreyAlertPeripheralSramCtrlRetAon = 8, /**< sram_ctrl_ret_aon */
kTopEarlgreyAlertPeripheralFlashCtrl = 9, /**< flash_ctrl */
kTopEarlgreyAlertPeripheralLast = 9, /**< \internal Final Alert peripheral */
} top_earlgrey_alert_peripheral_t;
@@ -965,13 +965,13 @@
kTopEarlgreyAlertIdAesFatalFault = 1, /**< aes_fatal_fault */
kTopEarlgreyAlertIdOtbnFatal = 2, /**< otbn_fatal */
kTopEarlgreyAlertIdOtbnRecov = 3, /**< otbn_recov */
- kTopEarlgreyAlertIdSensorCtrlRecovAs = 4, /**< sensor_ctrl_recov_as */
- kTopEarlgreyAlertIdSensorCtrlRecovCg = 5, /**< sensor_ctrl_recov_cg */
- kTopEarlgreyAlertIdSensorCtrlRecovGd = 6, /**< sensor_ctrl_recov_gd */
- kTopEarlgreyAlertIdSensorCtrlRecovTsHi = 7, /**< sensor_ctrl_recov_ts_hi */
- kTopEarlgreyAlertIdSensorCtrlRecovTsLo = 8, /**< sensor_ctrl_recov_ts_lo */
- kTopEarlgreyAlertIdSensorCtrlRecovLs = 9, /**< sensor_ctrl_recov_ls */
- kTopEarlgreyAlertIdSensorCtrlRecovOt = 10, /**< sensor_ctrl_recov_ot */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovAs = 4, /**< sensor_ctrl_aon_recov_as */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovCg = 5, /**< sensor_ctrl_aon_recov_cg */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovGd = 6, /**< sensor_ctrl_aon_recov_gd */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovTsHi = 7, /**< sensor_ctrl_aon_recov_ts_hi */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovTsLo = 8, /**< sensor_ctrl_aon_recov_ts_lo */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovLs = 9, /**< sensor_ctrl_aon_recov_ls */
+ kTopEarlgreyAlertIdSensorCtrlAonRecovOt = 10, /**< sensor_ctrl_aon_recov_ot */
kTopEarlgreyAlertIdKeymgrFatalFaultErr = 11, /**< keymgr_fatal_fault_err */
kTopEarlgreyAlertIdKeymgrRecovOperationErr = 12, /**< keymgr_recov_operation_err */
kTopEarlgreyAlertIdOtpCtrlFatalMacroError = 13, /**< otp_ctrl_fatal_macro_error */
@@ -980,7 +980,7 @@
kTopEarlgreyAlertIdLcCtrlFatalStateError = 16, /**< lc_ctrl_fatal_state_error */
kTopEarlgreyAlertIdEntropySrcRecovAlertCountMet = 17, /**< entropy_src_recov_alert_count_met */
kTopEarlgreyAlertIdSramCtrlMainFatalParityError = 18, /**< sram_ctrl_main_fatal_parity_error */
- kTopEarlgreyAlertIdSramCtrlRetFatalParityError = 19, /**< sram_ctrl_ret_fatal_parity_error */
+ kTopEarlgreyAlertIdSramCtrlRetAonFatalParityError = 19, /**< sram_ctrl_ret_aon_fatal_parity_error */
kTopEarlgreyAlertIdFlashCtrlRecovErr = 20, /**< flash_ctrl_recov_err */
kTopEarlgreyAlertIdFlashCtrlRecovMpErr = 21, /**< flash_ctrl_recov_mp_err */
kTopEarlgreyAlertIdFlashCtrlRecovEccErr = 22, /**< flash_ctrl_recov_ecc_err */
@@ -1192,7 +1192,7 @@
* Power Manager Wakeup Signals
*/
typedef enum top_earlgrey_power_manager_wake_ups {
- kTopEarlgreyPowerManagerWakeUpsPinmuxAonWkupReq = 0, /**< */
+ kTopEarlgreyPowerManagerWakeUpsPinmuxAonAonWkupReq = 0, /**< */
kTopEarlgreyPowerManagerWakeUpsLast = 0, /**< \internal Last valid pwrmgr wakeup signal */
} top_earlgrey_power_manager_wake_ups_t;
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
index cc37e7e..a7f6d08 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
@@ -41,14 +41,14 @@
#define TOP_EARLGREY_RAM_MAIN_SIZE_BYTES 0x20000
/**
- * Memory base address for ram_ret in top earlgrey.
+ * Memory base address for ram_ret_aon in top earlgrey.
*/
-#define TOP_EARLGREY_RAM_RET_BASE_ADDR 0x40520000
+#define TOP_EARLGREY_RAM_RET_AON_BASE_ADDR 0x40520000
/**
- * Memory size for ram_ret in top earlgrey.
+ * Memory size for ram_ret_aon in top earlgrey.
*/
-#define TOP_EARLGREY_RAM_RET_SIZE_BYTES 0x1000
+#define TOP_EARLGREY_RAM_RET_AON_SIZE_BYTES 0x1000
/**
* Memory base address for eflash in top earlgrey.
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
index f19a4ac..455737e 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.ld
@@ -8,6 +8,6 @@
MEMORY {
rom(rx) : ORIGIN = 0x00008000, LENGTH = 0x4000
ram_main(rw) : ORIGIN = 0x10000000, LENGTH = 0x20000
- ram_ret(rw) : ORIGIN = 0x40520000, LENGTH = 0x1000
+ ram_ret_aon(rw) : ORIGIN = 0x40520000, LENGTH = 0x1000
eflash(rx) : ORIGIN = 0x20000000, LENGTH = 0x100000
}
