[dif/autogen] Use EXPECT_DIF_* macros in unit tests
This updates the autogen'd DIFs to make use of the `EXPECT_DIF_*` macros
that were recently added.
Signed-off-by: Timothy Trippel <ttrippel@google.com>
diff --git a/sw/device/lib/dif/autogen/dif_adc_ctrl_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_adc_ctrl_autogen_unittest.cc
index a5667fa..22f93d0 100644
--- a/sw/device/lib/dif/autogen/dif_adc_ctrl_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_adc_ctrl_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "adc_ctrl_regs.h" // Generated.
@@ -28,32 +29,31 @@
class InitTest : public AdcCtrlTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_adc_ctrl_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_adc_ctrl_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_adc_ctrl_init(dev().region(), &adc_ctrl_), kDifOk);
+ EXPECT_DIF_OK(dif_adc_ctrl_init(dev().region(), &adc_ctrl_));
}
class AlertForceTest : public AdcCtrlTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_adc_ctrl_alert_force(nullptr, kDifAdcCtrlAlertFatalFault),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_adc_ctrl_alert_force(nullptr, kDifAdcCtrlAlertFatalFault));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(
- dif_adc_ctrl_alert_force(nullptr, static_cast<dif_adc_ctrl_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_adc_ctrl_alert_force(nullptr, static_cast<dif_adc_ctrl_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(ADC_CTRL_ALERT_TEST_REG_OFFSET,
{{ADC_CTRL_ALERT_TEST_FATAL_FAULT_BIT, true}});
- EXPECT_EQ(dif_adc_ctrl_alert_force(&adc_ctrl_, kDifAdcCtrlAlertFatalFault),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_adc_ctrl_alert_force(&adc_ctrl_, kDifAdcCtrlAlertFatalFault));
}
class IrqGetStateTest : public AdcCtrlTest {};
@@ -61,11 +61,11 @@
TEST_F(IrqGetStateTest, NullArgs) {
dif_adc_ctrl_irq_state_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_adc_ctrl_irq_get_state(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_adc_ctrl_irq_get_state(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_adc_ctrl_irq_get_state(&adc_ctrl_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_adc_ctrl_irq_get_state(&adc_ctrl_, nullptr));
- EXPECT_EQ(dif_adc_ctrl_irq_get_state(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_adc_ctrl_irq_get_state(nullptr, nullptr));
}
TEST_F(IrqGetStateTest, SuccessAllRaised) {
@@ -73,7 +73,7 @@
EXPECT_READ32(ADC_CTRL_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_adc_ctrl_irq_get_state(&adc_ctrl_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_adc_ctrl_irq_get_state(&adc_ctrl_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -81,7 +81,7 @@
dif_adc_ctrl_irq_state_snapshot_t irq_snapshot = 0;
EXPECT_READ32(ADC_CTRL_INTR_STATE_REG_OFFSET, 0);
- EXPECT_EQ(dif_adc_ctrl_irq_get_state(&adc_ctrl_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_adc_ctrl_irq_get_state(&adc_ctrl_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -90,25 +90,21 @@
TEST_F(IrqIsPendingTest, NullArgs) {
bool is_pending;
- EXPECT_EQ(dif_adc_ctrl_irq_is_pending(nullptr, kDifAdcCtrlIrqDebugCable,
- &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_adc_ctrl_irq_is_pending(
+ nullptr, kDifAdcCtrlIrqDebugCable, &is_pending));
- EXPECT_EQ(dif_adc_ctrl_irq_is_pending(&adc_ctrl_, kDifAdcCtrlIrqDebugCable,
- nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_adc_ctrl_irq_is_pending(
+ &adc_ctrl_, kDifAdcCtrlIrqDebugCable, nullptr));
- EXPECT_EQ(
- dif_adc_ctrl_irq_is_pending(nullptr, kDifAdcCtrlIrqDebugCable, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_adc_ctrl_irq_is_pending(nullptr, kDifAdcCtrlIrqDebugCable, nullptr));
}
TEST_F(IrqIsPendingTest, BadIrq) {
bool is_pending;
// All interrupt CSRs are 32 bit so interrupt 32 will be invalid.
- EXPECT_EQ(dif_adc_ctrl_irq_is_pending(
- &adc_ctrl_, static_cast<dif_adc_ctrl_irq_t>(32), &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_adc_ctrl_irq_is_pending(
+ &adc_ctrl_, static_cast<dif_adc_ctrl_irq_t>(32), &is_pending));
}
TEST_F(IrqIsPendingTest, Success) {
@@ -118,65 +114,60 @@
irq_state = false;
EXPECT_READ32(ADC_CTRL_INTR_STATE_REG_OFFSET,
{{ADC_CTRL_INTR_STATE_DEBUG_CABLE_BIT, true}});
- EXPECT_EQ(dif_adc_ctrl_irq_is_pending(&adc_ctrl_, kDifAdcCtrlIrqDebugCable,
- &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_adc_ctrl_irq_is_pending(
+ &adc_ctrl_, kDifAdcCtrlIrqDebugCable, &irq_state));
EXPECT_TRUE(irq_state);
}
class AcknowledgeAllTest : public AdcCtrlTest {};
TEST_F(AcknowledgeAllTest, NullArgs) {
- EXPECT_EQ(dif_adc_ctrl_irq_acknowledge_all(nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_adc_ctrl_irq_acknowledge_all(nullptr));
}
TEST_F(AcknowledgeAllTest, Success) {
EXPECT_WRITE32(ADC_CTRL_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_adc_ctrl_irq_acknowledge_all(&adc_ctrl_), kDifOk);
+ EXPECT_DIF_OK(dif_adc_ctrl_irq_acknowledge_all(&adc_ctrl_));
}
class IrqAcknowledgeTest : public AdcCtrlTest {};
TEST_F(IrqAcknowledgeTest, NullArgs) {
- EXPECT_EQ(dif_adc_ctrl_irq_acknowledge(nullptr, kDifAdcCtrlIrqDebugCable),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_adc_ctrl_irq_acknowledge(nullptr, kDifAdcCtrlIrqDebugCable));
}
TEST_F(IrqAcknowledgeTest, BadIrq) {
- EXPECT_EQ(dif_adc_ctrl_irq_acknowledge(nullptr,
- static_cast<dif_adc_ctrl_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_adc_ctrl_irq_acknowledge(
+ nullptr, static_cast<dif_adc_ctrl_irq_t>(32)));
}
TEST_F(IrqAcknowledgeTest, Success) {
// Clear the first IRQ state.
EXPECT_WRITE32(ADC_CTRL_INTR_STATE_REG_OFFSET,
{{ADC_CTRL_INTR_STATE_DEBUG_CABLE_BIT, true}});
- EXPECT_EQ(dif_adc_ctrl_irq_acknowledge(&adc_ctrl_, kDifAdcCtrlIrqDebugCable),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_adc_ctrl_irq_acknowledge(&adc_ctrl_, kDifAdcCtrlIrqDebugCable));
}
class IrqForceTest : public AdcCtrlTest {};
TEST_F(IrqForceTest, NullArgs) {
- EXPECT_EQ(dif_adc_ctrl_irq_force(nullptr, kDifAdcCtrlIrqDebugCable),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_adc_ctrl_irq_force(nullptr, kDifAdcCtrlIrqDebugCable));
}
TEST_F(IrqForceTest, BadIrq) {
- EXPECT_EQ(
- dif_adc_ctrl_irq_force(nullptr, static_cast<dif_adc_ctrl_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_adc_ctrl_irq_force(nullptr, static_cast<dif_adc_ctrl_irq_t>(32)));
}
TEST_F(IrqForceTest, Success) {
// Force first IRQ.
EXPECT_WRITE32(ADC_CTRL_INTR_TEST_REG_OFFSET,
{{ADC_CTRL_INTR_TEST_DEBUG_CABLE_BIT, true}});
- EXPECT_EQ(dif_adc_ctrl_irq_force(&adc_ctrl_, kDifAdcCtrlIrqDebugCable),
- kDifOk);
+ EXPECT_DIF_OK(dif_adc_ctrl_irq_force(&adc_ctrl_, kDifAdcCtrlIrqDebugCable));
}
class IrqGetEnabledTest : public AdcCtrlTest {};
@@ -184,25 +175,21 @@
TEST_F(IrqGetEnabledTest, NullArgs) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_adc_ctrl_irq_get_enabled(nullptr, kDifAdcCtrlIrqDebugCable,
- &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_adc_ctrl_irq_get_enabled(
+ nullptr, kDifAdcCtrlIrqDebugCable, &irq_state));
- EXPECT_EQ(dif_adc_ctrl_irq_get_enabled(&adc_ctrl_, kDifAdcCtrlIrqDebugCable,
- nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_adc_ctrl_irq_get_enabled(
+ &adc_ctrl_, kDifAdcCtrlIrqDebugCable, nullptr));
- EXPECT_EQ(
- dif_adc_ctrl_irq_get_enabled(nullptr, kDifAdcCtrlIrqDebugCable, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_adc_ctrl_irq_get_enabled(nullptr, kDifAdcCtrlIrqDebugCable, nullptr));
}
TEST_F(IrqGetEnabledTest, BadIrq) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_adc_ctrl_irq_get_enabled(
- &adc_ctrl_, static_cast<dif_adc_ctrl_irq_t>(32), &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_adc_ctrl_irq_get_enabled(
+ &adc_ctrl_, static_cast<dif_adc_ctrl_irq_t>(32), &irq_state));
}
TEST_F(IrqGetEnabledTest, Success) {
@@ -212,9 +199,8 @@
irq_state = kDifToggleDisabled;
EXPECT_READ32(ADC_CTRL_INTR_ENABLE_REG_OFFSET,
{{ADC_CTRL_INTR_ENABLE_DEBUG_CABLE_BIT, true}});
- EXPECT_EQ(dif_adc_ctrl_irq_get_enabled(&adc_ctrl_, kDifAdcCtrlIrqDebugCable,
- &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_adc_ctrl_irq_get_enabled(
+ &adc_ctrl_, kDifAdcCtrlIrqDebugCable, &irq_state));
EXPECT_EQ(irq_state, kDifToggleEnabled);
}
@@ -223,17 +209,15 @@
TEST_F(IrqSetEnabledTest, NullArgs) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_adc_ctrl_irq_set_enabled(nullptr, kDifAdcCtrlIrqDebugCable,
- irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_adc_ctrl_irq_set_enabled(
+ nullptr, kDifAdcCtrlIrqDebugCable, irq_state));
}
TEST_F(IrqSetEnabledTest, BadIrq) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_adc_ctrl_irq_set_enabled(
- &adc_ctrl_, static_cast<dif_adc_ctrl_irq_t>(32), irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_adc_ctrl_irq_set_enabled(
+ &adc_ctrl_, static_cast<dif_adc_ctrl_irq_t>(32), irq_state));
}
TEST_F(IrqSetEnabledTest, Success) {
@@ -243,9 +227,8 @@
irq_state = kDifToggleEnabled;
EXPECT_MASK32(ADC_CTRL_INTR_ENABLE_REG_OFFSET,
{{ADC_CTRL_INTR_ENABLE_DEBUG_CABLE_BIT, 0x1, true}});
- EXPECT_EQ(dif_adc_ctrl_irq_set_enabled(&adc_ctrl_, kDifAdcCtrlIrqDebugCable,
- irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_adc_ctrl_irq_set_enabled(
+ &adc_ctrl_, kDifAdcCtrlIrqDebugCable, irq_state));
}
class IrqDisableAllTest : public AdcCtrlTest {};
@@ -253,14 +236,14 @@
TEST_F(IrqDisableAllTest, NullArgs) {
dif_adc_ctrl_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_adc_ctrl_irq_disable_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_adc_ctrl_irq_disable_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_adc_ctrl_irq_disable_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_adc_ctrl_irq_disable_all(nullptr, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessNoSnapshot) {
EXPECT_WRITE32(ADC_CTRL_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_adc_ctrl_irq_disable_all(&adc_ctrl_, nullptr), kDifOk);
+ EXPECT_DIF_OK(dif_adc_ctrl_irq_disable_all(&adc_ctrl_, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessSnapshotAllDisabled) {
@@ -268,7 +251,7 @@
EXPECT_READ32(ADC_CTRL_INTR_ENABLE_REG_OFFSET, 0);
EXPECT_WRITE32(ADC_CTRL_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_adc_ctrl_irq_disable_all(&adc_ctrl_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_adc_ctrl_irq_disable_all(&adc_ctrl_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -278,7 +261,7 @@
EXPECT_READ32(ADC_CTRL_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
EXPECT_WRITE32(ADC_CTRL_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_adc_ctrl_irq_disable_all(&adc_ctrl_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_adc_ctrl_irq_disable_all(&adc_ctrl_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -287,11 +270,11 @@
TEST_F(IrqRestoreAllTest, NullArgs) {
dif_adc_ctrl_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_adc_ctrl_irq_restore_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_adc_ctrl_irq_restore_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_adc_ctrl_irq_restore_all(&adc_ctrl_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_adc_ctrl_irq_restore_all(&adc_ctrl_, nullptr));
- EXPECT_EQ(dif_adc_ctrl_irq_restore_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_adc_ctrl_irq_restore_all(nullptr, nullptr));
}
TEST_F(IrqRestoreAllTest, SuccessAllEnabled) {
@@ -300,14 +283,14 @@
EXPECT_WRITE32(ADC_CTRL_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_adc_ctrl_irq_restore_all(&adc_ctrl_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_adc_ctrl_irq_restore_all(&adc_ctrl_, &irq_snapshot));
}
TEST_F(IrqRestoreAllTest, SuccessAllDisabled) {
dif_adc_ctrl_irq_enable_snapshot_t irq_snapshot = 0;
EXPECT_WRITE32(ADC_CTRL_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_adc_ctrl_irq_restore_all(&adc_ctrl_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_adc_ctrl_irq_restore_all(&adc_ctrl_, &irq_snapshot));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_aes_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_aes_autogen_unittest.cc
index 1ceacbe..58b9034 100644
--- a/sw/device/lib/dif/autogen/dif_aes_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_aes_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "aes_regs.h" // Generated.
@@ -28,35 +29,35 @@
class InitTest : public AesTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_aes_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_aes_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_aes_init(dev().region(), &aes_), kDifOk);
+ EXPECT_DIF_OK(dif_aes_init(dev().region(), &aes_));
}
class AlertForceTest : public AesTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_aes_alert_force(nullptr, kDifAesAlertRecovCtrlUpdateErr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_aes_alert_force(nullptr, kDifAesAlertRecovCtrlUpdateErr));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(dif_aes_alert_force(nullptr, static_cast<dif_aes_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_aes_alert_force(nullptr, static_cast<dif_aes_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(AES_ALERT_TEST_REG_OFFSET,
{{AES_ALERT_TEST_RECOV_CTRL_UPDATE_ERR_BIT, true}});
- EXPECT_EQ(dif_aes_alert_force(&aes_, kDifAesAlertRecovCtrlUpdateErr), kDifOk);
+ EXPECT_DIF_OK(dif_aes_alert_force(&aes_, kDifAesAlertRecovCtrlUpdateErr));
// Force last alert.
EXPECT_WRITE32(AES_ALERT_TEST_REG_OFFSET,
{{AES_ALERT_TEST_FATAL_FAULT_BIT, true}});
- EXPECT_EQ(dif_aes_alert_force(&aes_, kDifAesAlertFatalFault), kDifOk);
+ EXPECT_DIF_OK(dif_aes_alert_force(&aes_, kDifAesAlertFatalFault));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_alert_handler_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_alert_handler_autogen_unittest.cc
index ac5952b..b1b83b2 100644
--- a/sw/device/lib/dif/autogen/dif_alert_handler_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_alert_handler_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "alert_handler_regs.h" // Generated.
@@ -28,11 +29,11 @@
class InitTest : public AlertHandlerTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_alert_handler_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_alert_handler_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_alert_handler_init(dev().region(), &alert_handler_), kDifOk);
+ EXPECT_DIF_OK(dif_alert_handler_init(dev().region(), &alert_handler_));
}
class IrqGetStateTest : public AlertHandlerTest {};
@@ -40,13 +41,11 @@
TEST_F(IrqGetStateTest, NullArgs) {
dif_alert_handler_irq_state_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_alert_handler_irq_get_state(nullptr, &irq_snapshot),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_alert_handler_irq_get_state(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_alert_handler_irq_get_state(&alert_handler_, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_alert_handler_irq_get_state(&alert_handler_, nullptr));
- EXPECT_EQ(dif_alert_handler_irq_get_state(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_alert_handler_irq_get_state(nullptr, nullptr));
}
TEST_F(IrqGetStateTest, SuccessAllRaised) {
@@ -54,8 +53,8 @@
EXPECT_READ32(ALERT_HANDLER_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_alert_handler_irq_get_state(&alert_handler_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_alert_handler_irq_get_state(&alert_handler_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -63,8 +62,8 @@
dif_alert_handler_irq_state_snapshot_t irq_snapshot = 0;
EXPECT_READ32(ALERT_HANDLER_INTR_STATE_REG_OFFSET, 0);
- EXPECT_EQ(dif_alert_handler_irq_get_state(&alert_handler_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_alert_handler_irq_get_state(&alert_handler_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -73,26 +72,21 @@
TEST_F(IrqIsPendingTest, NullArgs) {
bool is_pending;
- EXPECT_EQ(dif_alert_handler_irq_is_pending(nullptr, kDifAlertHandlerIrqClassa,
- &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_alert_handler_irq_is_pending(
+ nullptr, kDifAlertHandlerIrqClassa, &is_pending));
- EXPECT_EQ(dif_alert_handler_irq_is_pending(
- &alert_handler_, kDifAlertHandlerIrqClassa, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_alert_handler_irq_is_pending(
+ &alert_handler_, kDifAlertHandlerIrqClassa, nullptr));
- EXPECT_EQ(dif_alert_handler_irq_is_pending(nullptr, kDifAlertHandlerIrqClassa,
- nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_alert_handler_irq_is_pending(
+ nullptr, kDifAlertHandlerIrqClassa, nullptr));
}
TEST_F(IrqIsPendingTest, BadIrq) {
bool is_pending;
// All interrupt CSRs are 32 bit so interrupt 32 will be invalid.
- EXPECT_EQ(dif_alert_handler_irq_is_pending(
- &alert_handler_, static_cast<dif_alert_handler_irq_t>(32),
- &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_alert_handler_irq_is_pending(
+ &alert_handler_, static_cast<dif_alert_handler_irq_t>(32), &is_pending));
}
TEST_F(IrqIsPendingTest, Success) {
@@ -102,91 +96,82 @@
irq_state = false;
EXPECT_READ32(ALERT_HANDLER_INTR_STATE_REG_OFFSET,
{{ALERT_HANDLER_INTR_STATE_CLASSA_BIT, true}});
- EXPECT_EQ(dif_alert_handler_irq_is_pending(
- &alert_handler_, kDifAlertHandlerIrqClassa, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_alert_handler_irq_is_pending(
+ &alert_handler_, kDifAlertHandlerIrqClassa, &irq_state));
EXPECT_TRUE(irq_state);
// Get the last IRQ state.
irq_state = true;
EXPECT_READ32(ALERT_HANDLER_INTR_STATE_REG_OFFSET,
{{ALERT_HANDLER_INTR_STATE_CLASSD_BIT, false}});
- EXPECT_EQ(dif_alert_handler_irq_is_pending(
- &alert_handler_, kDifAlertHandlerIrqClassd, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_alert_handler_irq_is_pending(
+ &alert_handler_, kDifAlertHandlerIrqClassd, &irq_state));
EXPECT_FALSE(irq_state);
}
class AcknowledgeAllTest : public AlertHandlerTest {};
TEST_F(AcknowledgeAllTest, NullArgs) {
- EXPECT_EQ(dif_alert_handler_irq_acknowledge_all(nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_alert_handler_irq_acknowledge_all(nullptr));
}
TEST_F(AcknowledgeAllTest, Success) {
EXPECT_WRITE32(ALERT_HANDLER_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_alert_handler_irq_acknowledge_all(&alert_handler_), kDifOk);
+ EXPECT_DIF_OK(dif_alert_handler_irq_acknowledge_all(&alert_handler_));
}
class IrqAcknowledgeTest : public AlertHandlerTest {};
TEST_F(IrqAcknowledgeTest, NullArgs) {
- EXPECT_EQ(
- dif_alert_handler_irq_acknowledge(nullptr, kDifAlertHandlerIrqClassa),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_alert_handler_irq_acknowledge(nullptr, kDifAlertHandlerIrqClassa));
}
TEST_F(IrqAcknowledgeTest, BadIrq) {
- EXPECT_EQ(dif_alert_handler_irq_acknowledge(
- nullptr, static_cast<dif_alert_handler_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_alert_handler_irq_acknowledge(
+ nullptr, static_cast<dif_alert_handler_irq_t>(32)));
}
TEST_F(IrqAcknowledgeTest, Success) {
// Clear the first IRQ state.
EXPECT_WRITE32(ALERT_HANDLER_INTR_STATE_REG_OFFSET,
{{ALERT_HANDLER_INTR_STATE_CLASSA_BIT, true}});
- EXPECT_EQ(dif_alert_handler_irq_acknowledge(&alert_handler_,
- kDifAlertHandlerIrqClassa),
- kDifOk);
+ EXPECT_DIF_OK(dif_alert_handler_irq_acknowledge(&alert_handler_,
+ kDifAlertHandlerIrqClassa));
// Clear the last IRQ state.
EXPECT_WRITE32(ALERT_HANDLER_INTR_STATE_REG_OFFSET,
{{ALERT_HANDLER_INTR_STATE_CLASSD_BIT, true}});
- EXPECT_EQ(dif_alert_handler_irq_acknowledge(&alert_handler_,
- kDifAlertHandlerIrqClassd),
- kDifOk);
+ EXPECT_DIF_OK(dif_alert_handler_irq_acknowledge(&alert_handler_,
+ kDifAlertHandlerIrqClassd));
}
class IrqForceTest : public AlertHandlerTest {};
TEST_F(IrqForceTest, NullArgs) {
- EXPECT_EQ(dif_alert_handler_irq_force(nullptr, kDifAlertHandlerIrqClassa),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_alert_handler_irq_force(nullptr, kDifAlertHandlerIrqClassa));
}
TEST_F(IrqForceTest, BadIrq) {
- EXPECT_EQ(dif_alert_handler_irq_force(
- nullptr, static_cast<dif_alert_handler_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_alert_handler_irq_force(
+ nullptr, static_cast<dif_alert_handler_irq_t>(32)));
}
TEST_F(IrqForceTest, Success) {
// Force first IRQ.
EXPECT_WRITE32(ALERT_HANDLER_INTR_TEST_REG_OFFSET,
{{ALERT_HANDLER_INTR_TEST_CLASSA_BIT, true}});
- EXPECT_EQ(
- dif_alert_handler_irq_force(&alert_handler_, kDifAlertHandlerIrqClassa),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_alert_handler_irq_force(&alert_handler_, kDifAlertHandlerIrqClassa));
// Force last IRQ.
EXPECT_WRITE32(ALERT_HANDLER_INTR_TEST_REG_OFFSET,
{{ALERT_HANDLER_INTR_TEST_CLASSD_BIT, true}});
- EXPECT_EQ(
- dif_alert_handler_irq_force(&alert_handler_, kDifAlertHandlerIrqClassd),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_alert_handler_irq_force(&alert_handler_, kDifAlertHandlerIrqClassd));
}
class IrqGetEnabledTest : public AlertHandlerTest {};
@@ -194,26 +179,21 @@
TEST_F(IrqGetEnabledTest, NullArgs) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_alert_handler_irq_get_enabled(
- nullptr, kDifAlertHandlerIrqClassa, &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_alert_handler_irq_get_enabled(
+ nullptr, kDifAlertHandlerIrqClassa, &irq_state));
- EXPECT_EQ(dif_alert_handler_irq_get_enabled(
- &alert_handler_, kDifAlertHandlerIrqClassa, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_alert_handler_irq_get_enabled(
+ &alert_handler_, kDifAlertHandlerIrqClassa, nullptr));
- EXPECT_EQ(dif_alert_handler_irq_get_enabled(
- nullptr, kDifAlertHandlerIrqClassa, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_alert_handler_irq_get_enabled(
+ nullptr, kDifAlertHandlerIrqClassa, nullptr));
}
TEST_F(IrqGetEnabledTest, BadIrq) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_alert_handler_irq_get_enabled(
- &alert_handler_, static_cast<dif_alert_handler_irq_t>(32),
- &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_alert_handler_irq_get_enabled(
+ &alert_handler_, static_cast<dif_alert_handler_irq_t>(32), &irq_state));
}
TEST_F(IrqGetEnabledTest, Success) {
@@ -223,18 +203,16 @@
irq_state = kDifToggleDisabled;
EXPECT_READ32(ALERT_HANDLER_INTR_ENABLE_REG_OFFSET,
{{ALERT_HANDLER_INTR_ENABLE_CLASSA_BIT, true}});
- EXPECT_EQ(dif_alert_handler_irq_get_enabled(
- &alert_handler_, kDifAlertHandlerIrqClassa, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_alert_handler_irq_get_enabled(
+ &alert_handler_, kDifAlertHandlerIrqClassa, &irq_state));
EXPECT_EQ(irq_state, kDifToggleEnabled);
// Last IRQ is disabled.
irq_state = kDifToggleEnabled;
EXPECT_READ32(ALERT_HANDLER_INTR_ENABLE_REG_OFFSET,
{{ALERT_HANDLER_INTR_ENABLE_CLASSD_BIT, false}});
- EXPECT_EQ(dif_alert_handler_irq_get_enabled(
- &alert_handler_, kDifAlertHandlerIrqClassd, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_alert_handler_irq_get_enabled(
+ &alert_handler_, kDifAlertHandlerIrqClassd, &irq_state));
EXPECT_EQ(irq_state, kDifToggleDisabled);
}
@@ -243,18 +221,15 @@
TEST_F(IrqSetEnabledTest, NullArgs) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_alert_handler_irq_set_enabled(
- nullptr, kDifAlertHandlerIrqClassa, irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_alert_handler_irq_set_enabled(
+ nullptr, kDifAlertHandlerIrqClassa, irq_state));
}
TEST_F(IrqSetEnabledTest, BadIrq) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(
- dif_alert_handler_irq_set_enabled(
- &alert_handler_, static_cast<dif_alert_handler_irq_t>(32), irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_alert_handler_irq_set_enabled(
+ &alert_handler_, static_cast<dif_alert_handler_irq_t>(32), irq_state));
}
TEST_F(IrqSetEnabledTest, Success) {
@@ -264,17 +239,15 @@
irq_state = kDifToggleEnabled;
EXPECT_MASK32(ALERT_HANDLER_INTR_ENABLE_REG_OFFSET,
{{ALERT_HANDLER_INTR_ENABLE_CLASSA_BIT, 0x1, true}});
- EXPECT_EQ(dif_alert_handler_irq_set_enabled(
- &alert_handler_, kDifAlertHandlerIrqClassa, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_alert_handler_irq_set_enabled(
+ &alert_handler_, kDifAlertHandlerIrqClassa, irq_state));
// Disable last IRQ.
irq_state = kDifToggleDisabled;
EXPECT_MASK32(ALERT_HANDLER_INTR_ENABLE_REG_OFFSET,
{{ALERT_HANDLER_INTR_ENABLE_CLASSD_BIT, 0x1, false}});
- EXPECT_EQ(dif_alert_handler_irq_set_enabled(
- &alert_handler_, kDifAlertHandlerIrqClassd, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_alert_handler_irq_set_enabled(
+ &alert_handler_, kDifAlertHandlerIrqClassd, irq_state));
}
class IrqDisableAllTest : public AlertHandlerTest {};
@@ -282,16 +255,14 @@
TEST_F(IrqDisableAllTest, NullArgs) {
dif_alert_handler_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_alert_handler_irq_disable_all(nullptr, &irq_snapshot),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_alert_handler_irq_disable_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_alert_handler_irq_disable_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_alert_handler_irq_disable_all(nullptr, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessNoSnapshot) {
EXPECT_WRITE32(ALERT_HANDLER_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_alert_handler_irq_disable_all(&alert_handler_, nullptr),
- kDifOk);
+ EXPECT_DIF_OK(dif_alert_handler_irq_disable_all(&alert_handler_, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessSnapshotAllDisabled) {
@@ -299,8 +270,8 @@
EXPECT_READ32(ALERT_HANDLER_INTR_ENABLE_REG_OFFSET, 0);
EXPECT_WRITE32(ALERT_HANDLER_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_alert_handler_irq_disable_all(&alert_handler_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_alert_handler_irq_disable_all(&alert_handler_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -310,8 +281,8 @@
EXPECT_READ32(ALERT_HANDLER_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
EXPECT_WRITE32(ALERT_HANDLER_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_alert_handler_irq_disable_all(&alert_handler_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_alert_handler_irq_disable_all(&alert_handler_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -320,13 +291,12 @@
TEST_F(IrqRestoreAllTest, NullArgs) {
dif_alert_handler_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_alert_handler_irq_restore_all(nullptr, &irq_snapshot),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_alert_handler_irq_restore_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_alert_handler_irq_restore_all(&alert_handler_, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_alert_handler_irq_restore_all(&alert_handler_, nullptr));
- EXPECT_EQ(dif_alert_handler_irq_restore_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_alert_handler_irq_restore_all(nullptr, nullptr));
}
TEST_F(IrqRestoreAllTest, SuccessAllEnabled) {
@@ -335,16 +305,16 @@
EXPECT_WRITE32(ALERT_HANDLER_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_alert_handler_irq_restore_all(&alert_handler_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_alert_handler_irq_restore_all(&alert_handler_, &irq_snapshot));
}
TEST_F(IrqRestoreAllTest, SuccessAllDisabled) {
dif_alert_handler_irq_enable_snapshot_t irq_snapshot = 0;
EXPECT_WRITE32(ALERT_HANDLER_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_alert_handler_irq_restore_all(&alert_handler_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_alert_handler_irq_restore_all(&alert_handler_, &irq_snapshot));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_aon_timer_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_aon_timer_autogen_unittest.cc
index 395e339..acd9481 100644
--- a/sw/device/lib/dif/autogen/dif_aon_timer_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_aon_timer_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "aon_timer_regs.h" // Generated.
@@ -28,32 +29,31 @@
class InitTest : public AonTimerTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_aon_timer_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_aon_timer_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_aon_timer_init(dev().region(), &aon_timer_), kDifOk);
+ EXPECT_DIF_OK(dif_aon_timer_init(dev().region(), &aon_timer_));
}
class AlertForceTest : public AonTimerTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_aon_timer_alert_force(nullptr, kDifAonTimerAlertFatalFault),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_aon_timer_alert_force(nullptr, kDifAonTimerAlertFatalFault));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(dif_aon_timer_alert_force(nullptr,
- static_cast<dif_aon_timer_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_aon_timer_alert_force(
+ nullptr, static_cast<dif_aon_timer_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(AON_TIMER_ALERT_TEST_REG_OFFSET,
{{AON_TIMER_ALERT_TEST_FATAL_FAULT_BIT, true}});
- EXPECT_EQ(dif_aon_timer_alert_force(&aon_timer_, kDifAonTimerAlertFatalFault),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_aon_timer_alert_force(&aon_timer_, kDifAonTimerAlertFatalFault));
}
class IrqGetStateTest : public AonTimerTest {};
@@ -61,11 +61,11 @@
TEST_F(IrqGetStateTest, NullArgs) {
dif_aon_timer_irq_state_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_aon_timer_irq_get_state(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_aon_timer_irq_get_state(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_aon_timer_irq_get_state(&aon_timer_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_aon_timer_irq_get_state(&aon_timer_, nullptr));
- EXPECT_EQ(dif_aon_timer_irq_get_state(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_aon_timer_irq_get_state(nullptr, nullptr));
}
TEST_F(IrqGetStateTest, SuccessAllRaised) {
@@ -73,7 +73,7 @@
EXPECT_READ32(AON_TIMER_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_aon_timer_irq_get_state(&aon_timer_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_aon_timer_irq_get_state(&aon_timer_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -81,7 +81,7 @@
dif_aon_timer_irq_state_snapshot_t irq_snapshot = 0;
EXPECT_READ32(AON_TIMER_INTR_STATE_REG_OFFSET, 0);
- EXPECT_EQ(dif_aon_timer_irq_get_state(&aon_timer_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_aon_timer_irq_get_state(&aon_timer_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -90,25 +90,21 @@
TEST_F(IrqIsPendingTest, NullArgs) {
bool is_pending;
- EXPECT_EQ(dif_aon_timer_irq_is_pending(
- nullptr, kDifAonTimerIrqWkupTimerExpired, &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_aon_timer_irq_is_pending(
+ nullptr, kDifAonTimerIrqWkupTimerExpired, &is_pending));
- EXPECT_EQ(dif_aon_timer_irq_is_pending(
- &aon_timer_, kDifAonTimerIrqWkupTimerExpired, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_aon_timer_irq_is_pending(
+ &aon_timer_, kDifAonTimerIrqWkupTimerExpired, nullptr));
- EXPECT_EQ(dif_aon_timer_irq_is_pending(
- nullptr, kDifAonTimerIrqWkupTimerExpired, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_aon_timer_irq_is_pending(
+ nullptr, kDifAonTimerIrqWkupTimerExpired, nullptr));
}
TEST_F(IrqIsPendingTest, BadIrq) {
bool is_pending;
// All interrupt CSRs are 32 bit so interrupt 32 will be invalid.
- EXPECT_EQ(dif_aon_timer_irq_is_pending(
- &aon_timer_, static_cast<dif_aon_timer_irq_t>(32), &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_aon_timer_irq_is_pending(
+ &aon_timer_, static_cast<dif_aon_timer_irq_t>(32), &is_pending));
}
TEST_F(IrqIsPendingTest, Success) {
@@ -118,90 +114,82 @@
irq_state = false;
EXPECT_READ32(AON_TIMER_INTR_STATE_REG_OFFSET,
{{AON_TIMER_INTR_STATE_WKUP_TIMER_EXPIRED_BIT, true}});
- EXPECT_EQ(dif_aon_timer_irq_is_pending(
- &aon_timer_, kDifAonTimerIrqWkupTimerExpired, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_aon_timer_irq_is_pending(
+ &aon_timer_, kDifAonTimerIrqWkupTimerExpired, &irq_state));
EXPECT_TRUE(irq_state);
// Get the last IRQ state.
irq_state = true;
EXPECT_READ32(AON_TIMER_INTR_STATE_REG_OFFSET,
{{AON_TIMER_INTR_STATE_WDOG_TIMER_BARK_BIT, false}});
- EXPECT_EQ(dif_aon_timer_irq_is_pending(
- &aon_timer_, kDifAonTimerIrqWdogTimerBark, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_aon_timer_irq_is_pending(
+ &aon_timer_, kDifAonTimerIrqWdogTimerBark, &irq_state));
EXPECT_FALSE(irq_state);
}
class AcknowledgeAllTest : public AonTimerTest {};
TEST_F(AcknowledgeAllTest, NullArgs) {
- EXPECT_EQ(dif_aon_timer_irq_acknowledge_all(nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_aon_timer_irq_acknowledge_all(nullptr));
}
TEST_F(AcknowledgeAllTest, Success) {
EXPECT_WRITE32(AON_TIMER_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_aon_timer_irq_acknowledge_all(&aon_timer_), kDifOk);
+ EXPECT_DIF_OK(dif_aon_timer_irq_acknowledge_all(&aon_timer_));
}
class IrqAcknowledgeTest : public AonTimerTest {};
TEST_F(IrqAcknowledgeTest, NullArgs) {
- EXPECT_EQ(
- dif_aon_timer_irq_acknowledge(nullptr, kDifAonTimerIrqWkupTimerExpired),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_aon_timer_irq_acknowledge(nullptr, kDifAonTimerIrqWkupTimerExpired));
}
TEST_F(IrqAcknowledgeTest, BadIrq) {
- EXPECT_EQ(dif_aon_timer_irq_acknowledge(nullptr,
- static_cast<dif_aon_timer_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_aon_timer_irq_acknowledge(
+ nullptr, static_cast<dif_aon_timer_irq_t>(32)));
}
TEST_F(IrqAcknowledgeTest, Success) {
// Clear the first IRQ state.
EXPECT_WRITE32(AON_TIMER_INTR_STATE_REG_OFFSET,
{{AON_TIMER_INTR_STATE_WKUP_TIMER_EXPIRED_BIT, true}});
- EXPECT_EQ(dif_aon_timer_irq_acknowledge(&aon_timer_,
- kDifAonTimerIrqWkupTimerExpired),
- kDifOk);
+ EXPECT_DIF_OK(dif_aon_timer_irq_acknowledge(&aon_timer_,
+ kDifAonTimerIrqWkupTimerExpired));
// Clear the last IRQ state.
EXPECT_WRITE32(AON_TIMER_INTR_STATE_REG_OFFSET,
{{AON_TIMER_INTR_STATE_WDOG_TIMER_BARK_BIT, true}});
- EXPECT_EQ(
- dif_aon_timer_irq_acknowledge(&aon_timer_, kDifAonTimerIrqWdogTimerBark),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_aon_timer_irq_acknowledge(&aon_timer_, kDifAonTimerIrqWdogTimerBark));
}
class IrqForceTest : public AonTimerTest {};
TEST_F(IrqForceTest, NullArgs) {
- EXPECT_EQ(dif_aon_timer_irq_force(nullptr, kDifAonTimerIrqWkupTimerExpired),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_aon_timer_irq_force(nullptr, kDifAonTimerIrqWkupTimerExpired));
}
TEST_F(IrqForceTest, BadIrq) {
- EXPECT_EQ(
- dif_aon_timer_irq_force(nullptr, static_cast<dif_aon_timer_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_aon_timer_irq_force(nullptr, static_cast<dif_aon_timer_irq_t>(32)));
}
TEST_F(IrqForceTest, Success) {
// Force first IRQ.
EXPECT_WRITE32(AON_TIMER_INTR_TEST_REG_OFFSET,
{{AON_TIMER_INTR_TEST_WKUP_TIMER_EXPIRED_BIT, true}});
- EXPECT_EQ(
- dif_aon_timer_irq_force(&aon_timer_, kDifAonTimerIrqWkupTimerExpired),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_aon_timer_irq_force(&aon_timer_, kDifAonTimerIrqWkupTimerExpired));
// Force last IRQ.
EXPECT_WRITE32(AON_TIMER_INTR_TEST_REG_OFFSET,
{{AON_TIMER_INTR_TEST_WDOG_TIMER_BARK_BIT, true}});
- EXPECT_EQ(dif_aon_timer_irq_force(&aon_timer_, kDifAonTimerIrqWdogTimerBark),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_aon_timer_irq_force(&aon_timer_, kDifAonTimerIrqWdogTimerBark));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_clkmgr_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_clkmgr_autogen_unittest.cc
index f82847b..43b44cc 100644
--- a/sw/device/lib/dif/autogen/dif_clkmgr_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_clkmgr_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "clkmgr_regs.h" // Generated.
@@ -28,38 +29,34 @@
class InitTest : public ClkmgrTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_clkmgr_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_clkmgr_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_clkmgr_init(dev().region(), &clkmgr_), kDifOk);
+ EXPECT_DIF_OK(dif_clkmgr_init(dev().region(), &clkmgr_));
}
class AlertForceTest : public ClkmgrTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_clkmgr_alert_force(nullptr, kDifClkmgrAlertRecovFault),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_clkmgr_alert_force(nullptr, kDifClkmgrAlertRecovFault));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(
- dif_clkmgr_alert_force(nullptr, static_cast<dif_clkmgr_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_clkmgr_alert_force(nullptr, static_cast<dif_clkmgr_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(CLKMGR_ALERT_TEST_REG_OFFSET,
{{CLKMGR_ALERT_TEST_RECOV_FAULT_BIT, true}});
- EXPECT_EQ(dif_clkmgr_alert_force(&clkmgr_, kDifClkmgrAlertRecovFault),
- kDifOk);
+ EXPECT_DIF_OK(dif_clkmgr_alert_force(&clkmgr_, kDifClkmgrAlertRecovFault));
// Force last alert.
EXPECT_WRITE32(CLKMGR_ALERT_TEST_REG_OFFSET,
{{CLKMGR_ALERT_TEST_FATAL_FAULT_BIT, true}});
- EXPECT_EQ(dif_clkmgr_alert_force(&clkmgr_, kDifClkmgrAlertFatalFault),
- kDifOk);
+ EXPECT_DIF_OK(dif_clkmgr_alert_force(&clkmgr_, kDifClkmgrAlertFatalFault));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_csrng_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_csrng_autogen_unittest.cc
index e34eb0d..495811c 100644
--- a/sw/device/lib/dif/autogen/dif_csrng_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_csrng_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "csrng_regs.h" // Generated.
@@ -28,35 +29,34 @@
class InitTest : public CsrngTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_csrng_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_csrng_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_csrng_init(dev().region(), &csrng_), kDifOk);
+ EXPECT_DIF_OK(dif_csrng_init(dev().region(), &csrng_));
}
class AlertForceTest : public CsrngTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_csrng_alert_force(nullptr, kDifCsrngAlertRecovAlert),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_csrng_alert_force(nullptr, kDifCsrngAlertRecovAlert));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(dif_csrng_alert_force(nullptr, static_cast<dif_csrng_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_csrng_alert_force(nullptr, static_cast<dif_csrng_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(CSRNG_ALERT_TEST_REG_OFFSET,
{{CSRNG_ALERT_TEST_RECOV_ALERT_BIT, true}});
- EXPECT_EQ(dif_csrng_alert_force(&csrng_, kDifCsrngAlertRecovAlert), kDifOk);
+ EXPECT_DIF_OK(dif_csrng_alert_force(&csrng_, kDifCsrngAlertRecovAlert));
// Force last alert.
EXPECT_WRITE32(CSRNG_ALERT_TEST_REG_OFFSET,
{{CSRNG_ALERT_TEST_FATAL_ALERT_BIT, true}});
- EXPECT_EQ(dif_csrng_alert_force(&csrng_, kDifCsrngAlertFatalAlert), kDifOk);
+ EXPECT_DIF_OK(dif_csrng_alert_force(&csrng_, kDifCsrngAlertFatalAlert));
}
class IrqGetStateTest : public CsrngTest {};
@@ -64,11 +64,11 @@
TEST_F(IrqGetStateTest, NullArgs) {
dif_csrng_irq_state_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_csrng_irq_get_state(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_csrng_irq_get_state(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_csrng_irq_get_state(&csrng_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_csrng_irq_get_state(&csrng_, nullptr));
- EXPECT_EQ(dif_csrng_irq_get_state(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_csrng_irq_get_state(nullptr, nullptr));
}
TEST_F(IrqGetStateTest, SuccessAllRaised) {
@@ -76,7 +76,7 @@
EXPECT_READ32(CSRNG_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_csrng_irq_get_state(&csrng_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_csrng_irq_get_state(&csrng_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -84,7 +84,7 @@
dif_csrng_irq_state_snapshot_t irq_snapshot = 0;
EXPECT_READ32(CSRNG_INTR_STATE_REG_OFFSET, 0);
- EXPECT_EQ(dif_csrng_irq_get_state(&csrng_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_csrng_irq_get_state(&csrng_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -93,25 +93,21 @@
TEST_F(IrqIsPendingTest, NullArgs) {
bool is_pending;
- EXPECT_EQ(
- dif_csrng_irq_is_pending(nullptr, kDifCsrngIrqCsCmdReqDone, &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_csrng_irq_is_pending(nullptr, kDifCsrngIrqCsCmdReqDone, &is_pending));
- EXPECT_EQ(
- dif_csrng_irq_is_pending(&csrng_, kDifCsrngIrqCsCmdReqDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_csrng_irq_is_pending(&csrng_, kDifCsrngIrqCsCmdReqDone, nullptr));
- EXPECT_EQ(
- dif_csrng_irq_is_pending(nullptr, kDifCsrngIrqCsCmdReqDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_csrng_irq_is_pending(nullptr, kDifCsrngIrqCsCmdReqDone, nullptr));
}
TEST_F(IrqIsPendingTest, BadIrq) {
bool is_pending;
// All interrupt CSRs are 32 bit so interrupt 32 will be invalid.
- EXPECT_EQ(dif_csrng_irq_is_pending(&csrng_, static_cast<dif_csrng_irq_t>(32),
- &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_csrng_irq_is_pending(
+ &csrng_, static_cast<dif_csrng_irq_t>(32), &is_pending));
}
TEST_F(IrqIsPendingTest, Success) {
@@ -121,81 +117,77 @@
irq_state = false;
EXPECT_READ32(CSRNG_INTR_STATE_REG_OFFSET,
{{CSRNG_INTR_STATE_CS_CMD_REQ_DONE_BIT, true}});
- EXPECT_EQ(
- dif_csrng_irq_is_pending(&csrng_, kDifCsrngIrqCsCmdReqDone, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_csrng_irq_is_pending(&csrng_, kDifCsrngIrqCsCmdReqDone, &irq_state));
EXPECT_TRUE(irq_state);
// Get the last IRQ state.
irq_state = true;
EXPECT_READ32(CSRNG_INTR_STATE_REG_OFFSET,
{{CSRNG_INTR_STATE_CS_FATAL_ERR_BIT, false}});
- EXPECT_EQ(
- dif_csrng_irq_is_pending(&csrng_, kDifCsrngIrqCsFatalErr, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_csrng_irq_is_pending(&csrng_, kDifCsrngIrqCsFatalErr, &irq_state));
EXPECT_FALSE(irq_state);
}
class AcknowledgeAllTest : public CsrngTest {};
TEST_F(AcknowledgeAllTest, NullArgs) {
- EXPECT_EQ(dif_csrng_irq_acknowledge_all(nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_csrng_irq_acknowledge_all(nullptr));
}
TEST_F(AcknowledgeAllTest, Success) {
EXPECT_WRITE32(CSRNG_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_csrng_irq_acknowledge_all(&csrng_), kDifOk);
+ EXPECT_DIF_OK(dif_csrng_irq_acknowledge_all(&csrng_));
}
class IrqAcknowledgeTest : public CsrngTest {};
TEST_F(IrqAcknowledgeTest, NullArgs) {
- EXPECT_EQ(dif_csrng_irq_acknowledge(nullptr, kDifCsrngIrqCsCmdReqDone),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_csrng_irq_acknowledge(nullptr, kDifCsrngIrqCsCmdReqDone));
}
TEST_F(IrqAcknowledgeTest, BadIrq) {
- EXPECT_EQ(
- dif_csrng_irq_acknowledge(nullptr, static_cast<dif_csrng_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_csrng_irq_acknowledge(nullptr, static_cast<dif_csrng_irq_t>(32)));
}
TEST_F(IrqAcknowledgeTest, Success) {
// Clear the first IRQ state.
EXPECT_WRITE32(CSRNG_INTR_STATE_REG_OFFSET,
{{CSRNG_INTR_STATE_CS_CMD_REQ_DONE_BIT, true}});
- EXPECT_EQ(dif_csrng_irq_acknowledge(&csrng_, kDifCsrngIrqCsCmdReqDone),
- kDifOk);
+ EXPECT_DIF_OK(dif_csrng_irq_acknowledge(&csrng_, kDifCsrngIrqCsCmdReqDone));
// Clear the last IRQ state.
EXPECT_WRITE32(CSRNG_INTR_STATE_REG_OFFSET,
{{CSRNG_INTR_STATE_CS_FATAL_ERR_BIT, true}});
- EXPECT_EQ(dif_csrng_irq_acknowledge(&csrng_, kDifCsrngIrqCsFatalErr), kDifOk);
+ EXPECT_DIF_OK(dif_csrng_irq_acknowledge(&csrng_, kDifCsrngIrqCsFatalErr));
}
class IrqForceTest : public CsrngTest {};
TEST_F(IrqForceTest, NullArgs) {
- EXPECT_EQ(dif_csrng_irq_force(nullptr, kDifCsrngIrqCsCmdReqDone), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_csrng_irq_force(nullptr, kDifCsrngIrqCsCmdReqDone));
}
TEST_F(IrqForceTest, BadIrq) {
- EXPECT_EQ(dif_csrng_irq_force(nullptr, static_cast<dif_csrng_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_csrng_irq_force(nullptr, static_cast<dif_csrng_irq_t>(32)));
}
TEST_F(IrqForceTest, Success) {
// Force first IRQ.
EXPECT_WRITE32(CSRNG_INTR_TEST_REG_OFFSET,
{{CSRNG_INTR_TEST_CS_CMD_REQ_DONE_BIT, true}});
- EXPECT_EQ(dif_csrng_irq_force(&csrng_, kDifCsrngIrqCsCmdReqDone), kDifOk);
+ EXPECT_DIF_OK(dif_csrng_irq_force(&csrng_, kDifCsrngIrqCsCmdReqDone));
// Force last IRQ.
EXPECT_WRITE32(CSRNG_INTR_TEST_REG_OFFSET,
{{CSRNG_INTR_TEST_CS_FATAL_ERR_BIT, true}});
- EXPECT_EQ(dif_csrng_irq_force(&csrng_, kDifCsrngIrqCsFatalErr), kDifOk);
+ EXPECT_DIF_OK(dif_csrng_irq_force(&csrng_, kDifCsrngIrqCsFatalErr));
}
class IrqGetEnabledTest : public CsrngTest {};
@@ -203,25 +195,21 @@
TEST_F(IrqGetEnabledTest, NullArgs) {
dif_toggle_t irq_state;
- EXPECT_EQ(
- dif_csrng_irq_get_enabled(nullptr, kDifCsrngIrqCsCmdReqDone, &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_csrng_irq_get_enabled(nullptr, kDifCsrngIrqCsCmdReqDone, &irq_state));
- EXPECT_EQ(
- dif_csrng_irq_get_enabled(&csrng_, kDifCsrngIrqCsCmdReqDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_csrng_irq_get_enabled(&csrng_, kDifCsrngIrqCsCmdReqDone, nullptr));
- EXPECT_EQ(
- dif_csrng_irq_get_enabled(nullptr, kDifCsrngIrqCsCmdReqDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_csrng_irq_get_enabled(nullptr, kDifCsrngIrqCsCmdReqDone, nullptr));
}
TEST_F(IrqGetEnabledTest, BadIrq) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_csrng_irq_get_enabled(&csrng_, static_cast<dif_csrng_irq_t>(32),
- &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_csrng_irq_get_enabled(
+ &csrng_, static_cast<dif_csrng_irq_t>(32), &irq_state));
}
TEST_F(IrqGetEnabledTest, Success) {
@@ -231,18 +219,16 @@
irq_state = kDifToggleDisabled;
EXPECT_READ32(CSRNG_INTR_ENABLE_REG_OFFSET,
{{CSRNG_INTR_ENABLE_CS_CMD_REQ_DONE_BIT, true}});
- EXPECT_EQ(
- dif_csrng_irq_get_enabled(&csrng_, kDifCsrngIrqCsCmdReqDone, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_csrng_irq_get_enabled(&csrng_, kDifCsrngIrqCsCmdReqDone, &irq_state));
EXPECT_EQ(irq_state, kDifToggleEnabled);
// Last IRQ is disabled.
irq_state = kDifToggleEnabled;
EXPECT_READ32(CSRNG_INTR_ENABLE_REG_OFFSET,
{{CSRNG_INTR_ENABLE_CS_FATAL_ERR_BIT, false}});
- EXPECT_EQ(
- dif_csrng_irq_get_enabled(&csrng_, kDifCsrngIrqCsFatalErr, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_csrng_irq_get_enabled(&csrng_, kDifCsrngIrqCsFatalErr, &irq_state));
EXPECT_EQ(irq_state, kDifToggleDisabled);
}
@@ -251,17 +237,15 @@
TEST_F(IrqSetEnabledTest, NullArgs) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(
- dif_csrng_irq_set_enabled(nullptr, kDifCsrngIrqCsCmdReqDone, irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_csrng_irq_set_enabled(nullptr, kDifCsrngIrqCsCmdReqDone, irq_state));
}
TEST_F(IrqSetEnabledTest, BadIrq) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_csrng_irq_set_enabled(&csrng_, static_cast<dif_csrng_irq_t>(32),
- irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_csrng_irq_set_enabled(
+ &csrng_, static_cast<dif_csrng_irq_t>(32), irq_state));
}
TEST_F(IrqSetEnabledTest, Success) {
@@ -271,17 +255,15 @@
irq_state = kDifToggleEnabled;
EXPECT_MASK32(CSRNG_INTR_ENABLE_REG_OFFSET,
{{CSRNG_INTR_ENABLE_CS_CMD_REQ_DONE_BIT, 0x1, true}});
- EXPECT_EQ(
- dif_csrng_irq_set_enabled(&csrng_, kDifCsrngIrqCsCmdReqDone, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_csrng_irq_set_enabled(&csrng_, kDifCsrngIrqCsCmdReqDone, irq_state));
// Disable last IRQ.
irq_state = kDifToggleDisabled;
EXPECT_MASK32(CSRNG_INTR_ENABLE_REG_OFFSET,
{{CSRNG_INTR_ENABLE_CS_FATAL_ERR_BIT, 0x1, false}});
- EXPECT_EQ(
- dif_csrng_irq_set_enabled(&csrng_, kDifCsrngIrqCsFatalErr, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_csrng_irq_set_enabled(&csrng_, kDifCsrngIrqCsFatalErr, irq_state));
}
class IrqDisableAllTest : public CsrngTest {};
@@ -289,14 +271,14 @@
TEST_F(IrqDisableAllTest, NullArgs) {
dif_csrng_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_csrng_irq_disable_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_csrng_irq_disable_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_csrng_irq_disable_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_csrng_irq_disable_all(nullptr, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessNoSnapshot) {
EXPECT_WRITE32(CSRNG_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_csrng_irq_disable_all(&csrng_, nullptr), kDifOk);
+ EXPECT_DIF_OK(dif_csrng_irq_disable_all(&csrng_, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessSnapshotAllDisabled) {
@@ -304,7 +286,7 @@
EXPECT_READ32(CSRNG_INTR_ENABLE_REG_OFFSET, 0);
EXPECT_WRITE32(CSRNG_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_csrng_irq_disable_all(&csrng_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_csrng_irq_disable_all(&csrng_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -314,7 +296,7 @@
EXPECT_READ32(CSRNG_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
EXPECT_WRITE32(CSRNG_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_csrng_irq_disable_all(&csrng_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_csrng_irq_disable_all(&csrng_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -323,11 +305,11 @@
TEST_F(IrqRestoreAllTest, NullArgs) {
dif_csrng_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_csrng_irq_restore_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_csrng_irq_restore_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_csrng_irq_restore_all(&csrng_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_csrng_irq_restore_all(&csrng_, nullptr));
- EXPECT_EQ(dif_csrng_irq_restore_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_csrng_irq_restore_all(nullptr, nullptr));
}
TEST_F(IrqRestoreAllTest, SuccessAllEnabled) {
@@ -336,14 +318,14 @@
EXPECT_WRITE32(CSRNG_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_csrng_irq_restore_all(&csrng_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_csrng_irq_restore_all(&csrng_, &irq_snapshot));
}
TEST_F(IrqRestoreAllTest, SuccessAllDisabled) {
dif_csrng_irq_enable_snapshot_t irq_snapshot = 0;
EXPECT_WRITE32(CSRNG_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_csrng_irq_restore_all(&csrng_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_csrng_irq_restore_all(&csrng_, &irq_snapshot));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_edn_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_edn_autogen_unittest.cc
index dd792c7..97dcc74 100644
--- a/sw/device/lib/dif/autogen/dif_edn_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_edn_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "edn_regs.h" // Generated.
@@ -28,34 +29,34 @@
class InitTest : public EdnTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_edn_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_edn_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_edn_init(dev().region(), &edn_), kDifOk);
+ EXPECT_DIF_OK(dif_edn_init(dev().region(), &edn_));
}
class AlertForceTest : public EdnTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_edn_alert_force(nullptr, kDifEdnAlertRecovAlert), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_edn_alert_force(nullptr, kDifEdnAlertRecovAlert));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(dif_edn_alert_force(nullptr, static_cast<dif_edn_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_edn_alert_force(nullptr, static_cast<dif_edn_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(EDN_ALERT_TEST_REG_OFFSET,
{{EDN_ALERT_TEST_RECOV_ALERT_BIT, true}});
- EXPECT_EQ(dif_edn_alert_force(&edn_, kDifEdnAlertRecovAlert), kDifOk);
+ EXPECT_DIF_OK(dif_edn_alert_force(&edn_, kDifEdnAlertRecovAlert));
// Force last alert.
EXPECT_WRITE32(EDN_ALERT_TEST_REG_OFFSET,
{{EDN_ALERT_TEST_FATAL_ALERT_BIT, true}});
- EXPECT_EQ(dif_edn_alert_force(&edn_, kDifEdnAlertFatalAlert), kDifOk);
+ EXPECT_DIF_OK(dif_edn_alert_force(&edn_, kDifEdnAlertFatalAlert));
}
class IrqGetStateTest : public EdnTest {};
@@ -63,11 +64,11 @@
TEST_F(IrqGetStateTest, NullArgs) {
dif_edn_irq_state_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_edn_irq_get_state(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_edn_irq_get_state(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_edn_irq_get_state(&edn_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_edn_irq_get_state(&edn_, nullptr));
- EXPECT_EQ(dif_edn_irq_get_state(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_edn_irq_get_state(nullptr, nullptr));
}
TEST_F(IrqGetStateTest, SuccessAllRaised) {
@@ -75,7 +76,7 @@
EXPECT_READ32(EDN_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_edn_irq_get_state(&edn_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_edn_irq_get_state(&edn_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -83,7 +84,7 @@
dif_edn_irq_state_snapshot_t irq_snapshot = 0;
EXPECT_READ32(EDN_INTR_STATE_REG_OFFSET, 0);
- EXPECT_EQ(dif_edn_irq_get_state(&edn_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_edn_irq_get_state(&edn_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -92,23 +93,21 @@
TEST_F(IrqIsPendingTest, NullArgs) {
bool is_pending;
- EXPECT_EQ(
- dif_edn_irq_is_pending(nullptr, kDifEdnIrqEdnCmdReqDone, &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_edn_irq_is_pending(nullptr, kDifEdnIrqEdnCmdReqDone, &is_pending));
- EXPECT_EQ(dif_edn_irq_is_pending(&edn_, kDifEdnIrqEdnCmdReqDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_edn_irq_is_pending(&edn_, kDifEdnIrqEdnCmdReqDone, nullptr));
- EXPECT_EQ(dif_edn_irq_is_pending(nullptr, kDifEdnIrqEdnCmdReqDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_edn_irq_is_pending(nullptr, kDifEdnIrqEdnCmdReqDone, nullptr));
}
TEST_F(IrqIsPendingTest, BadIrq) {
bool is_pending;
// All interrupt CSRs are 32 bit so interrupt 32 will be invalid.
- EXPECT_EQ(dif_edn_irq_is_pending(&edn_, static_cast<dif_edn_irq_t>(32),
- &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_edn_irq_is_pending(
+ &edn_, static_cast<dif_edn_irq_t>(32), &is_pending));
}
TEST_F(IrqIsPendingTest, Success) {
@@ -118,77 +117,75 @@
irq_state = false;
EXPECT_READ32(EDN_INTR_STATE_REG_OFFSET,
{{EDN_INTR_STATE_EDN_CMD_REQ_DONE_BIT, true}});
- EXPECT_EQ(dif_edn_irq_is_pending(&edn_, kDifEdnIrqEdnCmdReqDone, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_edn_irq_is_pending(&edn_, kDifEdnIrqEdnCmdReqDone, &irq_state));
EXPECT_TRUE(irq_state);
// Get the last IRQ state.
irq_state = true;
EXPECT_READ32(EDN_INTR_STATE_REG_OFFSET,
{{EDN_INTR_STATE_EDN_FATAL_ERR_BIT, false}});
- EXPECT_EQ(dif_edn_irq_is_pending(&edn_, kDifEdnIrqEdnFatalErr, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_edn_irq_is_pending(&edn_, kDifEdnIrqEdnFatalErr, &irq_state));
EXPECT_FALSE(irq_state);
}
class AcknowledgeAllTest : public EdnTest {};
TEST_F(AcknowledgeAllTest, NullArgs) {
- EXPECT_EQ(dif_edn_irq_acknowledge_all(nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_edn_irq_acknowledge_all(nullptr));
}
TEST_F(AcknowledgeAllTest, Success) {
EXPECT_WRITE32(EDN_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_edn_irq_acknowledge_all(&edn_), kDifOk);
+ EXPECT_DIF_OK(dif_edn_irq_acknowledge_all(&edn_));
}
class IrqAcknowledgeTest : public EdnTest {};
TEST_F(IrqAcknowledgeTest, NullArgs) {
- EXPECT_EQ(dif_edn_irq_acknowledge(nullptr, kDifEdnIrqEdnCmdReqDone),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_edn_irq_acknowledge(nullptr, kDifEdnIrqEdnCmdReqDone));
}
TEST_F(IrqAcknowledgeTest, BadIrq) {
- EXPECT_EQ(dif_edn_irq_acknowledge(nullptr, static_cast<dif_edn_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_edn_irq_acknowledge(nullptr, static_cast<dif_edn_irq_t>(32)));
}
TEST_F(IrqAcknowledgeTest, Success) {
// Clear the first IRQ state.
EXPECT_WRITE32(EDN_INTR_STATE_REG_OFFSET,
{{EDN_INTR_STATE_EDN_CMD_REQ_DONE_BIT, true}});
- EXPECT_EQ(dif_edn_irq_acknowledge(&edn_, kDifEdnIrqEdnCmdReqDone), kDifOk);
+ EXPECT_DIF_OK(dif_edn_irq_acknowledge(&edn_, kDifEdnIrqEdnCmdReqDone));
// Clear the last IRQ state.
EXPECT_WRITE32(EDN_INTR_STATE_REG_OFFSET,
{{EDN_INTR_STATE_EDN_FATAL_ERR_BIT, true}});
- EXPECT_EQ(dif_edn_irq_acknowledge(&edn_, kDifEdnIrqEdnFatalErr), kDifOk);
+ EXPECT_DIF_OK(dif_edn_irq_acknowledge(&edn_, kDifEdnIrqEdnFatalErr));
}
class IrqForceTest : public EdnTest {};
TEST_F(IrqForceTest, NullArgs) {
- EXPECT_EQ(dif_edn_irq_force(nullptr, kDifEdnIrqEdnCmdReqDone), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_edn_irq_force(nullptr, kDifEdnIrqEdnCmdReqDone));
}
TEST_F(IrqForceTest, BadIrq) {
- EXPECT_EQ(dif_edn_irq_force(nullptr, static_cast<dif_edn_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_edn_irq_force(nullptr, static_cast<dif_edn_irq_t>(32)));
}
TEST_F(IrqForceTest, Success) {
// Force first IRQ.
EXPECT_WRITE32(EDN_INTR_TEST_REG_OFFSET,
{{EDN_INTR_TEST_EDN_CMD_REQ_DONE_BIT, true}});
- EXPECT_EQ(dif_edn_irq_force(&edn_, kDifEdnIrqEdnCmdReqDone), kDifOk);
+ EXPECT_DIF_OK(dif_edn_irq_force(&edn_, kDifEdnIrqEdnCmdReqDone));
// Force last IRQ.
EXPECT_WRITE32(EDN_INTR_TEST_REG_OFFSET,
{{EDN_INTR_TEST_EDN_FATAL_ERR_BIT, true}});
- EXPECT_EQ(dif_edn_irq_force(&edn_, kDifEdnIrqEdnFatalErr), kDifOk);
+ EXPECT_DIF_OK(dif_edn_irq_force(&edn_, kDifEdnIrqEdnFatalErr));
}
class IrqGetEnabledTest : public EdnTest {};
@@ -196,23 +193,21 @@
TEST_F(IrqGetEnabledTest, NullArgs) {
dif_toggle_t irq_state;
- EXPECT_EQ(
- dif_edn_irq_get_enabled(nullptr, kDifEdnIrqEdnCmdReqDone, &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_edn_irq_get_enabled(nullptr, kDifEdnIrqEdnCmdReqDone, &irq_state));
- EXPECT_EQ(dif_edn_irq_get_enabled(&edn_, kDifEdnIrqEdnCmdReqDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_edn_irq_get_enabled(&edn_, kDifEdnIrqEdnCmdReqDone, nullptr));
- EXPECT_EQ(dif_edn_irq_get_enabled(nullptr, kDifEdnIrqEdnCmdReqDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_edn_irq_get_enabled(nullptr, kDifEdnIrqEdnCmdReqDone, nullptr));
}
TEST_F(IrqGetEnabledTest, BadIrq) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_edn_irq_get_enabled(&edn_, static_cast<dif_edn_irq_t>(32),
- &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_edn_irq_get_enabled(
+ &edn_, static_cast<dif_edn_irq_t>(32), &irq_state));
}
TEST_F(IrqGetEnabledTest, Success) {
@@ -222,16 +217,16 @@
irq_state = kDifToggleDisabled;
EXPECT_READ32(EDN_INTR_ENABLE_REG_OFFSET,
{{EDN_INTR_ENABLE_EDN_CMD_REQ_DONE_BIT, true}});
- EXPECT_EQ(dif_edn_irq_get_enabled(&edn_, kDifEdnIrqEdnCmdReqDone, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_edn_irq_get_enabled(&edn_, kDifEdnIrqEdnCmdReqDone, &irq_state));
EXPECT_EQ(irq_state, kDifToggleEnabled);
// Last IRQ is disabled.
irq_state = kDifToggleEnabled;
EXPECT_READ32(EDN_INTR_ENABLE_REG_OFFSET,
{{EDN_INTR_ENABLE_EDN_FATAL_ERR_BIT, false}});
- EXPECT_EQ(dif_edn_irq_get_enabled(&edn_, kDifEdnIrqEdnFatalErr, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_edn_irq_get_enabled(&edn_, kDifEdnIrqEdnFatalErr, &irq_state));
EXPECT_EQ(irq_state, kDifToggleDisabled);
}
@@ -240,17 +235,15 @@
TEST_F(IrqSetEnabledTest, NullArgs) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(
- dif_edn_irq_set_enabled(nullptr, kDifEdnIrqEdnCmdReqDone, irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_edn_irq_set_enabled(nullptr, kDifEdnIrqEdnCmdReqDone, irq_state));
}
TEST_F(IrqSetEnabledTest, BadIrq) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(
- dif_edn_irq_set_enabled(&edn_, static_cast<dif_edn_irq_t>(32), irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_edn_irq_set_enabled(
+ &edn_, static_cast<dif_edn_irq_t>(32), irq_state));
}
TEST_F(IrqSetEnabledTest, Success) {
@@ -260,15 +253,15 @@
irq_state = kDifToggleEnabled;
EXPECT_MASK32(EDN_INTR_ENABLE_REG_OFFSET,
{{EDN_INTR_ENABLE_EDN_CMD_REQ_DONE_BIT, 0x1, true}});
- EXPECT_EQ(dif_edn_irq_set_enabled(&edn_, kDifEdnIrqEdnCmdReqDone, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_edn_irq_set_enabled(&edn_, kDifEdnIrqEdnCmdReqDone, irq_state));
// Disable last IRQ.
irq_state = kDifToggleDisabled;
EXPECT_MASK32(EDN_INTR_ENABLE_REG_OFFSET,
{{EDN_INTR_ENABLE_EDN_FATAL_ERR_BIT, 0x1, false}});
- EXPECT_EQ(dif_edn_irq_set_enabled(&edn_, kDifEdnIrqEdnFatalErr, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_edn_irq_set_enabled(&edn_, kDifEdnIrqEdnFatalErr, irq_state));
}
class IrqDisableAllTest : public EdnTest {};
@@ -276,14 +269,14 @@
TEST_F(IrqDisableAllTest, NullArgs) {
dif_edn_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_edn_irq_disable_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_edn_irq_disable_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_edn_irq_disable_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_edn_irq_disable_all(nullptr, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessNoSnapshot) {
EXPECT_WRITE32(EDN_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_edn_irq_disable_all(&edn_, nullptr), kDifOk);
+ EXPECT_DIF_OK(dif_edn_irq_disable_all(&edn_, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessSnapshotAllDisabled) {
@@ -291,7 +284,7 @@
EXPECT_READ32(EDN_INTR_ENABLE_REG_OFFSET, 0);
EXPECT_WRITE32(EDN_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_edn_irq_disable_all(&edn_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_edn_irq_disable_all(&edn_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -301,7 +294,7 @@
EXPECT_READ32(EDN_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
EXPECT_WRITE32(EDN_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_edn_irq_disable_all(&edn_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_edn_irq_disable_all(&edn_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -310,11 +303,11 @@
TEST_F(IrqRestoreAllTest, NullArgs) {
dif_edn_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_edn_irq_restore_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_edn_irq_restore_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_edn_irq_restore_all(&edn_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_edn_irq_restore_all(&edn_, nullptr));
- EXPECT_EQ(dif_edn_irq_restore_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_edn_irq_restore_all(nullptr, nullptr));
}
TEST_F(IrqRestoreAllTest, SuccessAllEnabled) {
@@ -323,14 +316,14 @@
EXPECT_WRITE32(EDN_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_edn_irq_restore_all(&edn_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_edn_irq_restore_all(&edn_, &irq_snapshot));
}
TEST_F(IrqRestoreAllTest, SuccessAllDisabled) {
dif_edn_irq_enable_snapshot_t irq_snapshot = 0;
EXPECT_WRITE32(EDN_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_edn_irq_restore_all(&edn_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_edn_irq_restore_all(&edn_, &irq_snapshot));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_entropy_src_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_entropy_src_autogen_unittest.cc
index a5cbaf1..515dc9a 100644
--- a/sw/device/lib/dif/autogen/dif_entropy_src_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_entropy_src_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "entropy_src_regs.h" // Generated.
@@ -28,40 +29,37 @@
class InitTest : public EntropySrcTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_entropy_src_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_entropy_src_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_entropy_src_init(dev().region(), &entropy_src_), kDifOk);
+ EXPECT_DIF_OK(dif_entropy_src_init(dev().region(), &entropy_src_));
}
class AlertForceTest : public EntropySrcTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_entropy_src_alert_force(nullptr, kDifEntropySrcAlertRecovAlert),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_entropy_src_alert_force(nullptr, kDifEntropySrcAlertRecovAlert));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(dif_entropy_src_alert_force(
- nullptr, static_cast<dif_entropy_src_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_entropy_src_alert_force(
+ nullptr, static_cast<dif_entropy_src_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(ENTROPY_SRC_ALERT_TEST_REG_OFFSET,
{{ENTROPY_SRC_ALERT_TEST_RECOV_ALERT_BIT, true}});
- EXPECT_EQ(
- dif_entropy_src_alert_force(&entropy_src_, kDifEntropySrcAlertRecovAlert),
- kDifOk);
+ EXPECT_DIF_OK(dif_entropy_src_alert_force(&entropy_src_,
+ kDifEntropySrcAlertRecovAlert));
// Force last alert.
EXPECT_WRITE32(ENTROPY_SRC_ALERT_TEST_REG_OFFSET,
{{ENTROPY_SRC_ALERT_TEST_FATAL_ALERT_BIT, true}});
- EXPECT_EQ(
- dif_entropy_src_alert_force(&entropy_src_, kDifEntropySrcAlertFatalAlert),
- kDifOk);
+ EXPECT_DIF_OK(dif_entropy_src_alert_force(&entropy_src_,
+ kDifEntropySrcAlertFatalAlert));
}
class IrqGetStateTest : public EntropySrcTest {};
@@ -69,11 +67,11 @@
TEST_F(IrqGetStateTest, NullArgs) {
dif_entropy_src_irq_state_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_entropy_src_irq_get_state(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_entropy_src_irq_get_state(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_entropy_src_irq_get_state(&entropy_src_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_entropy_src_irq_get_state(&entropy_src_, nullptr));
- EXPECT_EQ(dif_entropy_src_irq_get_state(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_entropy_src_irq_get_state(nullptr, nullptr));
}
TEST_F(IrqGetStateTest, SuccessAllRaised) {
@@ -81,8 +79,7 @@
EXPECT_READ32(ENTROPY_SRC_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_entropy_src_irq_get_state(&entropy_src_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(dif_entropy_src_irq_get_state(&entropy_src_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -90,8 +87,7 @@
dif_entropy_src_irq_state_snapshot_t irq_snapshot = 0;
EXPECT_READ32(ENTROPY_SRC_INTR_STATE_REG_OFFSET, 0);
- EXPECT_EQ(dif_entropy_src_irq_get_state(&entropy_src_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(dif_entropy_src_irq_get_state(&entropy_src_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -100,26 +96,21 @@
TEST_F(IrqIsPendingTest, NullArgs) {
bool is_pending;
- EXPECT_EQ(dif_entropy_src_irq_is_pending(
- nullptr, kDifEntropySrcIrqEsEntropyValid, &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_entropy_src_irq_is_pending(
+ nullptr, kDifEntropySrcIrqEsEntropyValid, &is_pending));
- EXPECT_EQ(dif_entropy_src_irq_is_pending(
- &entropy_src_, kDifEntropySrcIrqEsEntropyValid, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_entropy_src_irq_is_pending(
+ &entropy_src_, kDifEntropySrcIrqEsEntropyValid, nullptr));
- EXPECT_EQ(dif_entropy_src_irq_is_pending(
- nullptr, kDifEntropySrcIrqEsEntropyValid, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_entropy_src_irq_is_pending(
+ nullptr, kDifEntropySrcIrqEsEntropyValid, nullptr));
}
TEST_F(IrqIsPendingTest, BadIrq) {
bool is_pending;
// All interrupt CSRs are 32 bit so interrupt 32 will be invalid.
- EXPECT_EQ(
- dif_entropy_src_irq_is_pending(
- &entropy_src_, static_cast<dif_entropy_src_irq_t>(32), &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_entropy_src_irq_is_pending(
+ &entropy_src_, static_cast<dif_entropy_src_irq_t>(32), &is_pending));
}
TEST_F(IrqIsPendingTest, Success) {
@@ -129,91 +120,82 @@
irq_state = false;
EXPECT_READ32(ENTROPY_SRC_INTR_STATE_REG_OFFSET,
{{ENTROPY_SRC_INTR_STATE_ES_ENTROPY_VALID_BIT, true}});
- EXPECT_EQ(dif_entropy_src_irq_is_pending(
- &entropy_src_, kDifEntropySrcIrqEsEntropyValid, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_entropy_src_irq_is_pending(
+ &entropy_src_, kDifEntropySrcIrqEsEntropyValid, &irq_state));
EXPECT_TRUE(irq_state);
// Get the last IRQ state.
irq_state = true;
EXPECT_READ32(ENTROPY_SRC_INTR_STATE_REG_OFFSET,
{{ENTROPY_SRC_INTR_STATE_ES_FATAL_ERR_BIT, false}});
- EXPECT_EQ(dif_entropy_src_irq_is_pending(
- &entropy_src_, kDifEntropySrcIrqEsFatalErr, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_entropy_src_irq_is_pending(
+ &entropy_src_, kDifEntropySrcIrqEsFatalErr, &irq_state));
EXPECT_FALSE(irq_state);
}
class AcknowledgeAllTest : public EntropySrcTest {};
TEST_F(AcknowledgeAllTest, NullArgs) {
- EXPECT_EQ(dif_entropy_src_irq_acknowledge_all(nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_entropy_src_irq_acknowledge_all(nullptr));
}
TEST_F(AcknowledgeAllTest, Success) {
EXPECT_WRITE32(ENTROPY_SRC_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_entropy_src_irq_acknowledge_all(&entropy_src_), kDifOk);
+ EXPECT_DIF_OK(dif_entropy_src_irq_acknowledge_all(&entropy_src_));
}
class IrqAcknowledgeTest : public EntropySrcTest {};
TEST_F(IrqAcknowledgeTest, NullArgs) {
- EXPECT_EQ(
- dif_entropy_src_irq_acknowledge(nullptr, kDifEntropySrcIrqEsEntropyValid),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_entropy_src_irq_acknowledge(
+ nullptr, kDifEntropySrcIrqEsEntropyValid));
}
TEST_F(IrqAcknowledgeTest, BadIrq) {
- EXPECT_EQ(dif_entropy_src_irq_acknowledge(
- nullptr, static_cast<dif_entropy_src_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_entropy_src_irq_acknowledge(
+ nullptr, static_cast<dif_entropy_src_irq_t>(32)));
}
TEST_F(IrqAcknowledgeTest, Success) {
// Clear the first IRQ state.
EXPECT_WRITE32(ENTROPY_SRC_INTR_STATE_REG_OFFSET,
{{ENTROPY_SRC_INTR_STATE_ES_ENTROPY_VALID_BIT, true}});
- EXPECT_EQ(dif_entropy_src_irq_acknowledge(&entropy_src_,
- kDifEntropySrcIrqEsEntropyValid),
- kDifOk);
+ EXPECT_DIF_OK(dif_entropy_src_irq_acknowledge(
+ &entropy_src_, kDifEntropySrcIrqEsEntropyValid));
// Clear the last IRQ state.
EXPECT_WRITE32(ENTROPY_SRC_INTR_STATE_REG_OFFSET,
{{ENTROPY_SRC_INTR_STATE_ES_FATAL_ERR_BIT, true}});
- EXPECT_EQ(dif_entropy_src_irq_acknowledge(&entropy_src_,
- kDifEntropySrcIrqEsFatalErr),
- kDifOk);
+ EXPECT_DIF_OK(dif_entropy_src_irq_acknowledge(&entropy_src_,
+ kDifEntropySrcIrqEsFatalErr));
}
class IrqForceTest : public EntropySrcTest {};
TEST_F(IrqForceTest, NullArgs) {
- EXPECT_EQ(dif_entropy_src_irq_force(nullptr, kDifEntropySrcIrqEsEntropyValid),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_entropy_src_irq_force(nullptr, kDifEntropySrcIrqEsEntropyValid));
}
TEST_F(IrqForceTest, BadIrq) {
- EXPECT_EQ(dif_entropy_src_irq_force(nullptr,
- static_cast<dif_entropy_src_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_entropy_src_irq_force(
+ nullptr, static_cast<dif_entropy_src_irq_t>(32)));
}
TEST_F(IrqForceTest, Success) {
// Force first IRQ.
EXPECT_WRITE32(ENTROPY_SRC_INTR_TEST_REG_OFFSET,
{{ENTROPY_SRC_INTR_TEST_ES_ENTROPY_VALID_BIT, true}});
- EXPECT_EQ(
- dif_entropy_src_irq_force(&entropy_src_, kDifEntropySrcIrqEsEntropyValid),
- kDifOk);
+ EXPECT_DIF_OK(dif_entropy_src_irq_force(&entropy_src_,
+ kDifEntropySrcIrqEsEntropyValid));
// Force last IRQ.
EXPECT_WRITE32(ENTROPY_SRC_INTR_TEST_REG_OFFSET,
{{ENTROPY_SRC_INTR_TEST_ES_FATAL_ERR_BIT, true}});
- EXPECT_EQ(
- dif_entropy_src_irq_force(&entropy_src_, kDifEntropySrcIrqEsFatalErr),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_entropy_src_irq_force(&entropy_src_, kDifEntropySrcIrqEsFatalErr));
}
class IrqGetEnabledTest : public EntropySrcTest {};
@@ -221,26 +203,21 @@
TEST_F(IrqGetEnabledTest, NullArgs) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_entropy_src_irq_get_enabled(
- nullptr, kDifEntropySrcIrqEsEntropyValid, &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_entropy_src_irq_get_enabled(
+ nullptr, kDifEntropySrcIrqEsEntropyValid, &irq_state));
- EXPECT_EQ(dif_entropy_src_irq_get_enabled(
- &entropy_src_, kDifEntropySrcIrqEsEntropyValid, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_entropy_src_irq_get_enabled(
+ &entropy_src_, kDifEntropySrcIrqEsEntropyValid, nullptr));
- EXPECT_EQ(dif_entropy_src_irq_get_enabled(
- nullptr, kDifEntropySrcIrqEsEntropyValid, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_entropy_src_irq_get_enabled(
+ nullptr, kDifEntropySrcIrqEsEntropyValid, nullptr));
}
TEST_F(IrqGetEnabledTest, BadIrq) {
dif_toggle_t irq_state;
- EXPECT_EQ(
- dif_entropy_src_irq_get_enabled(
- &entropy_src_, static_cast<dif_entropy_src_irq_t>(32), &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_entropy_src_irq_get_enabled(
+ &entropy_src_, static_cast<dif_entropy_src_irq_t>(32), &irq_state));
}
TEST_F(IrqGetEnabledTest, Success) {
@@ -250,18 +227,16 @@
irq_state = kDifToggleDisabled;
EXPECT_READ32(ENTROPY_SRC_INTR_ENABLE_REG_OFFSET,
{{ENTROPY_SRC_INTR_ENABLE_ES_ENTROPY_VALID_BIT, true}});
- EXPECT_EQ(dif_entropy_src_irq_get_enabled(
- &entropy_src_, kDifEntropySrcIrqEsEntropyValid, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_entropy_src_irq_get_enabled(
+ &entropy_src_, kDifEntropySrcIrqEsEntropyValid, &irq_state));
EXPECT_EQ(irq_state, kDifToggleEnabled);
// Last IRQ is disabled.
irq_state = kDifToggleEnabled;
EXPECT_READ32(ENTROPY_SRC_INTR_ENABLE_REG_OFFSET,
{{ENTROPY_SRC_INTR_ENABLE_ES_FATAL_ERR_BIT, false}});
- EXPECT_EQ(dif_entropy_src_irq_get_enabled(
- &entropy_src_, kDifEntropySrcIrqEsFatalErr, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_entropy_src_irq_get_enabled(
+ &entropy_src_, kDifEntropySrcIrqEsFatalErr, &irq_state));
EXPECT_EQ(irq_state, kDifToggleDisabled);
}
@@ -270,18 +245,15 @@
TEST_F(IrqSetEnabledTest, NullArgs) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_entropy_src_irq_set_enabled(
- nullptr, kDifEntropySrcIrqEsEntropyValid, irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_entropy_src_irq_set_enabled(
+ nullptr, kDifEntropySrcIrqEsEntropyValid, irq_state));
}
TEST_F(IrqSetEnabledTest, BadIrq) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(
- dif_entropy_src_irq_set_enabled(
- &entropy_src_, static_cast<dif_entropy_src_irq_t>(32), irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_entropy_src_irq_set_enabled(
+ &entropy_src_, static_cast<dif_entropy_src_irq_t>(32), irq_state));
}
TEST_F(IrqSetEnabledTest, Success) {
@@ -291,17 +263,15 @@
irq_state = kDifToggleEnabled;
EXPECT_MASK32(ENTROPY_SRC_INTR_ENABLE_REG_OFFSET,
{{ENTROPY_SRC_INTR_ENABLE_ES_ENTROPY_VALID_BIT, 0x1, true}});
- EXPECT_EQ(dif_entropy_src_irq_set_enabled(
- &entropy_src_, kDifEntropySrcIrqEsEntropyValid, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_entropy_src_irq_set_enabled(
+ &entropy_src_, kDifEntropySrcIrqEsEntropyValid, irq_state));
// Disable last IRQ.
irq_state = kDifToggleDisabled;
EXPECT_MASK32(ENTROPY_SRC_INTR_ENABLE_REG_OFFSET,
{{ENTROPY_SRC_INTR_ENABLE_ES_FATAL_ERR_BIT, 0x1, false}});
- EXPECT_EQ(dif_entropy_src_irq_set_enabled(
- &entropy_src_, kDifEntropySrcIrqEsFatalErr, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_entropy_src_irq_set_enabled(
+ &entropy_src_, kDifEntropySrcIrqEsFatalErr, irq_state));
}
class IrqDisableAllTest : public EntropySrcTest {};
@@ -309,15 +279,14 @@
TEST_F(IrqDisableAllTest, NullArgs) {
dif_entropy_src_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_entropy_src_irq_disable_all(nullptr, &irq_snapshot),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_entropy_src_irq_disable_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_entropy_src_irq_disable_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_entropy_src_irq_disable_all(nullptr, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessNoSnapshot) {
EXPECT_WRITE32(ENTROPY_SRC_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_entropy_src_irq_disable_all(&entropy_src_, nullptr), kDifOk);
+ EXPECT_DIF_OK(dif_entropy_src_irq_disable_all(&entropy_src_, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessSnapshotAllDisabled) {
@@ -325,8 +294,7 @@
EXPECT_READ32(ENTROPY_SRC_INTR_ENABLE_REG_OFFSET, 0);
EXPECT_WRITE32(ENTROPY_SRC_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_entropy_src_irq_disable_all(&entropy_src_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(dif_entropy_src_irq_disable_all(&entropy_src_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -336,8 +304,7 @@
EXPECT_READ32(ENTROPY_SRC_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
EXPECT_WRITE32(ENTROPY_SRC_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_entropy_src_irq_disable_all(&entropy_src_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(dif_entropy_src_irq_disable_all(&entropy_src_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -346,13 +313,11 @@
TEST_F(IrqRestoreAllTest, NullArgs) {
dif_entropy_src_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_entropy_src_irq_restore_all(nullptr, &irq_snapshot),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_entropy_src_irq_restore_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_entropy_src_irq_restore_all(&entropy_src_, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_entropy_src_irq_restore_all(&entropy_src_, nullptr));
- EXPECT_EQ(dif_entropy_src_irq_restore_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_entropy_src_irq_restore_all(nullptr, nullptr));
}
TEST_F(IrqRestoreAllTest, SuccessAllEnabled) {
@@ -361,16 +326,14 @@
EXPECT_WRITE32(ENTROPY_SRC_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_entropy_src_irq_restore_all(&entropy_src_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(dif_entropy_src_irq_restore_all(&entropy_src_, &irq_snapshot));
}
TEST_F(IrqRestoreAllTest, SuccessAllDisabled) {
dif_entropy_src_irq_enable_snapshot_t irq_snapshot = 0;
EXPECT_WRITE32(ENTROPY_SRC_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_entropy_src_irq_restore_all(&entropy_src_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(dif_entropy_src_irq_restore_all(&entropy_src_, &irq_snapshot));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_flash_ctrl_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_flash_ctrl_autogen_unittest.cc
index f941091..8540e43 100644
--- a/sw/device/lib/dif/autogen/dif_flash_ctrl_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_flash_ctrl_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "flash_ctrl_regs.h" // Generated.
@@ -28,40 +29,37 @@
class InitTest : public FlashCtrlTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_flash_ctrl_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_flash_ctrl_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_flash_ctrl_init(dev().region(), &flash_ctrl_), kDifOk);
+ EXPECT_DIF_OK(dif_flash_ctrl_init(dev().region(), &flash_ctrl_));
}
class AlertForceTest : public FlashCtrlTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_flash_ctrl_alert_force(nullptr, kDifFlashCtrlAlertRecovErr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_flash_ctrl_alert_force(nullptr, kDifFlashCtrlAlertRecovErr));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(dif_flash_ctrl_alert_force(nullptr,
- static_cast<dif_flash_ctrl_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_flash_ctrl_alert_force(
+ nullptr, static_cast<dif_flash_ctrl_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(FLASH_CTRL_ALERT_TEST_REG_OFFSET,
{{FLASH_CTRL_ALERT_TEST_RECOV_ERR_BIT, true}});
- EXPECT_EQ(
- dif_flash_ctrl_alert_force(&flash_ctrl_, kDifFlashCtrlAlertRecovErr),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_flash_ctrl_alert_force(&flash_ctrl_, kDifFlashCtrlAlertRecovErr));
// Force last alert.
EXPECT_WRITE32(FLASH_CTRL_ALERT_TEST_REG_OFFSET,
{{FLASH_CTRL_ALERT_TEST_FATAL_ERR_BIT, true}});
- EXPECT_EQ(
- dif_flash_ctrl_alert_force(&flash_ctrl_, kDifFlashCtrlAlertFatalErr),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_flash_ctrl_alert_force(&flash_ctrl_, kDifFlashCtrlAlertFatalErr));
}
class IrqGetStateTest : public FlashCtrlTest {};
@@ -69,11 +67,11 @@
TEST_F(IrqGetStateTest, NullArgs) {
dif_flash_ctrl_irq_state_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_flash_ctrl_irq_get_state(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_flash_ctrl_irq_get_state(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_flash_ctrl_irq_get_state(&flash_ctrl_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_flash_ctrl_irq_get_state(&flash_ctrl_, nullptr));
- EXPECT_EQ(dif_flash_ctrl_irq_get_state(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_flash_ctrl_irq_get_state(nullptr, nullptr));
}
TEST_F(IrqGetStateTest, SuccessAllRaised) {
@@ -81,7 +79,7 @@
EXPECT_READ32(FLASH_CTRL_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_flash_ctrl_irq_get_state(&flash_ctrl_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_flash_ctrl_irq_get_state(&flash_ctrl_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -89,7 +87,7 @@
dif_flash_ctrl_irq_state_snapshot_t irq_snapshot = 0;
EXPECT_READ32(FLASH_CTRL_INTR_STATE_REG_OFFSET, 0);
- EXPECT_EQ(dif_flash_ctrl_irq_get_state(&flash_ctrl_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_flash_ctrl_irq_get_state(&flash_ctrl_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -98,26 +96,21 @@
TEST_F(IrqIsPendingTest, NullArgs) {
bool is_pending;
- EXPECT_EQ(dif_flash_ctrl_irq_is_pending(nullptr, kDifFlashCtrlIrqProgEmpty,
- &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_flash_ctrl_irq_is_pending(
+ nullptr, kDifFlashCtrlIrqProgEmpty, &is_pending));
- EXPECT_EQ(dif_flash_ctrl_irq_is_pending(&flash_ctrl_,
- kDifFlashCtrlIrqProgEmpty, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_flash_ctrl_irq_is_pending(
+ &flash_ctrl_, kDifFlashCtrlIrqProgEmpty, nullptr));
- EXPECT_EQ(dif_flash_ctrl_irq_is_pending(nullptr, kDifFlashCtrlIrqProgEmpty,
- nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_flash_ctrl_irq_is_pending(
+ nullptr, kDifFlashCtrlIrqProgEmpty, nullptr));
}
TEST_F(IrqIsPendingTest, BadIrq) {
bool is_pending;
// All interrupt CSRs are 32 bit so interrupt 32 will be invalid.
- EXPECT_EQ(
- dif_flash_ctrl_irq_is_pending(
- &flash_ctrl_, static_cast<dif_flash_ctrl_irq_t>(32), &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_flash_ctrl_irq_is_pending(
+ &flash_ctrl_, static_cast<dif_flash_ctrl_irq_t>(32), &is_pending));
}
TEST_F(IrqIsPendingTest, Success) {
@@ -127,88 +120,82 @@
irq_state = false;
EXPECT_READ32(FLASH_CTRL_INTR_STATE_REG_OFFSET,
{{FLASH_CTRL_INTR_STATE_PROG_EMPTY_BIT, true}});
- EXPECT_EQ(dif_flash_ctrl_irq_is_pending(
- &flash_ctrl_, kDifFlashCtrlIrqProgEmpty, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_flash_ctrl_irq_is_pending(
+ &flash_ctrl_, kDifFlashCtrlIrqProgEmpty, &irq_state));
EXPECT_TRUE(irq_state);
// Get the last IRQ state.
irq_state = true;
EXPECT_READ32(FLASH_CTRL_INTR_STATE_REG_OFFSET,
{{FLASH_CTRL_INTR_STATE_CORR_ERR_BIT, false}});
- EXPECT_EQ(dif_flash_ctrl_irq_is_pending(&flash_ctrl_, kDifFlashCtrlIrqCorrErr,
- &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_flash_ctrl_irq_is_pending(
+ &flash_ctrl_, kDifFlashCtrlIrqCorrErr, &irq_state));
EXPECT_FALSE(irq_state);
}
class AcknowledgeAllTest : public FlashCtrlTest {};
TEST_F(AcknowledgeAllTest, NullArgs) {
- EXPECT_EQ(dif_flash_ctrl_irq_acknowledge_all(nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_flash_ctrl_irq_acknowledge_all(nullptr));
}
TEST_F(AcknowledgeAllTest, Success) {
EXPECT_WRITE32(FLASH_CTRL_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_flash_ctrl_irq_acknowledge_all(&flash_ctrl_), kDifOk);
+ EXPECT_DIF_OK(dif_flash_ctrl_irq_acknowledge_all(&flash_ctrl_));
}
class IrqAcknowledgeTest : public FlashCtrlTest {};
TEST_F(IrqAcknowledgeTest, NullArgs) {
- EXPECT_EQ(dif_flash_ctrl_irq_acknowledge(nullptr, kDifFlashCtrlIrqProgEmpty),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_flash_ctrl_irq_acknowledge(nullptr, kDifFlashCtrlIrqProgEmpty));
}
TEST_F(IrqAcknowledgeTest, BadIrq) {
- EXPECT_EQ(dif_flash_ctrl_irq_acknowledge(
- nullptr, static_cast<dif_flash_ctrl_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_flash_ctrl_irq_acknowledge(
+ nullptr, static_cast<dif_flash_ctrl_irq_t>(32)));
}
TEST_F(IrqAcknowledgeTest, Success) {
// Clear the first IRQ state.
EXPECT_WRITE32(FLASH_CTRL_INTR_STATE_REG_OFFSET,
{{FLASH_CTRL_INTR_STATE_PROG_EMPTY_BIT, true}});
- EXPECT_EQ(
- dif_flash_ctrl_irq_acknowledge(&flash_ctrl_, kDifFlashCtrlIrqProgEmpty),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_flash_ctrl_irq_acknowledge(&flash_ctrl_, kDifFlashCtrlIrqProgEmpty));
// Clear the last IRQ state.
EXPECT_WRITE32(FLASH_CTRL_INTR_STATE_REG_OFFSET,
{{FLASH_CTRL_INTR_STATE_CORR_ERR_BIT, true}});
- EXPECT_EQ(
- dif_flash_ctrl_irq_acknowledge(&flash_ctrl_, kDifFlashCtrlIrqCorrErr),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_flash_ctrl_irq_acknowledge(&flash_ctrl_, kDifFlashCtrlIrqCorrErr));
}
class IrqForceTest : public FlashCtrlTest {};
TEST_F(IrqForceTest, NullArgs) {
- EXPECT_EQ(dif_flash_ctrl_irq_force(nullptr, kDifFlashCtrlIrqProgEmpty),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_flash_ctrl_irq_force(nullptr, kDifFlashCtrlIrqProgEmpty));
}
TEST_F(IrqForceTest, BadIrq) {
- EXPECT_EQ(
- dif_flash_ctrl_irq_force(nullptr, static_cast<dif_flash_ctrl_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_flash_ctrl_irq_force(nullptr, static_cast<dif_flash_ctrl_irq_t>(32)));
}
TEST_F(IrqForceTest, Success) {
// Force first IRQ.
EXPECT_WRITE32(FLASH_CTRL_INTR_TEST_REG_OFFSET,
{{FLASH_CTRL_INTR_TEST_PROG_EMPTY_BIT, true}});
- EXPECT_EQ(dif_flash_ctrl_irq_force(&flash_ctrl_, kDifFlashCtrlIrqProgEmpty),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_flash_ctrl_irq_force(&flash_ctrl_, kDifFlashCtrlIrqProgEmpty));
// Force last IRQ.
EXPECT_WRITE32(FLASH_CTRL_INTR_TEST_REG_OFFSET,
{{FLASH_CTRL_INTR_TEST_CORR_ERR_BIT, true}});
- EXPECT_EQ(dif_flash_ctrl_irq_force(&flash_ctrl_, kDifFlashCtrlIrqCorrErr),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_flash_ctrl_irq_force(&flash_ctrl_, kDifFlashCtrlIrqCorrErr));
}
class IrqGetEnabledTest : public FlashCtrlTest {};
@@ -216,26 +203,21 @@
TEST_F(IrqGetEnabledTest, NullArgs) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_flash_ctrl_irq_get_enabled(nullptr, kDifFlashCtrlIrqProgEmpty,
- &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_flash_ctrl_irq_get_enabled(
+ nullptr, kDifFlashCtrlIrqProgEmpty, &irq_state));
- EXPECT_EQ(dif_flash_ctrl_irq_get_enabled(&flash_ctrl_,
- kDifFlashCtrlIrqProgEmpty, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_flash_ctrl_irq_get_enabled(
+ &flash_ctrl_, kDifFlashCtrlIrqProgEmpty, nullptr));
- EXPECT_EQ(dif_flash_ctrl_irq_get_enabled(nullptr, kDifFlashCtrlIrqProgEmpty,
- nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_flash_ctrl_irq_get_enabled(
+ nullptr, kDifFlashCtrlIrqProgEmpty, nullptr));
}
TEST_F(IrqGetEnabledTest, BadIrq) {
dif_toggle_t irq_state;
- EXPECT_EQ(
- dif_flash_ctrl_irq_get_enabled(
- &flash_ctrl_, static_cast<dif_flash_ctrl_irq_t>(32), &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_flash_ctrl_irq_get_enabled(
+ &flash_ctrl_, static_cast<dif_flash_ctrl_irq_t>(32), &irq_state));
}
TEST_F(IrqGetEnabledTest, Success) {
@@ -245,18 +227,16 @@
irq_state = kDifToggleDisabled;
EXPECT_READ32(FLASH_CTRL_INTR_ENABLE_REG_OFFSET,
{{FLASH_CTRL_INTR_ENABLE_PROG_EMPTY_BIT, true}});
- EXPECT_EQ(dif_flash_ctrl_irq_get_enabled(
- &flash_ctrl_, kDifFlashCtrlIrqProgEmpty, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_flash_ctrl_irq_get_enabled(
+ &flash_ctrl_, kDifFlashCtrlIrqProgEmpty, &irq_state));
EXPECT_EQ(irq_state, kDifToggleEnabled);
// Last IRQ is disabled.
irq_state = kDifToggleEnabled;
EXPECT_READ32(FLASH_CTRL_INTR_ENABLE_REG_OFFSET,
{{FLASH_CTRL_INTR_ENABLE_CORR_ERR_BIT, false}});
- EXPECT_EQ(dif_flash_ctrl_irq_get_enabled(&flash_ctrl_,
- kDifFlashCtrlIrqCorrErr, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_flash_ctrl_irq_get_enabled(
+ &flash_ctrl_, kDifFlashCtrlIrqCorrErr, &irq_state));
EXPECT_EQ(irq_state, kDifToggleDisabled);
}
@@ -265,17 +245,15 @@
TEST_F(IrqSetEnabledTest, NullArgs) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_flash_ctrl_irq_set_enabled(nullptr, kDifFlashCtrlIrqProgEmpty,
- irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_flash_ctrl_irq_set_enabled(
+ nullptr, kDifFlashCtrlIrqProgEmpty, irq_state));
}
TEST_F(IrqSetEnabledTest, BadIrq) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_flash_ctrl_irq_set_enabled(
- &flash_ctrl_, static_cast<dif_flash_ctrl_irq_t>(32), irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_flash_ctrl_irq_set_enabled(
+ &flash_ctrl_, static_cast<dif_flash_ctrl_irq_t>(32), irq_state));
}
TEST_F(IrqSetEnabledTest, Success) {
@@ -285,17 +263,15 @@
irq_state = kDifToggleEnabled;
EXPECT_MASK32(FLASH_CTRL_INTR_ENABLE_REG_OFFSET,
{{FLASH_CTRL_INTR_ENABLE_PROG_EMPTY_BIT, 0x1, true}});
- EXPECT_EQ(dif_flash_ctrl_irq_set_enabled(
- &flash_ctrl_, kDifFlashCtrlIrqProgEmpty, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_flash_ctrl_irq_set_enabled(
+ &flash_ctrl_, kDifFlashCtrlIrqProgEmpty, irq_state));
// Disable last IRQ.
irq_state = kDifToggleDisabled;
EXPECT_MASK32(FLASH_CTRL_INTR_ENABLE_REG_OFFSET,
{{FLASH_CTRL_INTR_ENABLE_CORR_ERR_BIT, 0x1, false}});
- EXPECT_EQ(dif_flash_ctrl_irq_set_enabled(&flash_ctrl_,
- kDifFlashCtrlIrqCorrErr, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_flash_ctrl_irq_set_enabled(
+ &flash_ctrl_, kDifFlashCtrlIrqCorrErr, irq_state));
}
class IrqDisableAllTest : public FlashCtrlTest {};
@@ -303,14 +279,14 @@
TEST_F(IrqDisableAllTest, NullArgs) {
dif_flash_ctrl_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_flash_ctrl_irq_disable_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_flash_ctrl_irq_disable_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_flash_ctrl_irq_disable_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_flash_ctrl_irq_disable_all(nullptr, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessNoSnapshot) {
EXPECT_WRITE32(FLASH_CTRL_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_flash_ctrl_irq_disable_all(&flash_ctrl_, nullptr), kDifOk);
+ EXPECT_DIF_OK(dif_flash_ctrl_irq_disable_all(&flash_ctrl_, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessSnapshotAllDisabled) {
@@ -318,8 +294,7 @@
EXPECT_READ32(FLASH_CTRL_INTR_ENABLE_REG_OFFSET, 0);
EXPECT_WRITE32(FLASH_CTRL_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_flash_ctrl_irq_disable_all(&flash_ctrl_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(dif_flash_ctrl_irq_disable_all(&flash_ctrl_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -329,8 +304,7 @@
EXPECT_READ32(FLASH_CTRL_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
EXPECT_WRITE32(FLASH_CTRL_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_flash_ctrl_irq_disable_all(&flash_ctrl_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(dif_flash_ctrl_irq_disable_all(&flash_ctrl_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -339,11 +313,11 @@
TEST_F(IrqRestoreAllTest, NullArgs) {
dif_flash_ctrl_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_flash_ctrl_irq_restore_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_flash_ctrl_irq_restore_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_flash_ctrl_irq_restore_all(&flash_ctrl_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_flash_ctrl_irq_restore_all(&flash_ctrl_, nullptr));
- EXPECT_EQ(dif_flash_ctrl_irq_restore_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_flash_ctrl_irq_restore_all(nullptr, nullptr));
}
TEST_F(IrqRestoreAllTest, SuccessAllEnabled) {
@@ -352,16 +326,14 @@
EXPECT_WRITE32(FLASH_CTRL_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_flash_ctrl_irq_restore_all(&flash_ctrl_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(dif_flash_ctrl_irq_restore_all(&flash_ctrl_, &irq_snapshot));
}
TEST_F(IrqRestoreAllTest, SuccessAllDisabled) {
dif_flash_ctrl_irq_enable_snapshot_t irq_snapshot = 0;
EXPECT_WRITE32(FLASH_CTRL_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_flash_ctrl_irq_restore_all(&flash_ctrl_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(dif_flash_ctrl_irq_restore_all(&flash_ctrl_, &irq_snapshot));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_gpio_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_gpio_autogen_unittest.cc
index 5fa10c2..5fc048b 100644
--- a/sw/device/lib/dif/autogen/dif_gpio_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_gpio_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "gpio_regs.h" // Generated.
@@ -28,29 +29,29 @@
class InitTest : public GpioTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_gpio_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_gpio_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_gpio_init(dev().region(), &gpio_), kDifOk);
+ EXPECT_DIF_OK(dif_gpio_init(dev().region(), &gpio_));
}
class AlertForceTest : public GpioTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_gpio_alert_force(nullptr, kDifGpioAlertFatalFault), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_gpio_alert_force(nullptr, kDifGpioAlertFatalFault));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(dif_gpio_alert_force(nullptr, static_cast<dif_gpio_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_gpio_alert_force(nullptr, static_cast<dif_gpio_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(GPIO_ALERT_TEST_REG_OFFSET,
{{GPIO_ALERT_TEST_FATAL_FAULT_BIT, true}});
- EXPECT_EQ(dif_gpio_alert_force(&gpio_, kDifGpioAlertFatalFault), kDifOk);
+ EXPECT_DIF_OK(dif_gpio_alert_force(&gpio_, kDifGpioAlertFatalFault));
}
class IrqGetStateTest : public GpioTest {};
@@ -58,11 +59,11 @@
TEST_F(IrqGetStateTest, NullArgs) {
dif_gpio_irq_state_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_gpio_irq_get_state(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_gpio_irq_get_state(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_gpio_irq_get_state(&gpio_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_gpio_irq_get_state(&gpio_, nullptr));
- EXPECT_EQ(dif_gpio_irq_get_state(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_gpio_irq_get_state(nullptr, nullptr));
}
TEST_F(IrqGetStateTest, SuccessAllRaised) {
@@ -70,7 +71,7 @@
EXPECT_READ32(GPIO_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_gpio_irq_get_state(&gpio_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_gpio_irq_get_state(&gpio_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -78,7 +79,7 @@
dif_gpio_irq_state_snapshot_t irq_snapshot = 0;
EXPECT_READ32(GPIO_INTR_STATE_REG_OFFSET, 0);
- EXPECT_EQ(dif_gpio_irq_get_state(&gpio_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_gpio_irq_get_state(&gpio_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -87,22 +88,20 @@
TEST_F(IrqIsPendingTest, NullArgs) {
bool is_pending;
- EXPECT_EQ(dif_gpio_irq_is_pending(nullptr, kDifGpioIrqGpio0, &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_gpio_irq_is_pending(nullptr, kDifGpioIrqGpio0, &is_pending));
- EXPECT_EQ(dif_gpio_irq_is_pending(&gpio_, kDifGpioIrqGpio0, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_gpio_irq_is_pending(&gpio_, kDifGpioIrqGpio0, nullptr));
- EXPECT_EQ(dif_gpio_irq_is_pending(nullptr, kDifGpioIrqGpio0, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_gpio_irq_is_pending(nullptr, kDifGpioIrqGpio0, nullptr));
}
TEST_F(IrqIsPendingTest, BadIrq) {
bool is_pending;
// All interrupt CSRs are 32 bit so interrupt 32 will be invalid.
- EXPECT_EQ(dif_gpio_irq_is_pending(&gpio_, static_cast<dif_gpio_irq_t>(32),
- &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_gpio_irq_is_pending(
+ &gpio_, static_cast<dif_gpio_irq_t>(32), &is_pending));
}
TEST_F(IrqIsPendingTest, Success) {
@@ -111,71 +110,69 @@
// Get the first IRQ state.
irq_state = false;
EXPECT_READ32(GPIO_INTR_STATE_REG_OFFSET, {{0, true}});
- EXPECT_EQ(dif_gpio_irq_is_pending(&gpio_, kDifGpioIrqGpio0, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_gpio_irq_is_pending(&gpio_, kDifGpioIrqGpio0, &irq_state));
EXPECT_TRUE(irq_state);
// Get the last IRQ state.
irq_state = true;
EXPECT_READ32(GPIO_INTR_STATE_REG_OFFSET, {{31, false}});
- EXPECT_EQ(dif_gpio_irq_is_pending(&gpio_, kDifGpioIrqGpio31, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_gpio_irq_is_pending(&gpio_, kDifGpioIrqGpio31, &irq_state));
EXPECT_FALSE(irq_state);
}
class AcknowledgeAllTest : public GpioTest {};
TEST_F(AcknowledgeAllTest, NullArgs) {
- EXPECT_EQ(dif_gpio_irq_acknowledge_all(nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_gpio_irq_acknowledge_all(nullptr));
}
TEST_F(AcknowledgeAllTest, Success) {
EXPECT_WRITE32(GPIO_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_gpio_irq_acknowledge_all(&gpio_), kDifOk);
+ EXPECT_DIF_OK(dif_gpio_irq_acknowledge_all(&gpio_));
}
class IrqAcknowledgeTest : public GpioTest {};
TEST_F(IrqAcknowledgeTest, NullArgs) {
- EXPECT_EQ(dif_gpio_irq_acknowledge(nullptr, kDifGpioIrqGpio0), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_gpio_irq_acknowledge(nullptr, kDifGpioIrqGpio0));
}
TEST_F(IrqAcknowledgeTest, BadIrq) {
- EXPECT_EQ(dif_gpio_irq_acknowledge(nullptr, static_cast<dif_gpio_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_gpio_irq_acknowledge(nullptr, static_cast<dif_gpio_irq_t>(32)));
}
TEST_F(IrqAcknowledgeTest, Success) {
// Clear the first IRQ state.
EXPECT_WRITE32(GPIO_INTR_STATE_REG_OFFSET, {{0, true}});
- EXPECT_EQ(dif_gpio_irq_acknowledge(&gpio_, kDifGpioIrqGpio0), kDifOk);
+ EXPECT_DIF_OK(dif_gpio_irq_acknowledge(&gpio_, kDifGpioIrqGpio0));
// Clear the last IRQ state.
EXPECT_WRITE32(GPIO_INTR_STATE_REG_OFFSET, {{31, true}});
- EXPECT_EQ(dif_gpio_irq_acknowledge(&gpio_, kDifGpioIrqGpio31), kDifOk);
+ EXPECT_DIF_OK(dif_gpio_irq_acknowledge(&gpio_, kDifGpioIrqGpio31));
}
class IrqForceTest : public GpioTest {};
TEST_F(IrqForceTest, NullArgs) {
- EXPECT_EQ(dif_gpio_irq_force(nullptr, kDifGpioIrqGpio0), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_gpio_irq_force(nullptr, kDifGpioIrqGpio0));
}
TEST_F(IrqForceTest, BadIrq) {
- EXPECT_EQ(dif_gpio_irq_force(nullptr, static_cast<dif_gpio_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_gpio_irq_force(nullptr, static_cast<dif_gpio_irq_t>(32)));
}
TEST_F(IrqForceTest, Success) {
// Force first IRQ.
EXPECT_WRITE32(GPIO_INTR_TEST_REG_OFFSET, {{0, true}});
- EXPECT_EQ(dif_gpio_irq_force(&gpio_, kDifGpioIrqGpio0), kDifOk);
+ EXPECT_DIF_OK(dif_gpio_irq_force(&gpio_, kDifGpioIrqGpio0));
// Force last IRQ.
EXPECT_WRITE32(GPIO_INTR_TEST_REG_OFFSET, {{31, true}});
- EXPECT_EQ(dif_gpio_irq_force(&gpio_, kDifGpioIrqGpio31), kDifOk);
+ EXPECT_DIF_OK(dif_gpio_irq_force(&gpio_, kDifGpioIrqGpio31));
}
class IrqGetEnabledTest : public GpioTest {};
@@ -183,22 +180,21 @@
TEST_F(IrqGetEnabledTest, NullArgs) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_gpio_irq_get_enabled(nullptr, kDifGpioIrqGpio0, &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_gpio_irq_get_enabled(nullptr, kDifGpioIrqGpio0, &irq_state));
- EXPECT_EQ(dif_gpio_irq_get_enabled(&gpio_, kDifGpioIrqGpio0, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_gpio_irq_get_enabled(&gpio_, kDifGpioIrqGpio0, nullptr));
- EXPECT_EQ(dif_gpio_irq_get_enabled(nullptr, kDifGpioIrqGpio0, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_gpio_irq_get_enabled(nullptr, kDifGpioIrqGpio0, nullptr));
}
TEST_F(IrqGetEnabledTest, BadIrq) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_gpio_irq_get_enabled(&gpio_, static_cast<dif_gpio_irq_t>(32),
- &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_gpio_irq_get_enabled(
+ &gpio_, static_cast<dif_gpio_irq_t>(32), &irq_state));
}
TEST_F(IrqGetEnabledTest, Success) {
@@ -207,15 +203,14 @@
// First IRQ is enabled.
irq_state = kDifToggleDisabled;
EXPECT_READ32(GPIO_INTR_ENABLE_REG_OFFSET, {{0, true}});
- EXPECT_EQ(dif_gpio_irq_get_enabled(&gpio_, kDifGpioIrqGpio0, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_gpio_irq_get_enabled(&gpio_, kDifGpioIrqGpio0, &irq_state));
EXPECT_EQ(irq_state, kDifToggleEnabled);
// Last IRQ is disabled.
irq_state = kDifToggleEnabled;
EXPECT_READ32(GPIO_INTR_ENABLE_REG_OFFSET, {{31, false}});
- EXPECT_EQ(dif_gpio_irq_get_enabled(&gpio_, kDifGpioIrqGpio31, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_gpio_irq_get_enabled(&gpio_, kDifGpioIrqGpio31, &irq_state));
EXPECT_EQ(irq_state, kDifToggleDisabled);
}
@@ -224,16 +219,15 @@
TEST_F(IrqSetEnabledTest, NullArgs) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_gpio_irq_set_enabled(nullptr, kDifGpioIrqGpio0, irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_gpio_irq_set_enabled(nullptr, kDifGpioIrqGpio0, irq_state));
}
TEST_F(IrqSetEnabledTest, BadIrq) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_gpio_irq_set_enabled(&gpio_, static_cast<dif_gpio_irq_t>(32),
- irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_gpio_irq_set_enabled(
+ &gpio_, static_cast<dif_gpio_irq_t>(32), irq_state));
}
TEST_F(IrqSetEnabledTest, Success) {
@@ -242,14 +236,12 @@
// Enable first IRQ.
irq_state = kDifToggleEnabled;
EXPECT_MASK32(GPIO_INTR_ENABLE_REG_OFFSET, {{0, 0x1, true}});
- EXPECT_EQ(dif_gpio_irq_set_enabled(&gpio_, kDifGpioIrqGpio0, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_gpio_irq_set_enabled(&gpio_, kDifGpioIrqGpio0, irq_state));
// Disable last IRQ.
irq_state = kDifToggleDisabled;
EXPECT_MASK32(GPIO_INTR_ENABLE_REG_OFFSET, {{31, 0x1, false}});
- EXPECT_EQ(dif_gpio_irq_set_enabled(&gpio_, kDifGpioIrqGpio31, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_gpio_irq_set_enabled(&gpio_, kDifGpioIrqGpio31, irq_state));
}
class IrqDisableAllTest : public GpioTest {};
@@ -257,14 +249,14 @@
TEST_F(IrqDisableAllTest, NullArgs) {
dif_gpio_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_gpio_irq_disable_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_gpio_irq_disable_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_gpio_irq_disable_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_gpio_irq_disable_all(nullptr, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessNoSnapshot) {
EXPECT_WRITE32(GPIO_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_gpio_irq_disable_all(&gpio_, nullptr), kDifOk);
+ EXPECT_DIF_OK(dif_gpio_irq_disable_all(&gpio_, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessSnapshotAllDisabled) {
@@ -272,7 +264,7 @@
EXPECT_READ32(GPIO_INTR_ENABLE_REG_OFFSET, 0);
EXPECT_WRITE32(GPIO_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_gpio_irq_disable_all(&gpio_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_gpio_irq_disable_all(&gpio_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -282,7 +274,7 @@
EXPECT_READ32(GPIO_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
EXPECT_WRITE32(GPIO_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_gpio_irq_disable_all(&gpio_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_gpio_irq_disable_all(&gpio_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -291,11 +283,11 @@
TEST_F(IrqRestoreAllTest, NullArgs) {
dif_gpio_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_gpio_irq_restore_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_gpio_irq_restore_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_gpio_irq_restore_all(&gpio_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_gpio_irq_restore_all(&gpio_, nullptr));
- EXPECT_EQ(dif_gpio_irq_restore_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_gpio_irq_restore_all(nullptr, nullptr));
}
TEST_F(IrqRestoreAllTest, SuccessAllEnabled) {
@@ -304,14 +296,14 @@
EXPECT_WRITE32(GPIO_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_gpio_irq_restore_all(&gpio_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_gpio_irq_restore_all(&gpio_, &irq_snapshot));
}
TEST_F(IrqRestoreAllTest, SuccessAllDisabled) {
dif_gpio_irq_enable_snapshot_t irq_snapshot = 0;
EXPECT_WRITE32(GPIO_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_gpio_irq_restore_all(&gpio_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_gpio_irq_restore_all(&gpio_, &irq_snapshot));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_hmac_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_hmac_autogen_unittest.cc
index 6d71db1..61eaf5a 100644
--- a/sw/device/lib/dif/autogen/dif_hmac_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_hmac_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "hmac_regs.h" // Generated.
@@ -28,29 +29,29 @@
class InitTest : public HmacTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_hmac_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_hmac_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_hmac_init(dev().region(), &hmac_), kDifOk);
+ EXPECT_DIF_OK(dif_hmac_init(dev().region(), &hmac_));
}
class AlertForceTest : public HmacTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_hmac_alert_force(nullptr, kDifHmacAlertFatalFault), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_hmac_alert_force(nullptr, kDifHmacAlertFatalFault));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(dif_hmac_alert_force(nullptr, static_cast<dif_hmac_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_hmac_alert_force(nullptr, static_cast<dif_hmac_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(HMAC_ALERT_TEST_REG_OFFSET,
{{HMAC_ALERT_TEST_FATAL_FAULT_BIT, true}});
- EXPECT_EQ(dif_hmac_alert_force(&hmac_, kDifHmacAlertFatalFault), kDifOk);
+ EXPECT_DIF_OK(dif_hmac_alert_force(&hmac_, kDifHmacAlertFatalFault));
}
class IrqGetStateTest : public HmacTest {};
@@ -58,11 +59,11 @@
TEST_F(IrqGetStateTest, NullArgs) {
dif_hmac_irq_state_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_hmac_irq_get_state(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_hmac_irq_get_state(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_hmac_irq_get_state(&hmac_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_hmac_irq_get_state(&hmac_, nullptr));
- EXPECT_EQ(dif_hmac_irq_get_state(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_hmac_irq_get_state(nullptr, nullptr));
}
TEST_F(IrqGetStateTest, SuccessAllRaised) {
@@ -70,7 +71,7 @@
EXPECT_READ32(HMAC_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_hmac_irq_get_state(&hmac_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_hmac_irq_get_state(&hmac_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -78,7 +79,7 @@
dif_hmac_irq_state_snapshot_t irq_snapshot = 0;
EXPECT_READ32(HMAC_INTR_STATE_REG_OFFSET, 0);
- EXPECT_EQ(dif_hmac_irq_get_state(&hmac_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_hmac_irq_get_state(&hmac_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -87,22 +88,21 @@
TEST_F(IrqIsPendingTest, NullArgs) {
bool is_pending;
- EXPECT_EQ(dif_hmac_irq_is_pending(nullptr, kDifHmacIrqHmacDone, &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_hmac_irq_is_pending(nullptr, kDifHmacIrqHmacDone, &is_pending));
- EXPECT_EQ(dif_hmac_irq_is_pending(&hmac_, kDifHmacIrqHmacDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_hmac_irq_is_pending(&hmac_, kDifHmacIrqHmacDone, nullptr));
- EXPECT_EQ(dif_hmac_irq_is_pending(nullptr, kDifHmacIrqHmacDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_hmac_irq_is_pending(nullptr, kDifHmacIrqHmacDone, nullptr));
}
TEST_F(IrqIsPendingTest, BadIrq) {
bool is_pending;
// All interrupt CSRs are 32 bit so interrupt 32 will be invalid.
- EXPECT_EQ(dif_hmac_irq_is_pending(&hmac_, static_cast<dif_hmac_irq_t>(32),
- &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_hmac_irq_is_pending(
+ &hmac_, static_cast<dif_hmac_irq_t>(32), &is_pending));
}
TEST_F(IrqIsPendingTest, Success) {
@@ -112,76 +112,76 @@
irq_state = false;
EXPECT_READ32(HMAC_INTR_STATE_REG_OFFSET,
{{HMAC_INTR_STATE_HMAC_DONE_BIT, true}});
- EXPECT_EQ(dif_hmac_irq_is_pending(&hmac_, kDifHmacIrqHmacDone, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_hmac_irq_is_pending(&hmac_, kDifHmacIrqHmacDone, &irq_state));
EXPECT_TRUE(irq_state);
// Get the last IRQ state.
irq_state = true;
EXPECT_READ32(HMAC_INTR_STATE_REG_OFFSET,
{{HMAC_INTR_STATE_HMAC_ERR_BIT, false}});
- EXPECT_EQ(dif_hmac_irq_is_pending(&hmac_, kDifHmacIrqHmacErr, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_hmac_irq_is_pending(&hmac_, kDifHmacIrqHmacErr, &irq_state));
EXPECT_FALSE(irq_state);
}
class AcknowledgeAllTest : public HmacTest {};
TEST_F(AcknowledgeAllTest, NullArgs) {
- EXPECT_EQ(dif_hmac_irq_acknowledge_all(nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_hmac_irq_acknowledge_all(nullptr));
}
TEST_F(AcknowledgeAllTest, Success) {
EXPECT_WRITE32(HMAC_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_hmac_irq_acknowledge_all(&hmac_), kDifOk);
+ EXPECT_DIF_OK(dif_hmac_irq_acknowledge_all(&hmac_));
}
class IrqAcknowledgeTest : public HmacTest {};
TEST_F(IrqAcknowledgeTest, NullArgs) {
- EXPECT_EQ(dif_hmac_irq_acknowledge(nullptr, kDifHmacIrqHmacDone), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_hmac_irq_acknowledge(nullptr, kDifHmacIrqHmacDone));
}
TEST_F(IrqAcknowledgeTest, BadIrq) {
- EXPECT_EQ(dif_hmac_irq_acknowledge(nullptr, static_cast<dif_hmac_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_hmac_irq_acknowledge(nullptr, static_cast<dif_hmac_irq_t>(32)));
}
TEST_F(IrqAcknowledgeTest, Success) {
// Clear the first IRQ state.
EXPECT_WRITE32(HMAC_INTR_STATE_REG_OFFSET,
{{HMAC_INTR_STATE_HMAC_DONE_BIT, true}});
- EXPECT_EQ(dif_hmac_irq_acknowledge(&hmac_, kDifHmacIrqHmacDone), kDifOk);
+ EXPECT_DIF_OK(dif_hmac_irq_acknowledge(&hmac_, kDifHmacIrqHmacDone));
// Clear the last IRQ state.
EXPECT_WRITE32(HMAC_INTR_STATE_REG_OFFSET,
{{HMAC_INTR_STATE_HMAC_ERR_BIT, true}});
- EXPECT_EQ(dif_hmac_irq_acknowledge(&hmac_, kDifHmacIrqHmacErr), kDifOk);
+ EXPECT_DIF_OK(dif_hmac_irq_acknowledge(&hmac_, kDifHmacIrqHmacErr));
}
class IrqForceTest : public HmacTest {};
TEST_F(IrqForceTest, NullArgs) {
- EXPECT_EQ(dif_hmac_irq_force(nullptr, kDifHmacIrqHmacDone), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_hmac_irq_force(nullptr, kDifHmacIrqHmacDone));
}
TEST_F(IrqForceTest, BadIrq) {
- EXPECT_EQ(dif_hmac_irq_force(nullptr, static_cast<dif_hmac_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_hmac_irq_force(nullptr, static_cast<dif_hmac_irq_t>(32)));
}
TEST_F(IrqForceTest, Success) {
// Force first IRQ.
EXPECT_WRITE32(HMAC_INTR_TEST_REG_OFFSET,
{{HMAC_INTR_TEST_HMAC_DONE_BIT, true}});
- EXPECT_EQ(dif_hmac_irq_force(&hmac_, kDifHmacIrqHmacDone), kDifOk);
+ EXPECT_DIF_OK(dif_hmac_irq_force(&hmac_, kDifHmacIrqHmacDone));
// Force last IRQ.
EXPECT_WRITE32(HMAC_INTR_TEST_REG_OFFSET,
{{HMAC_INTR_TEST_HMAC_ERR_BIT, true}});
- EXPECT_EQ(dif_hmac_irq_force(&hmac_, kDifHmacIrqHmacErr), kDifOk);
+ EXPECT_DIF_OK(dif_hmac_irq_force(&hmac_, kDifHmacIrqHmacErr));
}
class IrqGetEnabledTest : public HmacTest {};
@@ -189,22 +189,21 @@
TEST_F(IrqGetEnabledTest, NullArgs) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_hmac_irq_get_enabled(nullptr, kDifHmacIrqHmacDone, &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_hmac_irq_get_enabled(nullptr, kDifHmacIrqHmacDone, &irq_state));
- EXPECT_EQ(dif_hmac_irq_get_enabled(&hmac_, kDifHmacIrqHmacDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_hmac_irq_get_enabled(&hmac_, kDifHmacIrqHmacDone, nullptr));
- EXPECT_EQ(dif_hmac_irq_get_enabled(nullptr, kDifHmacIrqHmacDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_hmac_irq_get_enabled(nullptr, kDifHmacIrqHmacDone, nullptr));
}
TEST_F(IrqGetEnabledTest, BadIrq) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_hmac_irq_get_enabled(&hmac_, static_cast<dif_hmac_irq_t>(32),
- &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_hmac_irq_get_enabled(
+ &hmac_, static_cast<dif_hmac_irq_t>(32), &irq_state));
}
TEST_F(IrqGetEnabledTest, Success) {
@@ -214,16 +213,16 @@
irq_state = kDifToggleDisabled;
EXPECT_READ32(HMAC_INTR_ENABLE_REG_OFFSET,
{{HMAC_INTR_ENABLE_HMAC_DONE_BIT, true}});
- EXPECT_EQ(dif_hmac_irq_get_enabled(&hmac_, kDifHmacIrqHmacDone, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_hmac_irq_get_enabled(&hmac_, kDifHmacIrqHmacDone, &irq_state));
EXPECT_EQ(irq_state, kDifToggleEnabled);
// Last IRQ is disabled.
irq_state = kDifToggleEnabled;
EXPECT_READ32(HMAC_INTR_ENABLE_REG_OFFSET,
{{HMAC_INTR_ENABLE_HMAC_ERR_BIT, false}});
- EXPECT_EQ(dif_hmac_irq_get_enabled(&hmac_, kDifHmacIrqHmacErr, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_hmac_irq_get_enabled(&hmac_, kDifHmacIrqHmacErr, &irq_state));
EXPECT_EQ(irq_state, kDifToggleDisabled);
}
@@ -232,16 +231,15 @@
TEST_F(IrqSetEnabledTest, NullArgs) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_hmac_irq_set_enabled(nullptr, kDifHmacIrqHmacDone, irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_hmac_irq_set_enabled(nullptr, kDifHmacIrqHmacDone, irq_state));
}
TEST_F(IrqSetEnabledTest, BadIrq) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_hmac_irq_set_enabled(&hmac_, static_cast<dif_hmac_irq_t>(32),
- irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_hmac_irq_set_enabled(
+ &hmac_, static_cast<dif_hmac_irq_t>(32), irq_state));
}
TEST_F(IrqSetEnabledTest, Success) {
@@ -251,15 +249,15 @@
irq_state = kDifToggleEnabled;
EXPECT_MASK32(HMAC_INTR_ENABLE_REG_OFFSET,
{{HMAC_INTR_ENABLE_HMAC_DONE_BIT, 0x1, true}});
- EXPECT_EQ(dif_hmac_irq_set_enabled(&hmac_, kDifHmacIrqHmacDone, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_hmac_irq_set_enabled(&hmac_, kDifHmacIrqHmacDone, irq_state));
// Disable last IRQ.
irq_state = kDifToggleDisabled;
EXPECT_MASK32(HMAC_INTR_ENABLE_REG_OFFSET,
{{HMAC_INTR_ENABLE_HMAC_ERR_BIT, 0x1, false}});
- EXPECT_EQ(dif_hmac_irq_set_enabled(&hmac_, kDifHmacIrqHmacErr, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_hmac_irq_set_enabled(&hmac_, kDifHmacIrqHmacErr, irq_state));
}
class IrqDisableAllTest : public HmacTest {};
@@ -267,14 +265,14 @@
TEST_F(IrqDisableAllTest, NullArgs) {
dif_hmac_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_hmac_irq_disable_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_hmac_irq_disable_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_hmac_irq_disable_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_hmac_irq_disable_all(nullptr, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessNoSnapshot) {
EXPECT_WRITE32(HMAC_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_hmac_irq_disable_all(&hmac_, nullptr), kDifOk);
+ EXPECT_DIF_OK(dif_hmac_irq_disable_all(&hmac_, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessSnapshotAllDisabled) {
@@ -282,7 +280,7 @@
EXPECT_READ32(HMAC_INTR_ENABLE_REG_OFFSET, 0);
EXPECT_WRITE32(HMAC_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_hmac_irq_disable_all(&hmac_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_hmac_irq_disable_all(&hmac_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -292,7 +290,7 @@
EXPECT_READ32(HMAC_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
EXPECT_WRITE32(HMAC_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_hmac_irq_disable_all(&hmac_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_hmac_irq_disable_all(&hmac_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -301,11 +299,11 @@
TEST_F(IrqRestoreAllTest, NullArgs) {
dif_hmac_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_hmac_irq_restore_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_hmac_irq_restore_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_hmac_irq_restore_all(&hmac_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_hmac_irq_restore_all(&hmac_, nullptr));
- EXPECT_EQ(dif_hmac_irq_restore_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_hmac_irq_restore_all(nullptr, nullptr));
}
TEST_F(IrqRestoreAllTest, SuccessAllEnabled) {
@@ -314,14 +312,14 @@
EXPECT_WRITE32(HMAC_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_hmac_irq_restore_all(&hmac_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_hmac_irq_restore_all(&hmac_, &irq_snapshot));
}
TEST_F(IrqRestoreAllTest, SuccessAllDisabled) {
dif_hmac_irq_enable_snapshot_t irq_snapshot = 0;
EXPECT_WRITE32(HMAC_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_hmac_irq_restore_all(&hmac_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_hmac_irq_restore_all(&hmac_, &irq_snapshot));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_i2c_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_i2c_autogen_unittest.cc
index 06d2490..f5258a1 100644
--- a/sw/device/lib/dif/autogen/dif_i2c_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_i2c_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "i2c_regs.h" // Generated.
@@ -28,29 +29,29 @@
class InitTest : public I2cTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_i2c_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_i2c_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_i2c_init(dev().region(), &i2c_), kDifOk);
+ EXPECT_DIF_OK(dif_i2c_init(dev().region(), &i2c_));
}
class AlertForceTest : public I2cTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_i2c_alert_force(nullptr, kDifI2cAlertFatalFault), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_i2c_alert_force(nullptr, kDifI2cAlertFatalFault));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(dif_i2c_alert_force(nullptr, static_cast<dif_i2c_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_i2c_alert_force(nullptr, static_cast<dif_i2c_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(I2C_ALERT_TEST_REG_OFFSET,
{{I2C_ALERT_TEST_FATAL_FAULT_BIT, true}});
- EXPECT_EQ(dif_i2c_alert_force(&i2c_, kDifI2cAlertFatalFault), kDifOk);
+ EXPECT_DIF_OK(dif_i2c_alert_force(&i2c_, kDifI2cAlertFatalFault));
}
class IrqGetStateTest : public I2cTest {};
@@ -58,11 +59,11 @@
TEST_F(IrqGetStateTest, NullArgs) {
dif_i2c_irq_state_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_i2c_irq_get_state(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_i2c_irq_get_state(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_i2c_irq_get_state(&i2c_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_i2c_irq_get_state(&i2c_, nullptr));
- EXPECT_EQ(dif_i2c_irq_get_state(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_i2c_irq_get_state(nullptr, nullptr));
}
TEST_F(IrqGetStateTest, SuccessAllRaised) {
@@ -70,7 +71,7 @@
EXPECT_READ32(I2C_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_i2c_irq_get_state(&i2c_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_i2c_irq_get_state(&i2c_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -78,7 +79,7 @@
dif_i2c_irq_state_snapshot_t irq_snapshot = 0;
EXPECT_READ32(I2C_INTR_STATE_REG_OFFSET, 0);
- EXPECT_EQ(dif_i2c_irq_get_state(&i2c_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_i2c_irq_get_state(&i2c_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -87,23 +88,21 @@
TEST_F(IrqIsPendingTest, NullArgs) {
bool is_pending;
- EXPECT_EQ(
- dif_i2c_irq_is_pending(nullptr, kDifI2cIrqFmtWatermark, &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_i2c_irq_is_pending(nullptr, kDifI2cIrqFmtWatermark, &is_pending));
- EXPECT_EQ(dif_i2c_irq_is_pending(&i2c_, kDifI2cIrqFmtWatermark, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_i2c_irq_is_pending(&i2c_, kDifI2cIrqFmtWatermark, nullptr));
- EXPECT_EQ(dif_i2c_irq_is_pending(nullptr, kDifI2cIrqFmtWatermark, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_i2c_irq_is_pending(nullptr, kDifI2cIrqFmtWatermark, nullptr));
}
TEST_F(IrqIsPendingTest, BadIrq) {
bool is_pending;
// All interrupt CSRs are 32 bit so interrupt 32 will be invalid.
- EXPECT_EQ(dif_i2c_irq_is_pending(&i2c_, static_cast<dif_i2c_irq_t>(32),
- &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_i2c_irq_is_pending(
+ &i2c_, static_cast<dif_i2c_irq_t>(32), &is_pending));
}
TEST_F(IrqIsPendingTest, Success) {
@@ -113,77 +112,75 @@
irq_state = false;
EXPECT_READ32(I2C_INTR_STATE_REG_OFFSET,
{{I2C_INTR_STATE_FMT_WATERMARK_BIT, true}});
- EXPECT_EQ(dif_i2c_irq_is_pending(&i2c_, kDifI2cIrqFmtWatermark, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_i2c_irq_is_pending(&i2c_, kDifI2cIrqFmtWatermark, &irq_state));
EXPECT_TRUE(irq_state);
// Get the last IRQ state.
irq_state = true;
EXPECT_READ32(I2C_INTR_STATE_REG_OFFSET,
{{I2C_INTR_STATE_HOST_TIMEOUT_BIT, false}});
- EXPECT_EQ(dif_i2c_irq_is_pending(&i2c_, kDifI2cIrqHostTimeout, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_i2c_irq_is_pending(&i2c_, kDifI2cIrqHostTimeout, &irq_state));
EXPECT_FALSE(irq_state);
}
class AcknowledgeAllTest : public I2cTest {};
TEST_F(AcknowledgeAllTest, NullArgs) {
- EXPECT_EQ(dif_i2c_irq_acknowledge_all(nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_i2c_irq_acknowledge_all(nullptr));
}
TEST_F(AcknowledgeAllTest, Success) {
EXPECT_WRITE32(I2C_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_i2c_irq_acknowledge_all(&i2c_), kDifOk);
+ EXPECT_DIF_OK(dif_i2c_irq_acknowledge_all(&i2c_));
}
class IrqAcknowledgeTest : public I2cTest {};
TEST_F(IrqAcknowledgeTest, NullArgs) {
- EXPECT_EQ(dif_i2c_irq_acknowledge(nullptr, kDifI2cIrqFmtWatermark),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_i2c_irq_acknowledge(nullptr, kDifI2cIrqFmtWatermark));
}
TEST_F(IrqAcknowledgeTest, BadIrq) {
- EXPECT_EQ(dif_i2c_irq_acknowledge(nullptr, static_cast<dif_i2c_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_i2c_irq_acknowledge(nullptr, static_cast<dif_i2c_irq_t>(32)));
}
TEST_F(IrqAcknowledgeTest, Success) {
// Clear the first IRQ state.
EXPECT_WRITE32(I2C_INTR_STATE_REG_OFFSET,
{{I2C_INTR_STATE_FMT_WATERMARK_BIT, true}});
- EXPECT_EQ(dif_i2c_irq_acknowledge(&i2c_, kDifI2cIrqFmtWatermark), kDifOk);
+ EXPECT_DIF_OK(dif_i2c_irq_acknowledge(&i2c_, kDifI2cIrqFmtWatermark));
// Clear the last IRQ state.
EXPECT_WRITE32(I2C_INTR_STATE_REG_OFFSET,
{{I2C_INTR_STATE_HOST_TIMEOUT_BIT, true}});
- EXPECT_EQ(dif_i2c_irq_acknowledge(&i2c_, kDifI2cIrqHostTimeout), kDifOk);
+ EXPECT_DIF_OK(dif_i2c_irq_acknowledge(&i2c_, kDifI2cIrqHostTimeout));
}
class IrqForceTest : public I2cTest {};
TEST_F(IrqForceTest, NullArgs) {
- EXPECT_EQ(dif_i2c_irq_force(nullptr, kDifI2cIrqFmtWatermark), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_i2c_irq_force(nullptr, kDifI2cIrqFmtWatermark));
}
TEST_F(IrqForceTest, BadIrq) {
- EXPECT_EQ(dif_i2c_irq_force(nullptr, static_cast<dif_i2c_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_i2c_irq_force(nullptr, static_cast<dif_i2c_irq_t>(32)));
}
TEST_F(IrqForceTest, Success) {
// Force first IRQ.
EXPECT_WRITE32(I2C_INTR_TEST_REG_OFFSET,
{{I2C_INTR_TEST_FMT_WATERMARK_BIT, true}});
- EXPECT_EQ(dif_i2c_irq_force(&i2c_, kDifI2cIrqFmtWatermark), kDifOk);
+ EXPECT_DIF_OK(dif_i2c_irq_force(&i2c_, kDifI2cIrqFmtWatermark));
// Force last IRQ.
EXPECT_WRITE32(I2C_INTR_TEST_REG_OFFSET,
{{I2C_INTR_TEST_HOST_TIMEOUT_BIT, true}});
- EXPECT_EQ(dif_i2c_irq_force(&i2c_, kDifI2cIrqHostTimeout), kDifOk);
+ EXPECT_DIF_OK(dif_i2c_irq_force(&i2c_, kDifI2cIrqHostTimeout));
}
class IrqGetEnabledTest : public I2cTest {};
@@ -191,23 +188,21 @@
TEST_F(IrqGetEnabledTest, NullArgs) {
dif_toggle_t irq_state;
- EXPECT_EQ(
- dif_i2c_irq_get_enabled(nullptr, kDifI2cIrqFmtWatermark, &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_i2c_irq_get_enabled(nullptr, kDifI2cIrqFmtWatermark, &irq_state));
- EXPECT_EQ(dif_i2c_irq_get_enabled(&i2c_, kDifI2cIrqFmtWatermark, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_i2c_irq_get_enabled(&i2c_, kDifI2cIrqFmtWatermark, nullptr));
- EXPECT_EQ(dif_i2c_irq_get_enabled(nullptr, kDifI2cIrqFmtWatermark, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_i2c_irq_get_enabled(nullptr, kDifI2cIrqFmtWatermark, nullptr));
}
TEST_F(IrqGetEnabledTest, BadIrq) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_i2c_irq_get_enabled(&i2c_, static_cast<dif_i2c_irq_t>(32),
- &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_i2c_irq_get_enabled(
+ &i2c_, static_cast<dif_i2c_irq_t>(32), &irq_state));
}
TEST_F(IrqGetEnabledTest, Success) {
@@ -217,16 +212,16 @@
irq_state = kDifToggleDisabled;
EXPECT_READ32(I2C_INTR_ENABLE_REG_OFFSET,
{{I2C_INTR_ENABLE_FMT_WATERMARK_BIT, true}});
- EXPECT_EQ(dif_i2c_irq_get_enabled(&i2c_, kDifI2cIrqFmtWatermark, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_i2c_irq_get_enabled(&i2c_, kDifI2cIrqFmtWatermark, &irq_state));
EXPECT_EQ(irq_state, kDifToggleEnabled);
// Last IRQ is disabled.
irq_state = kDifToggleEnabled;
EXPECT_READ32(I2C_INTR_ENABLE_REG_OFFSET,
{{I2C_INTR_ENABLE_HOST_TIMEOUT_BIT, false}});
- EXPECT_EQ(dif_i2c_irq_get_enabled(&i2c_, kDifI2cIrqHostTimeout, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_i2c_irq_get_enabled(&i2c_, kDifI2cIrqHostTimeout, &irq_state));
EXPECT_EQ(irq_state, kDifToggleDisabled);
}
@@ -235,16 +230,15 @@
TEST_F(IrqSetEnabledTest, NullArgs) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_i2c_irq_set_enabled(nullptr, kDifI2cIrqFmtWatermark, irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_i2c_irq_set_enabled(nullptr, kDifI2cIrqFmtWatermark, irq_state));
}
TEST_F(IrqSetEnabledTest, BadIrq) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(
- dif_i2c_irq_set_enabled(&i2c_, static_cast<dif_i2c_irq_t>(32), irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_i2c_irq_set_enabled(
+ &i2c_, static_cast<dif_i2c_irq_t>(32), irq_state));
}
TEST_F(IrqSetEnabledTest, Success) {
@@ -254,15 +248,15 @@
irq_state = kDifToggleEnabled;
EXPECT_MASK32(I2C_INTR_ENABLE_REG_OFFSET,
{{I2C_INTR_ENABLE_FMT_WATERMARK_BIT, 0x1, true}});
- EXPECT_EQ(dif_i2c_irq_set_enabled(&i2c_, kDifI2cIrqFmtWatermark, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_i2c_irq_set_enabled(&i2c_, kDifI2cIrqFmtWatermark, irq_state));
// Disable last IRQ.
irq_state = kDifToggleDisabled;
EXPECT_MASK32(I2C_INTR_ENABLE_REG_OFFSET,
{{I2C_INTR_ENABLE_HOST_TIMEOUT_BIT, 0x1, false}});
- EXPECT_EQ(dif_i2c_irq_set_enabled(&i2c_, kDifI2cIrqHostTimeout, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_i2c_irq_set_enabled(&i2c_, kDifI2cIrqHostTimeout, irq_state));
}
class IrqDisableAllTest : public I2cTest {};
@@ -270,14 +264,14 @@
TEST_F(IrqDisableAllTest, NullArgs) {
dif_i2c_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_i2c_irq_disable_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_i2c_irq_disable_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_i2c_irq_disable_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_i2c_irq_disable_all(nullptr, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessNoSnapshot) {
EXPECT_WRITE32(I2C_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_i2c_irq_disable_all(&i2c_, nullptr), kDifOk);
+ EXPECT_DIF_OK(dif_i2c_irq_disable_all(&i2c_, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessSnapshotAllDisabled) {
@@ -285,7 +279,7 @@
EXPECT_READ32(I2C_INTR_ENABLE_REG_OFFSET, 0);
EXPECT_WRITE32(I2C_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_i2c_irq_disable_all(&i2c_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_i2c_irq_disable_all(&i2c_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -295,7 +289,7 @@
EXPECT_READ32(I2C_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
EXPECT_WRITE32(I2C_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_i2c_irq_disable_all(&i2c_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_i2c_irq_disable_all(&i2c_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -304,11 +298,11 @@
TEST_F(IrqRestoreAllTest, NullArgs) {
dif_i2c_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_i2c_irq_restore_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_i2c_irq_restore_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_i2c_irq_restore_all(&i2c_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_i2c_irq_restore_all(&i2c_, nullptr));
- EXPECT_EQ(dif_i2c_irq_restore_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_i2c_irq_restore_all(nullptr, nullptr));
}
TEST_F(IrqRestoreAllTest, SuccessAllEnabled) {
@@ -317,14 +311,14 @@
EXPECT_WRITE32(I2C_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_i2c_irq_restore_all(&i2c_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_i2c_irq_restore_all(&i2c_, &irq_snapshot));
}
TEST_F(IrqRestoreAllTest, SuccessAllDisabled) {
dif_i2c_irq_enable_snapshot_t irq_snapshot = 0;
EXPECT_WRITE32(I2C_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_i2c_irq_restore_all(&i2c_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_i2c_irq_restore_all(&i2c_, &irq_snapshot));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_keymgr_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_keymgr_autogen_unittest.cc
index 316259e..3ebdf83 100644
--- a/sw/device/lib/dif/autogen/dif_keymgr_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_keymgr_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "keymgr_regs.h" // Generated.
@@ -28,38 +29,36 @@
class InitTest : public KeymgrTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_keymgr_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_keymgr_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_keymgr_init(dev().region(), &keymgr_), kDifOk);
+ EXPECT_DIF_OK(dif_keymgr_init(dev().region(), &keymgr_));
}
class AlertForceTest : public KeymgrTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_keymgr_alert_force(nullptr, kDifKeymgrAlertRecovOperationErr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_keymgr_alert_force(nullptr, kDifKeymgrAlertRecovOperationErr));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(
- dif_keymgr_alert_force(nullptr, static_cast<dif_keymgr_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_keymgr_alert_force(nullptr, static_cast<dif_keymgr_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(KEYMGR_ALERT_TEST_REG_OFFSET,
{{KEYMGR_ALERT_TEST_RECOV_OPERATION_ERR_BIT, true}});
- EXPECT_EQ(dif_keymgr_alert_force(&keymgr_, kDifKeymgrAlertRecovOperationErr),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_keymgr_alert_force(&keymgr_, kDifKeymgrAlertRecovOperationErr));
// Force last alert.
EXPECT_WRITE32(KEYMGR_ALERT_TEST_REG_OFFSET,
{{KEYMGR_ALERT_TEST_FATAL_FAULT_ERR_BIT, true}});
- EXPECT_EQ(dif_keymgr_alert_force(&keymgr_, kDifKeymgrAlertFatalFaultErr),
- kDifOk);
+ EXPECT_DIF_OK(dif_keymgr_alert_force(&keymgr_, kDifKeymgrAlertFatalFaultErr));
}
class IrqGetStateTest : public KeymgrTest {};
@@ -67,11 +66,11 @@
TEST_F(IrqGetStateTest, NullArgs) {
dif_keymgr_irq_state_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_keymgr_irq_get_state(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_keymgr_irq_get_state(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_keymgr_irq_get_state(&keymgr_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_keymgr_irq_get_state(&keymgr_, nullptr));
- EXPECT_EQ(dif_keymgr_irq_get_state(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_keymgr_irq_get_state(nullptr, nullptr));
}
TEST_F(IrqGetStateTest, SuccessAllRaised) {
@@ -79,7 +78,7 @@
EXPECT_READ32(KEYMGR_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_keymgr_irq_get_state(&keymgr_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_keymgr_irq_get_state(&keymgr_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -87,7 +86,7 @@
dif_keymgr_irq_state_snapshot_t irq_snapshot = 0;
EXPECT_READ32(KEYMGR_INTR_STATE_REG_OFFSET, 0);
- EXPECT_EQ(dif_keymgr_irq_get_state(&keymgr_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_keymgr_irq_get_state(&keymgr_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -96,23 +95,21 @@
TEST_F(IrqIsPendingTest, NullArgs) {
bool is_pending;
- EXPECT_EQ(
- dif_keymgr_irq_is_pending(nullptr, kDifKeymgrIrqOpDone, &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_keymgr_irq_is_pending(nullptr, kDifKeymgrIrqOpDone, &is_pending));
- EXPECT_EQ(dif_keymgr_irq_is_pending(&keymgr_, kDifKeymgrIrqOpDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_keymgr_irq_is_pending(&keymgr_, kDifKeymgrIrqOpDone, nullptr));
- EXPECT_EQ(dif_keymgr_irq_is_pending(nullptr, kDifKeymgrIrqOpDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_keymgr_irq_is_pending(nullptr, kDifKeymgrIrqOpDone, nullptr));
}
TEST_F(IrqIsPendingTest, BadIrq) {
bool is_pending;
// All interrupt CSRs are 32 bit so interrupt 32 will be invalid.
- EXPECT_EQ(dif_keymgr_irq_is_pending(
- &keymgr_, static_cast<dif_keymgr_irq_t>(32), &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_keymgr_irq_is_pending(
+ &keymgr_, static_cast<dif_keymgr_irq_t>(32), &is_pending));
}
TEST_F(IrqIsPendingTest, Success) {
@@ -122,61 +119,58 @@
irq_state = false;
EXPECT_READ32(KEYMGR_INTR_STATE_REG_OFFSET,
{{KEYMGR_INTR_STATE_OP_DONE_BIT, true}});
- EXPECT_EQ(
- dif_keymgr_irq_is_pending(&keymgr_, kDifKeymgrIrqOpDone, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_keymgr_irq_is_pending(&keymgr_, kDifKeymgrIrqOpDone, &irq_state));
EXPECT_TRUE(irq_state);
}
class AcknowledgeAllTest : public KeymgrTest {};
TEST_F(AcknowledgeAllTest, NullArgs) {
- EXPECT_EQ(dif_keymgr_irq_acknowledge_all(nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_keymgr_irq_acknowledge_all(nullptr));
}
TEST_F(AcknowledgeAllTest, Success) {
EXPECT_WRITE32(KEYMGR_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_keymgr_irq_acknowledge_all(&keymgr_), kDifOk);
+ EXPECT_DIF_OK(dif_keymgr_irq_acknowledge_all(&keymgr_));
}
class IrqAcknowledgeTest : public KeymgrTest {};
TEST_F(IrqAcknowledgeTest, NullArgs) {
- EXPECT_EQ(dif_keymgr_irq_acknowledge(nullptr, kDifKeymgrIrqOpDone),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_keymgr_irq_acknowledge(nullptr, kDifKeymgrIrqOpDone));
}
TEST_F(IrqAcknowledgeTest, BadIrq) {
- EXPECT_EQ(
- dif_keymgr_irq_acknowledge(nullptr, static_cast<dif_keymgr_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_keymgr_irq_acknowledge(nullptr, static_cast<dif_keymgr_irq_t>(32)));
}
TEST_F(IrqAcknowledgeTest, Success) {
// Clear the first IRQ state.
EXPECT_WRITE32(KEYMGR_INTR_STATE_REG_OFFSET,
{{KEYMGR_INTR_STATE_OP_DONE_BIT, true}});
- EXPECT_EQ(dif_keymgr_irq_acknowledge(&keymgr_, kDifKeymgrIrqOpDone), kDifOk);
+ EXPECT_DIF_OK(dif_keymgr_irq_acknowledge(&keymgr_, kDifKeymgrIrqOpDone));
}
class IrqForceTest : public KeymgrTest {};
TEST_F(IrqForceTest, NullArgs) {
- EXPECT_EQ(dif_keymgr_irq_force(nullptr, kDifKeymgrIrqOpDone), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_keymgr_irq_force(nullptr, kDifKeymgrIrqOpDone));
}
TEST_F(IrqForceTest, BadIrq) {
- EXPECT_EQ(dif_keymgr_irq_force(nullptr, static_cast<dif_keymgr_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_keymgr_irq_force(nullptr, static_cast<dif_keymgr_irq_t>(32)));
}
TEST_F(IrqForceTest, Success) {
// Force first IRQ.
EXPECT_WRITE32(KEYMGR_INTR_TEST_REG_OFFSET,
{{KEYMGR_INTR_TEST_OP_DONE_BIT, true}});
- EXPECT_EQ(dif_keymgr_irq_force(&keymgr_, kDifKeymgrIrqOpDone), kDifOk);
+ EXPECT_DIF_OK(dif_keymgr_irq_force(&keymgr_, kDifKeymgrIrqOpDone));
}
class IrqGetEnabledTest : public KeymgrTest {};
@@ -184,23 +178,21 @@
TEST_F(IrqGetEnabledTest, NullArgs) {
dif_toggle_t irq_state;
- EXPECT_EQ(
- dif_keymgr_irq_get_enabled(nullptr, kDifKeymgrIrqOpDone, &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_keymgr_irq_get_enabled(nullptr, kDifKeymgrIrqOpDone, &irq_state));
- EXPECT_EQ(dif_keymgr_irq_get_enabled(&keymgr_, kDifKeymgrIrqOpDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_keymgr_irq_get_enabled(&keymgr_, kDifKeymgrIrqOpDone, nullptr));
- EXPECT_EQ(dif_keymgr_irq_get_enabled(nullptr, kDifKeymgrIrqOpDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_keymgr_irq_get_enabled(nullptr, kDifKeymgrIrqOpDone, nullptr));
}
TEST_F(IrqGetEnabledTest, BadIrq) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_keymgr_irq_get_enabled(
- &keymgr_, static_cast<dif_keymgr_irq_t>(32), &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_keymgr_irq_get_enabled(
+ &keymgr_, static_cast<dif_keymgr_irq_t>(32), &irq_state));
}
TEST_F(IrqGetEnabledTest, Success) {
@@ -210,9 +202,8 @@
irq_state = kDifToggleDisabled;
EXPECT_READ32(KEYMGR_INTR_ENABLE_REG_OFFSET,
{{KEYMGR_INTR_ENABLE_OP_DONE_BIT, true}});
- EXPECT_EQ(
- dif_keymgr_irq_get_enabled(&keymgr_, kDifKeymgrIrqOpDone, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_keymgr_irq_get_enabled(&keymgr_, kDifKeymgrIrqOpDone, &irq_state));
EXPECT_EQ(irq_state, kDifToggleEnabled);
}
@@ -221,16 +212,15 @@
TEST_F(IrqSetEnabledTest, NullArgs) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_keymgr_irq_set_enabled(nullptr, kDifKeymgrIrqOpDone, irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_keymgr_irq_set_enabled(nullptr, kDifKeymgrIrqOpDone, irq_state));
}
TEST_F(IrqSetEnabledTest, BadIrq) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_keymgr_irq_set_enabled(
- &keymgr_, static_cast<dif_keymgr_irq_t>(32), irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_keymgr_irq_set_enabled(
+ &keymgr_, static_cast<dif_keymgr_irq_t>(32), irq_state));
}
TEST_F(IrqSetEnabledTest, Success) {
@@ -240,9 +230,8 @@
irq_state = kDifToggleEnabled;
EXPECT_MASK32(KEYMGR_INTR_ENABLE_REG_OFFSET,
{{KEYMGR_INTR_ENABLE_OP_DONE_BIT, 0x1, true}});
- EXPECT_EQ(
- dif_keymgr_irq_set_enabled(&keymgr_, kDifKeymgrIrqOpDone, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_keymgr_irq_set_enabled(&keymgr_, kDifKeymgrIrqOpDone, irq_state));
}
class IrqDisableAllTest : public KeymgrTest {};
@@ -250,14 +239,14 @@
TEST_F(IrqDisableAllTest, NullArgs) {
dif_keymgr_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_keymgr_irq_disable_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_keymgr_irq_disable_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_keymgr_irq_disable_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_keymgr_irq_disable_all(nullptr, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessNoSnapshot) {
EXPECT_WRITE32(KEYMGR_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_keymgr_irq_disable_all(&keymgr_, nullptr), kDifOk);
+ EXPECT_DIF_OK(dif_keymgr_irq_disable_all(&keymgr_, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessSnapshotAllDisabled) {
@@ -265,7 +254,7 @@
EXPECT_READ32(KEYMGR_INTR_ENABLE_REG_OFFSET, 0);
EXPECT_WRITE32(KEYMGR_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_keymgr_irq_disable_all(&keymgr_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_keymgr_irq_disable_all(&keymgr_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -275,7 +264,7 @@
EXPECT_READ32(KEYMGR_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
EXPECT_WRITE32(KEYMGR_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_keymgr_irq_disable_all(&keymgr_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_keymgr_irq_disable_all(&keymgr_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -284,11 +273,11 @@
TEST_F(IrqRestoreAllTest, NullArgs) {
dif_keymgr_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_keymgr_irq_restore_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_keymgr_irq_restore_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_keymgr_irq_restore_all(&keymgr_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_keymgr_irq_restore_all(&keymgr_, nullptr));
- EXPECT_EQ(dif_keymgr_irq_restore_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_keymgr_irq_restore_all(nullptr, nullptr));
}
TEST_F(IrqRestoreAllTest, SuccessAllEnabled) {
@@ -297,14 +286,14 @@
EXPECT_WRITE32(KEYMGR_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_keymgr_irq_restore_all(&keymgr_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_keymgr_irq_restore_all(&keymgr_, &irq_snapshot));
}
TEST_F(IrqRestoreAllTest, SuccessAllDisabled) {
dif_keymgr_irq_enable_snapshot_t irq_snapshot = 0;
EXPECT_WRITE32(KEYMGR_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_keymgr_irq_restore_all(&keymgr_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_keymgr_irq_restore_all(&keymgr_, &irq_snapshot));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_kmac_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_kmac_autogen_unittest.cc
index e5c705c..a5de987 100644
--- a/sw/device/lib/dif/autogen/dif_kmac_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_kmac_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "kmac_regs.h" // Generated.
@@ -28,36 +29,35 @@
class InitTest : public KmacTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_kmac_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_kmac_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_kmac_init(dev().region(), &kmac_), kDifOk);
+ EXPECT_DIF_OK(dif_kmac_init(dev().region(), &kmac_));
}
class AlertForceTest : public KmacTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_kmac_alert_force(nullptr, kDifKmacAlertRecovOperationErr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_kmac_alert_force(nullptr, kDifKmacAlertRecovOperationErr));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(dif_kmac_alert_force(nullptr, static_cast<dif_kmac_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_kmac_alert_force(nullptr, static_cast<dif_kmac_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(KMAC_ALERT_TEST_REG_OFFSET,
{{KMAC_ALERT_TEST_RECOV_OPERATION_ERR_BIT, true}});
- EXPECT_EQ(dif_kmac_alert_force(&kmac_, kDifKmacAlertRecovOperationErr),
- kDifOk);
+ EXPECT_DIF_OK(dif_kmac_alert_force(&kmac_, kDifKmacAlertRecovOperationErr));
// Force last alert.
EXPECT_WRITE32(KMAC_ALERT_TEST_REG_OFFSET,
{{KMAC_ALERT_TEST_FATAL_FAULT_ERR_BIT, true}});
- EXPECT_EQ(dif_kmac_alert_force(&kmac_, kDifKmacAlertFatalFaultErr), kDifOk);
+ EXPECT_DIF_OK(dif_kmac_alert_force(&kmac_, kDifKmacAlertFatalFaultErr));
}
class IrqGetStateTest : public KmacTest {};
@@ -65,11 +65,11 @@
TEST_F(IrqGetStateTest, NullArgs) {
dif_kmac_irq_state_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_kmac_irq_get_state(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_kmac_irq_get_state(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_kmac_irq_get_state(&kmac_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_kmac_irq_get_state(&kmac_, nullptr));
- EXPECT_EQ(dif_kmac_irq_get_state(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_kmac_irq_get_state(nullptr, nullptr));
}
TEST_F(IrqGetStateTest, SuccessAllRaised) {
@@ -77,7 +77,7 @@
EXPECT_READ32(KMAC_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_kmac_irq_get_state(&kmac_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_kmac_irq_get_state(&kmac_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -85,7 +85,7 @@
dif_kmac_irq_state_snapshot_t irq_snapshot = 0;
EXPECT_READ32(KMAC_INTR_STATE_REG_OFFSET, 0);
- EXPECT_EQ(dif_kmac_irq_get_state(&kmac_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_kmac_irq_get_state(&kmac_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -94,22 +94,21 @@
TEST_F(IrqIsPendingTest, NullArgs) {
bool is_pending;
- EXPECT_EQ(dif_kmac_irq_is_pending(nullptr, kDifKmacIrqKmacDone, &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_kmac_irq_is_pending(nullptr, kDifKmacIrqKmacDone, &is_pending));
- EXPECT_EQ(dif_kmac_irq_is_pending(&kmac_, kDifKmacIrqKmacDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_kmac_irq_is_pending(&kmac_, kDifKmacIrqKmacDone, nullptr));
- EXPECT_EQ(dif_kmac_irq_is_pending(nullptr, kDifKmacIrqKmacDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_kmac_irq_is_pending(nullptr, kDifKmacIrqKmacDone, nullptr));
}
TEST_F(IrqIsPendingTest, BadIrq) {
bool is_pending;
// All interrupt CSRs are 32 bit so interrupt 32 will be invalid.
- EXPECT_EQ(dif_kmac_irq_is_pending(&kmac_, static_cast<dif_kmac_irq_t>(32),
- &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_kmac_irq_is_pending(
+ &kmac_, static_cast<dif_kmac_irq_t>(32), &is_pending));
}
TEST_F(IrqIsPendingTest, Success) {
@@ -119,76 +118,76 @@
irq_state = false;
EXPECT_READ32(KMAC_INTR_STATE_REG_OFFSET,
{{KMAC_INTR_STATE_KMAC_DONE_BIT, true}});
- EXPECT_EQ(dif_kmac_irq_is_pending(&kmac_, kDifKmacIrqKmacDone, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_kmac_irq_is_pending(&kmac_, kDifKmacIrqKmacDone, &irq_state));
EXPECT_TRUE(irq_state);
// Get the last IRQ state.
irq_state = true;
EXPECT_READ32(KMAC_INTR_STATE_REG_OFFSET,
{{KMAC_INTR_STATE_KMAC_ERR_BIT, false}});
- EXPECT_EQ(dif_kmac_irq_is_pending(&kmac_, kDifKmacIrqKmacErr, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_kmac_irq_is_pending(&kmac_, kDifKmacIrqKmacErr, &irq_state));
EXPECT_FALSE(irq_state);
}
class AcknowledgeAllTest : public KmacTest {};
TEST_F(AcknowledgeAllTest, NullArgs) {
- EXPECT_EQ(dif_kmac_irq_acknowledge_all(nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_kmac_irq_acknowledge_all(nullptr));
}
TEST_F(AcknowledgeAllTest, Success) {
EXPECT_WRITE32(KMAC_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_kmac_irq_acknowledge_all(&kmac_), kDifOk);
+ EXPECT_DIF_OK(dif_kmac_irq_acknowledge_all(&kmac_));
}
class IrqAcknowledgeTest : public KmacTest {};
TEST_F(IrqAcknowledgeTest, NullArgs) {
- EXPECT_EQ(dif_kmac_irq_acknowledge(nullptr, kDifKmacIrqKmacDone), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_kmac_irq_acknowledge(nullptr, kDifKmacIrqKmacDone));
}
TEST_F(IrqAcknowledgeTest, BadIrq) {
- EXPECT_EQ(dif_kmac_irq_acknowledge(nullptr, static_cast<dif_kmac_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_kmac_irq_acknowledge(nullptr, static_cast<dif_kmac_irq_t>(32)));
}
TEST_F(IrqAcknowledgeTest, Success) {
// Clear the first IRQ state.
EXPECT_WRITE32(KMAC_INTR_STATE_REG_OFFSET,
{{KMAC_INTR_STATE_KMAC_DONE_BIT, true}});
- EXPECT_EQ(dif_kmac_irq_acknowledge(&kmac_, kDifKmacIrqKmacDone), kDifOk);
+ EXPECT_DIF_OK(dif_kmac_irq_acknowledge(&kmac_, kDifKmacIrqKmacDone));
// Clear the last IRQ state.
EXPECT_WRITE32(KMAC_INTR_STATE_REG_OFFSET,
{{KMAC_INTR_STATE_KMAC_ERR_BIT, true}});
- EXPECT_EQ(dif_kmac_irq_acknowledge(&kmac_, kDifKmacIrqKmacErr), kDifOk);
+ EXPECT_DIF_OK(dif_kmac_irq_acknowledge(&kmac_, kDifKmacIrqKmacErr));
}
class IrqForceTest : public KmacTest {};
TEST_F(IrqForceTest, NullArgs) {
- EXPECT_EQ(dif_kmac_irq_force(nullptr, kDifKmacIrqKmacDone), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_kmac_irq_force(nullptr, kDifKmacIrqKmacDone));
}
TEST_F(IrqForceTest, BadIrq) {
- EXPECT_EQ(dif_kmac_irq_force(nullptr, static_cast<dif_kmac_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_kmac_irq_force(nullptr, static_cast<dif_kmac_irq_t>(32)));
}
TEST_F(IrqForceTest, Success) {
// Force first IRQ.
EXPECT_WRITE32(KMAC_INTR_TEST_REG_OFFSET,
{{KMAC_INTR_TEST_KMAC_DONE_BIT, true}});
- EXPECT_EQ(dif_kmac_irq_force(&kmac_, kDifKmacIrqKmacDone), kDifOk);
+ EXPECT_DIF_OK(dif_kmac_irq_force(&kmac_, kDifKmacIrqKmacDone));
// Force last IRQ.
EXPECT_WRITE32(KMAC_INTR_TEST_REG_OFFSET,
{{KMAC_INTR_TEST_KMAC_ERR_BIT, true}});
- EXPECT_EQ(dif_kmac_irq_force(&kmac_, kDifKmacIrqKmacErr), kDifOk);
+ EXPECT_DIF_OK(dif_kmac_irq_force(&kmac_, kDifKmacIrqKmacErr));
}
class IrqGetEnabledTest : public KmacTest {};
@@ -196,22 +195,21 @@
TEST_F(IrqGetEnabledTest, NullArgs) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_kmac_irq_get_enabled(nullptr, kDifKmacIrqKmacDone, &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_kmac_irq_get_enabled(nullptr, kDifKmacIrqKmacDone, &irq_state));
- EXPECT_EQ(dif_kmac_irq_get_enabled(&kmac_, kDifKmacIrqKmacDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_kmac_irq_get_enabled(&kmac_, kDifKmacIrqKmacDone, nullptr));
- EXPECT_EQ(dif_kmac_irq_get_enabled(nullptr, kDifKmacIrqKmacDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_kmac_irq_get_enabled(nullptr, kDifKmacIrqKmacDone, nullptr));
}
TEST_F(IrqGetEnabledTest, BadIrq) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_kmac_irq_get_enabled(&kmac_, static_cast<dif_kmac_irq_t>(32),
- &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_kmac_irq_get_enabled(
+ &kmac_, static_cast<dif_kmac_irq_t>(32), &irq_state));
}
TEST_F(IrqGetEnabledTest, Success) {
@@ -221,16 +219,16 @@
irq_state = kDifToggleDisabled;
EXPECT_READ32(KMAC_INTR_ENABLE_REG_OFFSET,
{{KMAC_INTR_ENABLE_KMAC_DONE_BIT, true}});
- EXPECT_EQ(dif_kmac_irq_get_enabled(&kmac_, kDifKmacIrqKmacDone, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_kmac_irq_get_enabled(&kmac_, kDifKmacIrqKmacDone, &irq_state));
EXPECT_EQ(irq_state, kDifToggleEnabled);
// Last IRQ is disabled.
irq_state = kDifToggleEnabled;
EXPECT_READ32(KMAC_INTR_ENABLE_REG_OFFSET,
{{KMAC_INTR_ENABLE_KMAC_ERR_BIT, false}});
- EXPECT_EQ(dif_kmac_irq_get_enabled(&kmac_, kDifKmacIrqKmacErr, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_kmac_irq_get_enabled(&kmac_, kDifKmacIrqKmacErr, &irq_state));
EXPECT_EQ(irq_state, kDifToggleDisabled);
}
@@ -239,16 +237,15 @@
TEST_F(IrqSetEnabledTest, NullArgs) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_kmac_irq_set_enabled(nullptr, kDifKmacIrqKmacDone, irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_kmac_irq_set_enabled(nullptr, kDifKmacIrqKmacDone, irq_state));
}
TEST_F(IrqSetEnabledTest, BadIrq) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_kmac_irq_set_enabled(&kmac_, static_cast<dif_kmac_irq_t>(32),
- irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_kmac_irq_set_enabled(
+ &kmac_, static_cast<dif_kmac_irq_t>(32), irq_state));
}
TEST_F(IrqSetEnabledTest, Success) {
@@ -258,15 +255,15 @@
irq_state = kDifToggleEnabled;
EXPECT_MASK32(KMAC_INTR_ENABLE_REG_OFFSET,
{{KMAC_INTR_ENABLE_KMAC_DONE_BIT, 0x1, true}});
- EXPECT_EQ(dif_kmac_irq_set_enabled(&kmac_, kDifKmacIrqKmacDone, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_kmac_irq_set_enabled(&kmac_, kDifKmacIrqKmacDone, irq_state));
// Disable last IRQ.
irq_state = kDifToggleDisabled;
EXPECT_MASK32(KMAC_INTR_ENABLE_REG_OFFSET,
{{KMAC_INTR_ENABLE_KMAC_ERR_BIT, 0x1, false}});
- EXPECT_EQ(dif_kmac_irq_set_enabled(&kmac_, kDifKmacIrqKmacErr, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_kmac_irq_set_enabled(&kmac_, kDifKmacIrqKmacErr, irq_state));
}
class IrqDisableAllTest : public KmacTest {};
@@ -274,14 +271,14 @@
TEST_F(IrqDisableAllTest, NullArgs) {
dif_kmac_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_kmac_irq_disable_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_kmac_irq_disable_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_kmac_irq_disable_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_kmac_irq_disable_all(nullptr, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessNoSnapshot) {
EXPECT_WRITE32(KMAC_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_kmac_irq_disable_all(&kmac_, nullptr), kDifOk);
+ EXPECT_DIF_OK(dif_kmac_irq_disable_all(&kmac_, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessSnapshotAllDisabled) {
@@ -289,7 +286,7 @@
EXPECT_READ32(KMAC_INTR_ENABLE_REG_OFFSET, 0);
EXPECT_WRITE32(KMAC_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_kmac_irq_disable_all(&kmac_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_kmac_irq_disable_all(&kmac_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -299,7 +296,7 @@
EXPECT_READ32(KMAC_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
EXPECT_WRITE32(KMAC_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_kmac_irq_disable_all(&kmac_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_kmac_irq_disable_all(&kmac_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -308,11 +305,11 @@
TEST_F(IrqRestoreAllTest, NullArgs) {
dif_kmac_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_kmac_irq_restore_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_kmac_irq_restore_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_kmac_irq_restore_all(&kmac_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_kmac_irq_restore_all(&kmac_, nullptr));
- EXPECT_EQ(dif_kmac_irq_restore_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_kmac_irq_restore_all(nullptr, nullptr));
}
TEST_F(IrqRestoreAllTest, SuccessAllEnabled) {
@@ -321,14 +318,14 @@
EXPECT_WRITE32(KMAC_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_kmac_irq_restore_all(&kmac_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_kmac_irq_restore_all(&kmac_, &irq_snapshot));
}
TEST_F(IrqRestoreAllTest, SuccessAllDisabled) {
dif_kmac_irq_enable_snapshot_t irq_snapshot = 0;
EXPECT_WRITE32(KMAC_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_kmac_irq_restore_all(&kmac_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_kmac_irq_restore_all(&kmac_, &irq_snapshot));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_lc_ctrl_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_lc_ctrl_autogen_unittest.cc
index 5511a50..0d9e2ea 100644
--- a/sw/device/lib/dif/autogen/dif_lc_ctrl_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_lc_ctrl_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "lc_ctrl_regs.h" // Generated.
@@ -28,39 +29,37 @@
class InitTest : public LcCtrlTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_lc_ctrl_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_lc_ctrl_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_lc_ctrl_init(dev().region(), &lc_ctrl_), kDifOk);
+ EXPECT_DIF_OK(dif_lc_ctrl_init(dev().region(), &lc_ctrl_));
}
class AlertForceTest : public LcCtrlTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_lc_ctrl_alert_force(nullptr, kDifLcCtrlAlertFatalProgError),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_lc_ctrl_alert_force(nullptr, kDifLcCtrlAlertFatalProgError));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(
- dif_lc_ctrl_alert_force(nullptr, static_cast<dif_lc_ctrl_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_lc_ctrl_alert_force(nullptr, static_cast<dif_lc_ctrl_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(LC_CTRL_ALERT_TEST_REG_OFFSET,
{{LC_CTRL_ALERT_TEST_FATAL_PROG_ERROR_BIT, true}});
- EXPECT_EQ(dif_lc_ctrl_alert_force(&lc_ctrl_, kDifLcCtrlAlertFatalProgError),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_lc_ctrl_alert_force(&lc_ctrl_, kDifLcCtrlAlertFatalProgError));
// Force last alert.
EXPECT_WRITE32(LC_CTRL_ALERT_TEST_REG_OFFSET,
{{LC_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_BIT, true}});
- EXPECT_EQ(
- dif_lc_ctrl_alert_force(&lc_ctrl_, kDifLcCtrlAlertFatalBusIntegError),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_lc_ctrl_alert_force(&lc_ctrl_, kDifLcCtrlAlertFatalBusIntegError));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_otbn_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_otbn_autogen_unittest.cc
index dd0dbf0..f7e306e 100644
--- a/sw/device/lib/dif/autogen/dif_otbn_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_otbn_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "otbn_regs.h" // Generated.
@@ -28,34 +29,34 @@
class InitTest : public OtbnTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_otbn_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otbn_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_otbn_init(dev().region(), &otbn_), kDifOk);
+ EXPECT_DIF_OK(dif_otbn_init(dev().region(), &otbn_));
}
class AlertForceTest : public OtbnTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_otbn_alert_force(nullptr, kDifOtbnAlertFatal), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otbn_alert_force(nullptr, kDifOtbnAlertFatal));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(dif_otbn_alert_force(nullptr, static_cast<dif_otbn_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_otbn_alert_force(nullptr, static_cast<dif_otbn_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(OTBN_ALERT_TEST_REG_OFFSET,
{{OTBN_ALERT_TEST_FATAL_BIT, true}});
- EXPECT_EQ(dif_otbn_alert_force(&otbn_, kDifOtbnAlertFatal), kDifOk);
+ EXPECT_DIF_OK(dif_otbn_alert_force(&otbn_, kDifOtbnAlertFatal));
// Force last alert.
EXPECT_WRITE32(OTBN_ALERT_TEST_REG_OFFSET,
{{OTBN_ALERT_TEST_RECOV_BIT, true}});
- EXPECT_EQ(dif_otbn_alert_force(&otbn_, kDifOtbnAlertRecov), kDifOk);
+ EXPECT_DIF_OK(dif_otbn_alert_force(&otbn_, kDifOtbnAlertRecov));
}
class IrqGetStateTest : public OtbnTest {};
@@ -63,11 +64,11 @@
TEST_F(IrqGetStateTest, NullArgs) {
dif_otbn_irq_state_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_otbn_irq_get_state(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otbn_irq_get_state(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_otbn_irq_get_state(&otbn_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otbn_irq_get_state(&otbn_, nullptr));
- EXPECT_EQ(dif_otbn_irq_get_state(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otbn_irq_get_state(nullptr, nullptr));
}
TEST_F(IrqGetStateTest, SuccessAllRaised) {
@@ -75,7 +76,7 @@
EXPECT_READ32(OTBN_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_otbn_irq_get_state(&otbn_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_otbn_irq_get_state(&otbn_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -83,7 +84,7 @@
dif_otbn_irq_state_snapshot_t irq_snapshot = 0;
EXPECT_READ32(OTBN_INTR_STATE_REG_OFFSET, 0);
- EXPECT_EQ(dif_otbn_irq_get_state(&otbn_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_otbn_irq_get_state(&otbn_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -92,22 +93,19 @@
TEST_F(IrqIsPendingTest, NullArgs) {
bool is_pending;
- EXPECT_EQ(dif_otbn_irq_is_pending(nullptr, kDifOtbnIrqDone, &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_otbn_irq_is_pending(nullptr, kDifOtbnIrqDone, &is_pending));
- EXPECT_EQ(dif_otbn_irq_is_pending(&otbn_, kDifOtbnIrqDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otbn_irq_is_pending(&otbn_, kDifOtbnIrqDone, nullptr));
- EXPECT_EQ(dif_otbn_irq_is_pending(nullptr, kDifOtbnIrqDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otbn_irq_is_pending(nullptr, kDifOtbnIrqDone, nullptr));
}
TEST_F(IrqIsPendingTest, BadIrq) {
bool is_pending;
// All interrupt CSRs are 32 bit so interrupt 32 will be invalid.
- EXPECT_EQ(dif_otbn_irq_is_pending(&otbn_, static_cast<dif_otbn_irq_t>(32),
- &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otbn_irq_is_pending(
+ &otbn_, static_cast<dif_otbn_irq_t>(32), &is_pending));
}
TEST_F(IrqIsPendingTest, Success) {
@@ -116,57 +114,56 @@
// Get the first IRQ state.
irq_state = false;
EXPECT_READ32(OTBN_INTR_STATE_REG_OFFSET, {{OTBN_INTR_STATE_DONE_BIT, true}});
- EXPECT_EQ(dif_otbn_irq_is_pending(&otbn_, kDifOtbnIrqDone, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_otbn_irq_is_pending(&otbn_, kDifOtbnIrqDone, &irq_state));
EXPECT_TRUE(irq_state);
}
class AcknowledgeAllTest : public OtbnTest {};
TEST_F(AcknowledgeAllTest, NullArgs) {
- EXPECT_EQ(dif_otbn_irq_acknowledge_all(nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otbn_irq_acknowledge_all(nullptr));
}
TEST_F(AcknowledgeAllTest, Success) {
EXPECT_WRITE32(OTBN_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_otbn_irq_acknowledge_all(&otbn_), kDifOk);
+ EXPECT_DIF_OK(dif_otbn_irq_acknowledge_all(&otbn_));
}
class IrqAcknowledgeTest : public OtbnTest {};
TEST_F(IrqAcknowledgeTest, NullArgs) {
- EXPECT_EQ(dif_otbn_irq_acknowledge(nullptr, kDifOtbnIrqDone), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otbn_irq_acknowledge(nullptr, kDifOtbnIrqDone));
}
TEST_F(IrqAcknowledgeTest, BadIrq) {
- EXPECT_EQ(dif_otbn_irq_acknowledge(nullptr, static_cast<dif_otbn_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_otbn_irq_acknowledge(nullptr, static_cast<dif_otbn_irq_t>(32)));
}
TEST_F(IrqAcknowledgeTest, Success) {
// Clear the first IRQ state.
EXPECT_WRITE32(OTBN_INTR_STATE_REG_OFFSET,
{{OTBN_INTR_STATE_DONE_BIT, true}});
- EXPECT_EQ(dif_otbn_irq_acknowledge(&otbn_, kDifOtbnIrqDone), kDifOk);
+ EXPECT_DIF_OK(dif_otbn_irq_acknowledge(&otbn_, kDifOtbnIrqDone));
}
class IrqForceTest : public OtbnTest {};
TEST_F(IrqForceTest, NullArgs) {
- EXPECT_EQ(dif_otbn_irq_force(nullptr, kDifOtbnIrqDone), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otbn_irq_force(nullptr, kDifOtbnIrqDone));
}
TEST_F(IrqForceTest, BadIrq) {
- EXPECT_EQ(dif_otbn_irq_force(nullptr, static_cast<dif_otbn_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_otbn_irq_force(nullptr, static_cast<dif_otbn_irq_t>(32)));
}
TEST_F(IrqForceTest, Success) {
// Force first IRQ.
EXPECT_WRITE32(OTBN_INTR_TEST_REG_OFFSET, {{OTBN_INTR_TEST_DONE_BIT, true}});
- EXPECT_EQ(dif_otbn_irq_force(&otbn_, kDifOtbnIrqDone), kDifOk);
+ EXPECT_DIF_OK(dif_otbn_irq_force(&otbn_, kDifOtbnIrqDone));
}
class IrqGetEnabledTest : public OtbnTest {};
@@ -174,22 +171,20 @@
TEST_F(IrqGetEnabledTest, NullArgs) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_otbn_irq_get_enabled(nullptr, kDifOtbnIrqDone, &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_otbn_irq_get_enabled(nullptr, kDifOtbnIrqDone, &irq_state));
- EXPECT_EQ(dif_otbn_irq_get_enabled(&otbn_, kDifOtbnIrqDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otbn_irq_get_enabled(&otbn_, kDifOtbnIrqDone, nullptr));
- EXPECT_EQ(dif_otbn_irq_get_enabled(nullptr, kDifOtbnIrqDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_otbn_irq_get_enabled(nullptr, kDifOtbnIrqDone, nullptr));
}
TEST_F(IrqGetEnabledTest, BadIrq) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_otbn_irq_get_enabled(&otbn_, static_cast<dif_otbn_irq_t>(32),
- &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otbn_irq_get_enabled(
+ &otbn_, static_cast<dif_otbn_irq_t>(32), &irq_state));
}
TEST_F(IrqGetEnabledTest, Success) {
@@ -199,8 +194,7 @@
irq_state = kDifToggleDisabled;
EXPECT_READ32(OTBN_INTR_ENABLE_REG_OFFSET,
{{OTBN_INTR_ENABLE_DONE_BIT, true}});
- EXPECT_EQ(dif_otbn_irq_get_enabled(&otbn_, kDifOtbnIrqDone, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_otbn_irq_get_enabled(&otbn_, kDifOtbnIrqDone, &irq_state));
EXPECT_EQ(irq_state, kDifToggleEnabled);
}
@@ -209,16 +203,15 @@
TEST_F(IrqSetEnabledTest, NullArgs) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_otbn_irq_set_enabled(nullptr, kDifOtbnIrqDone, irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_otbn_irq_set_enabled(nullptr, kDifOtbnIrqDone, irq_state));
}
TEST_F(IrqSetEnabledTest, BadIrq) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_otbn_irq_set_enabled(&otbn_, static_cast<dif_otbn_irq_t>(32),
- irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otbn_irq_set_enabled(
+ &otbn_, static_cast<dif_otbn_irq_t>(32), irq_state));
}
TEST_F(IrqSetEnabledTest, Success) {
@@ -228,8 +221,7 @@
irq_state = kDifToggleEnabled;
EXPECT_MASK32(OTBN_INTR_ENABLE_REG_OFFSET,
{{OTBN_INTR_ENABLE_DONE_BIT, 0x1, true}});
- EXPECT_EQ(dif_otbn_irq_set_enabled(&otbn_, kDifOtbnIrqDone, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_otbn_irq_set_enabled(&otbn_, kDifOtbnIrqDone, irq_state));
}
class IrqDisableAllTest : public OtbnTest {};
@@ -237,14 +229,14 @@
TEST_F(IrqDisableAllTest, NullArgs) {
dif_otbn_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_otbn_irq_disable_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otbn_irq_disable_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_otbn_irq_disable_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otbn_irq_disable_all(nullptr, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessNoSnapshot) {
EXPECT_WRITE32(OTBN_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_otbn_irq_disable_all(&otbn_, nullptr), kDifOk);
+ EXPECT_DIF_OK(dif_otbn_irq_disable_all(&otbn_, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessSnapshotAllDisabled) {
@@ -252,7 +244,7 @@
EXPECT_READ32(OTBN_INTR_ENABLE_REG_OFFSET, 0);
EXPECT_WRITE32(OTBN_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_otbn_irq_disable_all(&otbn_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_otbn_irq_disable_all(&otbn_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -262,7 +254,7 @@
EXPECT_READ32(OTBN_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
EXPECT_WRITE32(OTBN_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_otbn_irq_disable_all(&otbn_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_otbn_irq_disable_all(&otbn_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -271,11 +263,11 @@
TEST_F(IrqRestoreAllTest, NullArgs) {
dif_otbn_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_otbn_irq_restore_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otbn_irq_restore_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_otbn_irq_restore_all(&otbn_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otbn_irq_restore_all(&otbn_, nullptr));
- EXPECT_EQ(dif_otbn_irq_restore_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otbn_irq_restore_all(nullptr, nullptr));
}
TEST_F(IrqRestoreAllTest, SuccessAllEnabled) {
@@ -284,14 +276,14 @@
EXPECT_WRITE32(OTBN_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_otbn_irq_restore_all(&otbn_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_otbn_irq_restore_all(&otbn_, &irq_snapshot));
}
TEST_F(IrqRestoreAllTest, SuccessAllDisabled) {
dif_otbn_irq_enable_snapshot_t irq_snapshot = 0;
EXPECT_WRITE32(OTBN_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_otbn_irq_restore_all(&otbn_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_otbn_irq_restore_all(&otbn_, &irq_snapshot));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_otp_ctrl_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_otp_ctrl_autogen_unittest.cc
index 313bf8e..62fbb3a 100644
--- a/sw/device/lib/dif/autogen/dif_otp_ctrl_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_otp_ctrl_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "otp_ctrl_regs.h" // Generated.
@@ -28,40 +29,37 @@
class InitTest : public OtpCtrlTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_otp_ctrl_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otp_ctrl_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_otp_ctrl_init(dev().region(), &otp_ctrl_), kDifOk);
+ EXPECT_DIF_OK(dif_otp_ctrl_init(dev().region(), &otp_ctrl_));
}
class AlertForceTest : public OtpCtrlTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_otp_ctrl_alert_force(nullptr, kDifOtpCtrlAlertFatalMacroError),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_otp_ctrl_alert_force(nullptr, kDifOtpCtrlAlertFatalMacroError));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(
- dif_otp_ctrl_alert_force(nullptr, static_cast<dif_otp_ctrl_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_otp_ctrl_alert_force(nullptr, static_cast<dif_otp_ctrl_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(OTP_CTRL_ALERT_TEST_REG_OFFSET,
{{OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_BIT, true}});
- EXPECT_EQ(
- dif_otp_ctrl_alert_force(&otp_ctrl_, kDifOtpCtrlAlertFatalMacroError),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_otp_ctrl_alert_force(&otp_ctrl_, kDifOtpCtrlAlertFatalMacroError));
// Force last alert.
EXPECT_WRITE32(OTP_CTRL_ALERT_TEST_REG_OFFSET,
{{OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_BIT, true}});
- EXPECT_EQ(
- dif_otp_ctrl_alert_force(&otp_ctrl_, kDifOtpCtrlAlertFatalBusIntegError),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_otp_ctrl_alert_force(&otp_ctrl_, kDifOtpCtrlAlertFatalBusIntegError));
}
class IrqGetStateTest : public OtpCtrlTest {};
@@ -69,11 +67,11 @@
TEST_F(IrqGetStateTest, NullArgs) {
dif_otp_ctrl_irq_state_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_otp_ctrl_irq_get_state(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otp_ctrl_irq_get_state(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_otp_ctrl_irq_get_state(&otp_ctrl_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otp_ctrl_irq_get_state(&otp_ctrl_, nullptr));
- EXPECT_EQ(dif_otp_ctrl_irq_get_state(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otp_ctrl_irq_get_state(nullptr, nullptr));
}
TEST_F(IrqGetStateTest, SuccessAllRaised) {
@@ -81,7 +79,7 @@
EXPECT_READ32(OTP_CTRL_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_otp_ctrl_irq_get_state(&otp_ctrl_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_otp_ctrl_irq_get_state(&otp_ctrl_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -89,7 +87,7 @@
dif_otp_ctrl_irq_state_snapshot_t irq_snapshot = 0;
EXPECT_READ32(OTP_CTRL_INTR_STATE_REG_OFFSET, 0);
- EXPECT_EQ(dif_otp_ctrl_irq_get_state(&otp_ctrl_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_otp_ctrl_irq_get_state(&otp_ctrl_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -98,25 +96,21 @@
TEST_F(IrqIsPendingTest, NullArgs) {
bool is_pending;
- EXPECT_EQ(dif_otp_ctrl_irq_is_pending(nullptr, kDifOtpCtrlIrqOtpOperationDone,
- &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otp_ctrl_irq_is_pending(
+ nullptr, kDifOtpCtrlIrqOtpOperationDone, &is_pending));
- EXPECT_EQ(dif_otp_ctrl_irq_is_pending(
- &otp_ctrl_, kDifOtpCtrlIrqOtpOperationDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otp_ctrl_irq_is_pending(
+ &otp_ctrl_, kDifOtpCtrlIrqOtpOperationDone, nullptr));
- EXPECT_EQ(dif_otp_ctrl_irq_is_pending(nullptr, kDifOtpCtrlIrqOtpOperationDone,
- nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otp_ctrl_irq_is_pending(
+ nullptr, kDifOtpCtrlIrqOtpOperationDone, nullptr));
}
TEST_F(IrqIsPendingTest, BadIrq) {
bool is_pending;
// All interrupt CSRs are 32 bit so interrupt 32 will be invalid.
- EXPECT_EQ(dif_otp_ctrl_irq_is_pending(
- &otp_ctrl_, static_cast<dif_otp_ctrl_irq_t>(32), &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otp_ctrl_irq_is_pending(
+ &otp_ctrl_, static_cast<dif_otp_ctrl_irq_t>(32), &is_pending));
}
TEST_F(IrqIsPendingTest, Success) {
@@ -126,87 +120,81 @@
irq_state = false;
EXPECT_READ32(OTP_CTRL_INTR_STATE_REG_OFFSET,
{{OTP_CTRL_INTR_STATE_OTP_OPERATION_DONE_BIT, true}});
- EXPECT_EQ(dif_otp_ctrl_irq_is_pending(
- &otp_ctrl_, kDifOtpCtrlIrqOtpOperationDone, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_otp_ctrl_irq_is_pending(
+ &otp_ctrl_, kDifOtpCtrlIrqOtpOperationDone, &irq_state));
EXPECT_TRUE(irq_state);
// Get the last IRQ state.
irq_state = true;
EXPECT_READ32(OTP_CTRL_INTR_STATE_REG_OFFSET,
{{OTP_CTRL_INTR_STATE_OTP_ERROR_BIT, false}});
- EXPECT_EQ(dif_otp_ctrl_irq_is_pending(&otp_ctrl_, kDifOtpCtrlIrqOtpError,
- &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_otp_ctrl_irq_is_pending(&otp_ctrl_, kDifOtpCtrlIrqOtpError,
+ &irq_state));
EXPECT_FALSE(irq_state);
}
class AcknowledgeAllTest : public OtpCtrlTest {};
TEST_F(AcknowledgeAllTest, NullArgs) {
- EXPECT_EQ(dif_otp_ctrl_irq_acknowledge_all(nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otp_ctrl_irq_acknowledge_all(nullptr));
}
TEST_F(AcknowledgeAllTest, Success) {
EXPECT_WRITE32(OTP_CTRL_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_otp_ctrl_irq_acknowledge_all(&otp_ctrl_), kDifOk);
+ EXPECT_DIF_OK(dif_otp_ctrl_irq_acknowledge_all(&otp_ctrl_));
}
class IrqAcknowledgeTest : public OtpCtrlTest {};
TEST_F(IrqAcknowledgeTest, NullArgs) {
- EXPECT_EQ(
- dif_otp_ctrl_irq_acknowledge(nullptr, kDifOtpCtrlIrqOtpOperationDone),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_otp_ctrl_irq_acknowledge(nullptr, kDifOtpCtrlIrqOtpOperationDone));
}
TEST_F(IrqAcknowledgeTest, BadIrq) {
- EXPECT_EQ(dif_otp_ctrl_irq_acknowledge(nullptr,
- static_cast<dif_otp_ctrl_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otp_ctrl_irq_acknowledge(
+ nullptr, static_cast<dif_otp_ctrl_irq_t>(32)));
}
TEST_F(IrqAcknowledgeTest, Success) {
// Clear the first IRQ state.
EXPECT_WRITE32(OTP_CTRL_INTR_STATE_REG_OFFSET,
{{OTP_CTRL_INTR_STATE_OTP_OPERATION_DONE_BIT, true}});
- EXPECT_EQ(
- dif_otp_ctrl_irq_acknowledge(&otp_ctrl_, kDifOtpCtrlIrqOtpOperationDone),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_otp_ctrl_irq_acknowledge(&otp_ctrl_, kDifOtpCtrlIrqOtpOperationDone));
// Clear the last IRQ state.
EXPECT_WRITE32(OTP_CTRL_INTR_STATE_REG_OFFSET,
{{OTP_CTRL_INTR_STATE_OTP_ERROR_BIT, true}});
- EXPECT_EQ(dif_otp_ctrl_irq_acknowledge(&otp_ctrl_, kDifOtpCtrlIrqOtpError),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_otp_ctrl_irq_acknowledge(&otp_ctrl_, kDifOtpCtrlIrqOtpError));
}
class IrqForceTest : public OtpCtrlTest {};
TEST_F(IrqForceTest, NullArgs) {
- EXPECT_EQ(dif_otp_ctrl_irq_force(nullptr, kDifOtpCtrlIrqOtpOperationDone),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_otp_ctrl_irq_force(nullptr, kDifOtpCtrlIrqOtpOperationDone));
}
TEST_F(IrqForceTest, BadIrq) {
- EXPECT_EQ(
- dif_otp_ctrl_irq_force(nullptr, static_cast<dif_otp_ctrl_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_otp_ctrl_irq_force(nullptr, static_cast<dif_otp_ctrl_irq_t>(32)));
}
TEST_F(IrqForceTest, Success) {
// Force first IRQ.
EXPECT_WRITE32(OTP_CTRL_INTR_TEST_REG_OFFSET,
{{OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_BIT, true}});
- EXPECT_EQ(dif_otp_ctrl_irq_force(&otp_ctrl_, kDifOtpCtrlIrqOtpOperationDone),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_otp_ctrl_irq_force(&otp_ctrl_, kDifOtpCtrlIrqOtpOperationDone));
// Force last IRQ.
EXPECT_WRITE32(OTP_CTRL_INTR_TEST_REG_OFFSET,
{{OTP_CTRL_INTR_TEST_OTP_ERROR_BIT, true}});
- EXPECT_EQ(dif_otp_ctrl_irq_force(&otp_ctrl_, kDifOtpCtrlIrqOtpError), kDifOk);
+ EXPECT_DIF_OK(dif_otp_ctrl_irq_force(&otp_ctrl_, kDifOtpCtrlIrqOtpError));
}
class IrqGetEnabledTest : public OtpCtrlTest {};
@@ -214,25 +202,21 @@
TEST_F(IrqGetEnabledTest, NullArgs) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_otp_ctrl_irq_get_enabled(
- nullptr, kDifOtpCtrlIrqOtpOperationDone, &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otp_ctrl_irq_get_enabled(
+ nullptr, kDifOtpCtrlIrqOtpOperationDone, &irq_state));
- EXPECT_EQ(dif_otp_ctrl_irq_get_enabled(
- &otp_ctrl_, kDifOtpCtrlIrqOtpOperationDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otp_ctrl_irq_get_enabled(
+ &otp_ctrl_, kDifOtpCtrlIrqOtpOperationDone, nullptr));
- EXPECT_EQ(dif_otp_ctrl_irq_get_enabled(
- nullptr, kDifOtpCtrlIrqOtpOperationDone, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otp_ctrl_irq_get_enabled(
+ nullptr, kDifOtpCtrlIrqOtpOperationDone, nullptr));
}
TEST_F(IrqGetEnabledTest, BadIrq) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_otp_ctrl_irq_get_enabled(
- &otp_ctrl_, static_cast<dif_otp_ctrl_irq_t>(32), &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otp_ctrl_irq_get_enabled(
+ &otp_ctrl_, static_cast<dif_otp_ctrl_irq_t>(32), &irq_state));
}
TEST_F(IrqGetEnabledTest, Success) {
@@ -242,18 +226,16 @@
irq_state = kDifToggleDisabled;
EXPECT_READ32(OTP_CTRL_INTR_ENABLE_REG_OFFSET,
{{OTP_CTRL_INTR_ENABLE_OTP_OPERATION_DONE_BIT, true}});
- EXPECT_EQ(dif_otp_ctrl_irq_get_enabled(
- &otp_ctrl_, kDifOtpCtrlIrqOtpOperationDone, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_otp_ctrl_irq_get_enabled(
+ &otp_ctrl_, kDifOtpCtrlIrqOtpOperationDone, &irq_state));
EXPECT_EQ(irq_state, kDifToggleEnabled);
// Last IRQ is disabled.
irq_state = kDifToggleEnabled;
EXPECT_READ32(OTP_CTRL_INTR_ENABLE_REG_OFFSET,
{{OTP_CTRL_INTR_ENABLE_OTP_ERROR_BIT, false}});
- EXPECT_EQ(dif_otp_ctrl_irq_get_enabled(&otp_ctrl_, kDifOtpCtrlIrqOtpError,
- &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_otp_ctrl_irq_get_enabled(&otp_ctrl_, kDifOtpCtrlIrqOtpError,
+ &irq_state));
EXPECT_EQ(irq_state, kDifToggleDisabled);
}
@@ -262,17 +244,15 @@
TEST_F(IrqSetEnabledTest, NullArgs) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_otp_ctrl_irq_set_enabled(
- nullptr, kDifOtpCtrlIrqOtpOperationDone, irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otp_ctrl_irq_set_enabled(
+ nullptr, kDifOtpCtrlIrqOtpOperationDone, irq_state));
}
TEST_F(IrqSetEnabledTest, BadIrq) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_otp_ctrl_irq_set_enabled(
- &otp_ctrl_, static_cast<dif_otp_ctrl_irq_t>(32), irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otp_ctrl_irq_set_enabled(
+ &otp_ctrl_, static_cast<dif_otp_ctrl_irq_t>(32), irq_state));
}
TEST_F(IrqSetEnabledTest, Success) {
@@ -282,17 +262,15 @@
irq_state = kDifToggleEnabled;
EXPECT_MASK32(OTP_CTRL_INTR_ENABLE_REG_OFFSET,
{{OTP_CTRL_INTR_ENABLE_OTP_OPERATION_DONE_BIT, 0x1, true}});
- EXPECT_EQ(dif_otp_ctrl_irq_set_enabled(
- &otp_ctrl_, kDifOtpCtrlIrqOtpOperationDone, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_otp_ctrl_irq_set_enabled(
+ &otp_ctrl_, kDifOtpCtrlIrqOtpOperationDone, irq_state));
// Disable last IRQ.
irq_state = kDifToggleDisabled;
EXPECT_MASK32(OTP_CTRL_INTR_ENABLE_REG_OFFSET,
{{OTP_CTRL_INTR_ENABLE_OTP_ERROR_BIT, 0x1, false}});
- EXPECT_EQ(dif_otp_ctrl_irq_set_enabled(&otp_ctrl_, kDifOtpCtrlIrqOtpError,
- irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_otp_ctrl_irq_set_enabled(&otp_ctrl_, kDifOtpCtrlIrqOtpError,
+ irq_state));
}
class IrqDisableAllTest : public OtpCtrlTest {};
@@ -300,14 +278,14 @@
TEST_F(IrqDisableAllTest, NullArgs) {
dif_otp_ctrl_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_otp_ctrl_irq_disable_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otp_ctrl_irq_disable_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_otp_ctrl_irq_disable_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otp_ctrl_irq_disable_all(nullptr, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessNoSnapshot) {
EXPECT_WRITE32(OTP_CTRL_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_otp_ctrl_irq_disable_all(&otp_ctrl_, nullptr), kDifOk);
+ EXPECT_DIF_OK(dif_otp_ctrl_irq_disable_all(&otp_ctrl_, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessSnapshotAllDisabled) {
@@ -315,7 +293,7 @@
EXPECT_READ32(OTP_CTRL_INTR_ENABLE_REG_OFFSET, 0);
EXPECT_WRITE32(OTP_CTRL_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_otp_ctrl_irq_disable_all(&otp_ctrl_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_otp_ctrl_irq_disable_all(&otp_ctrl_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -325,7 +303,7 @@
EXPECT_READ32(OTP_CTRL_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
EXPECT_WRITE32(OTP_CTRL_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_otp_ctrl_irq_disable_all(&otp_ctrl_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_otp_ctrl_irq_disable_all(&otp_ctrl_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -334,11 +312,11 @@
TEST_F(IrqRestoreAllTest, NullArgs) {
dif_otp_ctrl_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_otp_ctrl_irq_restore_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otp_ctrl_irq_restore_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_otp_ctrl_irq_restore_all(&otp_ctrl_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otp_ctrl_irq_restore_all(&otp_ctrl_, nullptr));
- EXPECT_EQ(dif_otp_ctrl_irq_restore_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_otp_ctrl_irq_restore_all(nullptr, nullptr));
}
TEST_F(IrqRestoreAllTest, SuccessAllEnabled) {
@@ -347,14 +325,14 @@
EXPECT_WRITE32(OTP_CTRL_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_otp_ctrl_irq_restore_all(&otp_ctrl_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_otp_ctrl_irq_restore_all(&otp_ctrl_, &irq_snapshot));
}
TEST_F(IrqRestoreAllTest, SuccessAllDisabled) {
dif_otp_ctrl_irq_enable_snapshot_t irq_snapshot = 0;
EXPECT_WRITE32(OTP_CTRL_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_otp_ctrl_irq_restore_all(&otp_ctrl_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_otp_ctrl_irq_restore_all(&otp_ctrl_, &irq_snapshot));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_pattgen_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_pattgen_autogen_unittest.cc
index f53381f..988ee8f 100644
--- a/sw/device/lib/dif/autogen/dif_pattgen_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_pattgen_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "pattgen_regs.h" // Generated.
@@ -28,32 +29,30 @@
class InitTest : public PattgenTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_pattgen_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pattgen_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_pattgen_init(dev().region(), &pattgen_), kDifOk);
+ EXPECT_DIF_OK(dif_pattgen_init(dev().region(), &pattgen_));
}
class AlertForceTest : public PattgenTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_pattgen_alert_force(nullptr, kDifPattgenAlertFatalFault),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_pattgen_alert_force(nullptr, kDifPattgenAlertFatalFault));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(
- dif_pattgen_alert_force(nullptr, static_cast<dif_pattgen_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_pattgen_alert_force(nullptr, static_cast<dif_pattgen_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(PATTGEN_ALERT_TEST_REG_OFFSET,
{{PATTGEN_ALERT_TEST_FATAL_FAULT_BIT, true}});
- EXPECT_EQ(dif_pattgen_alert_force(&pattgen_, kDifPattgenAlertFatalFault),
- kDifOk);
+ EXPECT_DIF_OK(dif_pattgen_alert_force(&pattgen_, kDifPattgenAlertFatalFault));
}
class IrqGetStateTest : public PattgenTest {};
@@ -61,11 +60,11 @@
TEST_F(IrqGetStateTest, NullArgs) {
dif_pattgen_irq_state_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_pattgen_irq_get_state(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pattgen_irq_get_state(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_pattgen_irq_get_state(&pattgen_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pattgen_irq_get_state(&pattgen_, nullptr));
- EXPECT_EQ(dif_pattgen_irq_get_state(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pattgen_irq_get_state(nullptr, nullptr));
}
TEST_F(IrqGetStateTest, SuccessAllRaised) {
@@ -73,7 +72,7 @@
EXPECT_READ32(PATTGEN_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_pattgen_irq_get_state(&pattgen_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_pattgen_irq_get_state(&pattgen_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -81,7 +80,7 @@
dif_pattgen_irq_state_snapshot_t irq_snapshot = 0;
EXPECT_READ32(PATTGEN_INTR_STATE_REG_OFFSET, 0);
- EXPECT_EQ(dif_pattgen_irq_get_state(&pattgen_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_pattgen_irq_get_state(&pattgen_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -90,24 +89,21 @@
TEST_F(IrqIsPendingTest, NullArgs) {
bool is_pending;
- EXPECT_EQ(
- dif_pattgen_irq_is_pending(nullptr, kDifPattgenIrqDoneCh0, &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_pattgen_irq_is_pending(nullptr, kDifPattgenIrqDoneCh0, &is_pending));
- EXPECT_EQ(
- dif_pattgen_irq_is_pending(&pattgen_, kDifPattgenIrqDoneCh0, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_pattgen_irq_is_pending(&pattgen_, kDifPattgenIrqDoneCh0, nullptr));
- EXPECT_EQ(dif_pattgen_irq_is_pending(nullptr, kDifPattgenIrqDoneCh0, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_pattgen_irq_is_pending(nullptr, kDifPattgenIrqDoneCh0, nullptr));
}
TEST_F(IrqIsPendingTest, BadIrq) {
bool is_pending;
// All interrupt CSRs are 32 bit so interrupt 32 will be invalid.
- EXPECT_EQ(dif_pattgen_irq_is_pending(
- &pattgen_, static_cast<dif_pattgen_irq_t>(32), &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pattgen_irq_is_pending(
+ &pattgen_, static_cast<dif_pattgen_irq_t>(32), &is_pending));
}
TEST_F(IrqIsPendingTest, Success) {
@@ -117,82 +113,77 @@
irq_state = false;
EXPECT_READ32(PATTGEN_INTR_STATE_REG_OFFSET,
{{PATTGEN_INTR_STATE_DONE_CH0_BIT, true}});
- EXPECT_EQ(
- dif_pattgen_irq_is_pending(&pattgen_, kDifPattgenIrqDoneCh0, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_pattgen_irq_is_pending(&pattgen_, kDifPattgenIrqDoneCh0, &irq_state));
EXPECT_TRUE(irq_state);
// Get the last IRQ state.
irq_state = true;
EXPECT_READ32(PATTGEN_INTR_STATE_REG_OFFSET,
{{PATTGEN_INTR_STATE_DONE_CH1_BIT, false}});
- EXPECT_EQ(
- dif_pattgen_irq_is_pending(&pattgen_, kDifPattgenIrqDoneCh1, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_pattgen_irq_is_pending(&pattgen_, kDifPattgenIrqDoneCh1, &irq_state));
EXPECT_FALSE(irq_state);
}
class AcknowledgeAllTest : public PattgenTest {};
TEST_F(AcknowledgeAllTest, NullArgs) {
- EXPECT_EQ(dif_pattgen_irq_acknowledge_all(nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pattgen_irq_acknowledge_all(nullptr));
}
TEST_F(AcknowledgeAllTest, Success) {
EXPECT_WRITE32(PATTGEN_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_pattgen_irq_acknowledge_all(&pattgen_), kDifOk);
+ EXPECT_DIF_OK(dif_pattgen_irq_acknowledge_all(&pattgen_));
}
class IrqAcknowledgeTest : public PattgenTest {};
TEST_F(IrqAcknowledgeTest, NullArgs) {
- EXPECT_EQ(dif_pattgen_irq_acknowledge(nullptr, kDifPattgenIrqDoneCh0),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_pattgen_irq_acknowledge(nullptr, kDifPattgenIrqDoneCh0));
}
TEST_F(IrqAcknowledgeTest, BadIrq) {
- EXPECT_EQ(
- dif_pattgen_irq_acknowledge(nullptr, static_cast<dif_pattgen_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_pattgen_irq_acknowledge(nullptr, static_cast<dif_pattgen_irq_t>(32)));
}
TEST_F(IrqAcknowledgeTest, Success) {
// Clear the first IRQ state.
EXPECT_WRITE32(PATTGEN_INTR_STATE_REG_OFFSET,
{{PATTGEN_INTR_STATE_DONE_CH0_BIT, true}});
- EXPECT_EQ(dif_pattgen_irq_acknowledge(&pattgen_, kDifPattgenIrqDoneCh0),
- kDifOk);
+ EXPECT_DIF_OK(dif_pattgen_irq_acknowledge(&pattgen_, kDifPattgenIrqDoneCh0));
// Clear the last IRQ state.
EXPECT_WRITE32(PATTGEN_INTR_STATE_REG_OFFSET,
{{PATTGEN_INTR_STATE_DONE_CH1_BIT, true}});
- EXPECT_EQ(dif_pattgen_irq_acknowledge(&pattgen_, kDifPattgenIrqDoneCh1),
- kDifOk);
+ EXPECT_DIF_OK(dif_pattgen_irq_acknowledge(&pattgen_, kDifPattgenIrqDoneCh1));
}
class IrqForceTest : public PattgenTest {};
TEST_F(IrqForceTest, NullArgs) {
- EXPECT_EQ(dif_pattgen_irq_force(nullptr, kDifPattgenIrqDoneCh0), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pattgen_irq_force(nullptr, kDifPattgenIrqDoneCh0));
}
TEST_F(IrqForceTest, BadIrq) {
- EXPECT_EQ(dif_pattgen_irq_force(nullptr, static_cast<dif_pattgen_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_pattgen_irq_force(nullptr, static_cast<dif_pattgen_irq_t>(32)));
}
TEST_F(IrqForceTest, Success) {
// Force first IRQ.
EXPECT_WRITE32(PATTGEN_INTR_TEST_REG_OFFSET,
{{PATTGEN_INTR_TEST_DONE_CH0_BIT, true}});
- EXPECT_EQ(dif_pattgen_irq_force(&pattgen_, kDifPattgenIrqDoneCh0), kDifOk);
+ EXPECT_DIF_OK(dif_pattgen_irq_force(&pattgen_, kDifPattgenIrqDoneCh0));
// Force last IRQ.
EXPECT_WRITE32(PATTGEN_INTR_TEST_REG_OFFSET,
{{PATTGEN_INTR_TEST_DONE_CH1_BIT, true}});
- EXPECT_EQ(dif_pattgen_irq_force(&pattgen_, kDifPattgenIrqDoneCh1), kDifOk);
+ EXPECT_DIF_OK(dif_pattgen_irq_force(&pattgen_, kDifPattgenIrqDoneCh1));
}
class IrqGetEnabledTest : public PattgenTest {};
@@ -200,25 +191,21 @@
TEST_F(IrqGetEnabledTest, NullArgs) {
dif_toggle_t irq_state;
- EXPECT_EQ(
- dif_pattgen_irq_get_enabled(nullptr, kDifPattgenIrqDoneCh0, &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_pattgen_irq_get_enabled(nullptr, kDifPattgenIrqDoneCh0, &irq_state));
- EXPECT_EQ(
- dif_pattgen_irq_get_enabled(&pattgen_, kDifPattgenIrqDoneCh0, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_pattgen_irq_get_enabled(&pattgen_, kDifPattgenIrqDoneCh0, nullptr));
- EXPECT_EQ(
- dif_pattgen_irq_get_enabled(nullptr, kDifPattgenIrqDoneCh0, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_pattgen_irq_get_enabled(nullptr, kDifPattgenIrqDoneCh0, nullptr));
}
TEST_F(IrqGetEnabledTest, BadIrq) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_pattgen_irq_get_enabled(
- &pattgen_, static_cast<dif_pattgen_irq_t>(32), &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pattgen_irq_get_enabled(
+ &pattgen_, static_cast<dif_pattgen_irq_t>(32), &irq_state));
}
TEST_F(IrqGetEnabledTest, Success) {
@@ -228,18 +215,16 @@
irq_state = kDifToggleDisabled;
EXPECT_READ32(PATTGEN_INTR_ENABLE_REG_OFFSET,
{{PATTGEN_INTR_ENABLE_DONE_CH0_BIT, true}});
- EXPECT_EQ(
- dif_pattgen_irq_get_enabled(&pattgen_, kDifPattgenIrqDoneCh0, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_pattgen_irq_get_enabled(&pattgen_, kDifPattgenIrqDoneCh0,
+ &irq_state));
EXPECT_EQ(irq_state, kDifToggleEnabled);
// Last IRQ is disabled.
irq_state = kDifToggleEnabled;
EXPECT_READ32(PATTGEN_INTR_ENABLE_REG_OFFSET,
{{PATTGEN_INTR_ENABLE_DONE_CH1_BIT, false}});
- EXPECT_EQ(
- dif_pattgen_irq_get_enabled(&pattgen_, kDifPattgenIrqDoneCh1, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_pattgen_irq_get_enabled(&pattgen_, kDifPattgenIrqDoneCh1,
+ &irq_state));
EXPECT_EQ(irq_state, kDifToggleDisabled);
}
@@ -248,17 +233,15 @@
TEST_F(IrqSetEnabledTest, NullArgs) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(
- dif_pattgen_irq_set_enabled(nullptr, kDifPattgenIrqDoneCh0, irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_pattgen_irq_set_enabled(nullptr, kDifPattgenIrqDoneCh0, irq_state));
}
TEST_F(IrqSetEnabledTest, BadIrq) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_pattgen_irq_set_enabled(
- &pattgen_, static_cast<dif_pattgen_irq_t>(32), irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pattgen_irq_set_enabled(
+ &pattgen_, static_cast<dif_pattgen_irq_t>(32), irq_state));
}
TEST_F(IrqSetEnabledTest, Success) {
@@ -268,17 +251,15 @@
irq_state = kDifToggleEnabled;
EXPECT_MASK32(PATTGEN_INTR_ENABLE_REG_OFFSET,
{{PATTGEN_INTR_ENABLE_DONE_CH0_BIT, 0x1, true}});
- EXPECT_EQ(
- dif_pattgen_irq_set_enabled(&pattgen_, kDifPattgenIrqDoneCh0, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_pattgen_irq_set_enabled(&pattgen_, kDifPattgenIrqDoneCh0, irq_state));
// Disable last IRQ.
irq_state = kDifToggleDisabled;
EXPECT_MASK32(PATTGEN_INTR_ENABLE_REG_OFFSET,
{{PATTGEN_INTR_ENABLE_DONE_CH1_BIT, 0x1, false}});
- EXPECT_EQ(
- dif_pattgen_irq_set_enabled(&pattgen_, kDifPattgenIrqDoneCh1, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_pattgen_irq_set_enabled(&pattgen_, kDifPattgenIrqDoneCh1, irq_state));
}
class IrqDisableAllTest : public PattgenTest {};
@@ -286,14 +267,14 @@
TEST_F(IrqDisableAllTest, NullArgs) {
dif_pattgen_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_pattgen_irq_disable_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pattgen_irq_disable_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_pattgen_irq_disable_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pattgen_irq_disable_all(nullptr, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessNoSnapshot) {
EXPECT_WRITE32(PATTGEN_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_pattgen_irq_disable_all(&pattgen_, nullptr), kDifOk);
+ EXPECT_DIF_OK(dif_pattgen_irq_disable_all(&pattgen_, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessSnapshotAllDisabled) {
@@ -301,7 +282,7 @@
EXPECT_READ32(PATTGEN_INTR_ENABLE_REG_OFFSET, 0);
EXPECT_WRITE32(PATTGEN_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_pattgen_irq_disable_all(&pattgen_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_pattgen_irq_disable_all(&pattgen_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -311,7 +292,7 @@
EXPECT_READ32(PATTGEN_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
EXPECT_WRITE32(PATTGEN_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_pattgen_irq_disable_all(&pattgen_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_pattgen_irq_disable_all(&pattgen_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -320,11 +301,11 @@
TEST_F(IrqRestoreAllTest, NullArgs) {
dif_pattgen_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_pattgen_irq_restore_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pattgen_irq_restore_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_pattgen_irq_restore_all(&pattgen_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pattgen_irq_restore_all(&pattgen_, nullptr));
- EXPECT_EQ(dif_pattgen_irq_restore_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pattgen_irq_restore_all(nullptr, nullptr));
}
TEST_F(IrqRestoreAllTest, SuccessAllEnabled) {
@@ -333,14 +314,14 @@
EXPECT_WRITE32(PATTGEN_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_pattgen_irq_restore_all(&pattgen_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_pattgen_irq_restore_all(&pattgen_, &irq_snapshot));
}
TEST_F(IrqRestoreAllTest, SuccessAllDisabled) {
dif_pattgen_irq_enable_snapshot_t irq_snapshot = 0;
EXPECT_WRITE32(PATTGEN_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_pattgen_irq_restore_all(&pattgen_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_pattgen_irq_restore_all(&pattgen_, &irq_snapshot));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_pinmux_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_pinmux_autogen_unittest.cc
index 7067ce2..143be7c 100644
--- a/sw/device/lib/dif/autogen/dif_pinmux_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_pinmux_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "pinmux_regs.h" // Generated.
@@ -28,32 +29,29 @@
class InitTest : public PinmuxTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_pinmux_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pinmux_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_pinmux_init(dev().region(), &pinmux_), kDifOk);
+ EXPECT_DIF_OK(dif_pinmux_init(dev().region(), &pinmux_));
}
class AlertForceTest : public PinmuxTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_pinmux_alert_force(nullptr, kDifPinmuxAlertFatalFault),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pinmux_alert_force(nullptr, kDifPinmuxAlertFatalFault));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(
- dif_pinmux_alert_force(nullptr, static_cast<dif_pinmux_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_pinmux_alert_force(nullptr, static_cast<dif_pinmux_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(PINMUX_ALERT_TEST_REG_OFFSET,
{{PINMUX_ALERT_TEST_FATAL_FAULT_BIT, true}});
- EXPECT_EQ(dif_pinmux_alert_force(&pinmux_, kDifPinmuxAlertFatalFault),
- kDifOk);
+ EXPECT_DIF_OK(dif_pinmux_alert_force(&pinmux_, kDifPinmuxAlertFatalFault));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_pwm_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_pwm_autogen_unittest.cc
index f761332..e57481b 100644
--- a/sw/device/lib/dif/autogen/dif_pwm_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_pwm_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "pwm_regs.h" // Generated.
@@ -28,29 +29,29 @@
class InitTest : public PwmTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_pwm_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pwm_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_pwm_init(dev().region(), &pwm_), kDifOk);
+ EXPECT_DIF_OK(dif_pwm_init(dev().region(), &pwm_));
}
class AlertForceTest : public PwmTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_pwm_alert_force(nullptr, kDifPwmAlertFatalFault), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pwm_alert_force(nullptr, kDifPwmAlertFatalFault));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(dif_pwm_alert_force(nullptr, static_cast<dif_pwm_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_pwm_alert_force(nullptr, static_cast<dif_pwm_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(PWM_ALERT_TEST_REG_OFFSET,
{{PWM_ALERT_TEST_FATAL_FAULT_BIT, true}});
- EXPECT_EQ(dif_pwm_alert_force(&pwm_, kDifPwmAlertFatalFault), kDifOk);
+ EXPECT_DIF_OK(dif_pwm_alert_force(&pwm_, kDifPwmAlertFatalFault));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_pwrmgr_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_pwrmgr_autogen_unittest.cc
index d0e91da..41a11f3 100644
--- a/sw/device/lib/dif/autogen/dif_pwrmgr_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_pwrmgr_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "pwrmgr_regs.h" // Generated.
@@ -28,32 +29,29 @@
class InitTest : public PwrmgrTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_pwrmgr_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pwrmgr_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_pwrmgr_init(dev().region(), &pwrmgr_), kDifOk);
+ EXPECT_DIF_OK(dif_pwrmgr_init(dev().region(), &pwrmgr_));
}
class AlertForceTest : public PwrmgrTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_pwrmgr_alert_force(nullptr, kDifPwrmgrAlertFatalFault),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pwrmgr_alert_force(nullptr, kDifPwrmgrAlertFatalFault));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(
- dif_pwrmgr_alert_force(nullptr, static_cast<dif_pwrmgr_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_pwrmgr_alert_force(nullptr, static_cast<dif_pwrmgr_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(PWRMGR_ALERT_TEST_REG_OFFSET,
{{PWRMGR_ALERT_TEST_FATAL_FAULT_BIT, true}});
- EXPECT_EQ(dif_pwrmgr_alert_force(&pwrmgr_, kDifPwrmgrAlertFatalFault),
- kDifOk);
+ EXPECT_DIF_OK(dif_pwrmgr_alert_force(&pwrmgr_, kDifPwrmgrAlertFatalFault));
}
class IrqGetStateTest : public PwrmgrTest {};
@@ -61,11 +59,11 @@
TEST_F(IrqGetStateTest, NullArgs) {
dif_pwrmgr_irq_state_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_pwrmgr_irq_get_state(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pwrmgr_irq_get_state(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_pwrmgr_irq_get_state(&pwrmgr_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pwrmgr_irq_get_state(&pwrmgr_, nullptr));
- EXPECT_EQ(dif_pwrmgr_irq_get_state(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pwrmgr_irq_get_state(nullptr, nullptr));
}
TEST_F(IrqGetStateTest, SuccessAllRaised) {
@@ -73,7 +71,7 @@
EXPECT_READ32(PWRMGR_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_pwrmgr_irq_get_state(&pwrmgr_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_pwrmgr_irq_get_state(&pwrmgr_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -81,7 +79,7 @@
dif_pwrmgr_irq_state_snapshot_t irq_snapshot = 0;
EXPECT_READ32(PWRMGR_INTR_STATE_REG_OFFSET, 0);
- EXPECT_EQ(dif_pwrmgr_irq_get_state(&pwrmgr_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_pwrmgr_irq_get_state(&pwrmgr_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -90,23 +88,21 @@
TEST_F(IrqIsPendingTest, NullArgs) {
bool is_pending;
- EXPECT_EQ(
- dif_pwrmgr_irq_is_pending(nullptr, kDifPwrmgrIrqWakeup, &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_pwrmgr_irq_is_pending(nullptr, kDifPwrmgrIrqWakeup, &is_pending));
- EXPECT_EQ(dif_pwrmgr_irq_is_pending(&pwrmgr_, kDifPwrmgrIrqWakeup, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_pwrmgr_irq_is_pending(&pwrmgr_, kDifPwrmgrIrqWakeup, nullptr));
- EXPECT_EQ(dif_pwrmgr_irq_is_pending(nullptr, kDifPwrmgrIrqWakeup, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_pwrmgr_irq_is_pending(nullptr, kDifPwrmgrIrqWakeup, nullptr));
}
TEST_F(IrqIsPendingTest, BadIrq) {
bool is_pending;
// All interrupt CSRs are 32 bit so interrupt 32 will be invalid.
- EXPECT_EQ(dif_pwrmgr_irq_is_pending(
- &pwrmgr_, static_cast<dif_pwrmgr_irq_t>(32), &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pwrmgr_irq_is_pending(
+ &pwrmgr_, static_cast<dif_pwrmgr_irq_t>(32), &is_pending));
}
TEST_F(IrqIsPendingTest, Success) {
@@ -116,61 +112,58 @@
irq_state = false;
EXPECT_READ32(PWRMGR_INTR_STATE_REG_OFFSET,
{{PWRMGR_INTR_STATE_WAKEUP_BIT, true}});
- EXPECT_EQ(
- dif_pwrmgr_irq_is_pending(&pwrmgr_, kDifPwrmgrIrqWakeup, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_pwrmgr_irq_is_pending(&pwrmgr_, kDifPwrmgrIrqWakeup, &irq_state));
EXPECT_TRUE(irq_state);
}
class AcknowledgeAllTest : public PwrmgrTest {};
TEST_F(AcknowledgeAllTest, NullArgs) {
- EXPECT_EQ(dif_pwrmgr_irq_acknowledge_all(nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pwrmgr_irq_acknowledge_all(nullptr));
}
TEST_F(AcknowledgeAllTest, Success) {
EXPECT_WRITE32(PWRMGR_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_pwrmgr_irq_acknowledge_all(&pwrmgr_), kDifOk);
+ EXPECT_DIF_OK(dif_pwrmgr_irq_acknowledge_all(&pwrmgr_));
}
class IrqAcknowledgeTest : public PwrmgrTest {};
TEST_F(IrqAcknowledgeTest, NullArgs) {
- EXPECT_EQ(dif_pwrmgr_irq_acknowledge(nullptr, kDifPwrmgrIrqWakeup),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pwrmgr_irq_acknowledge(nullptr, kDifPwrmgrIrqWakeup));
}
TEST_F(IrqAcknowledgeTest, BadIrq) {
- EXPECT_EQ(
- dif_pwrmgr_irq_acknowledge(nullptr, static_cast<dif_pwrmgr_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_pwrmgr_irq_acknowledge(nullptr, static_cast<dif_pwrmgr_irq_t>(32)));
}
TEST_F(IrqAcknowledgeTest, Success) {
// Clear the first IRQ state.
EXPECT_WRITE32(PWRMGR_INTR_STATE_REG_OFFSET,
{{PWRMGR_INTR_STATE_WAKEUP_BIT, true}});
- EXPECT_EQ(dif_pwrmgr_irq_acknowledge(&pwrmgr_, kDifPwrmgrIrqWakeup), kDifOk);
+ EXPECT_DIF_OK(dif_pwrmgr_irq_acknowledge(&pwrmgr_, kDifPwrmgrIrqWakeup));
}
class IrqForceTest : public PwrmgrTest {};
TEST_F(IrqForceTest, NullArgs) {
- EXPECT_EQ(dif_pwrmgr_irq_force(nullptr, kDifPwrmgrIrqWakeup), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pwrmgr_irq_force(nullptr, kDifPwrmgrIrqWakeup));
}
TEST_F(IrqForceTest, BadIrq) {
- EXPECT_EQ(dif_pwrmgr_irq_force(nullptr, static_cast<dif_pwrmgr_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_pwrmgr_irq_force(nullptr, static_cast<dif_pwrmgr_irq_t>(32)));
}
TEST_F(IrqForceTest, Success) {
// Force first IRQ.
EXPECT_WRITE32(PWRMGR_INTR_TEST_REG_OFFSET,
{{PWRMGR_INTR_TEST_WAKEUP_BIT, true}});
- EXPECT_EQ(dif_pwrmgr_irq_force(&pwrmgr_, kDifPwrmgrIrqWakeup), kDifOk);
+ EXPECT_DIF_OK(dif_pwrmgr_irq_force(&pwrmgr_, kDifPwrmgrIrqWakeup));
}
class IrqGetEnabledTest : public PwrmgrTest {};
@@ -178,23 +171,21 @@
TEST_F(IrqGetEnabledTest, NullArgs) {
dif_toggle_t irq_state;
- EXPECT_EQ(
- dif_pwrmgr_irq_get_enabled(nullptr, kDifPwrmgrIrqWakeup, &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_pwrmgr_irq_get_enabled(nullptr, kDifPwrmgrIrqWakeup, &irq_state));
- EXPECT_EQ(dif_pwrmgr_irq_get_enabled(&pwrmgr_, kDifPwrmgrIrqWakeup, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_pwrmgr_irq_get_enabled(&pwrmgr_, kDifPwrmgrIrqWakeup, nullptr));
- EXPECT_EQ(dif_pwrmgr_irq_get_enabled(nullptr, kDifPwrmgrIrqWakeup, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_pwrmgr_irq_get_enabled(nullptr, kDifPwrmgrIrqWakeup, nullptr));
}
TEST_F(IrqGetEnabledTest, BadIrq) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_pwrmgr_irq_get_enabled(
- &pwrmgr_, static_cast<dif_pwrmgr_irq_t>(32), &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pwrmgr_irq_get_enabled(
+ &pwrmgr_, static_cast<dif_pwrmgr_irq_t>(32), &irq_state));
}
TEST_F(IrqGetEnabledTest, Success) {
@@ -204,9 +195,8 @@
irq_state = kDifToggleDisabled;
EXPECT_READ32(PWRMGR_INTR_ENABLE_REG_OFFSET,
{{PWRMGR_INTR_ENABLE_WAKEUP_BIT, true}});
- EXPECT_EQ(
- dif_pwrmgr_irq_get_enabled(&pwrmgr_, kDifPwrmgrIrqWakeup, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_pwrmgr_irq_get_enabled(&pwrmgr_, kDifPwrmgrIrqWakeup, &irq_state));
EXPECT_EQ(irq_state, kDifToggleEnabled);
}
@@ -215,16 +205,15 @@
TEST_F(IrqSetEnabledTest, NullArgs) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_pwrmgr_irq_set_enabled(nullptr, kDifPwrmgrIrqWakeup, irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_pwrmgr_irq_set_enabled(nullptr, kDifPwrmgrIrqWakeup, irq_state));
}
TEST_F(IrqSetEnabledTest, BadIrq) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_pwrmgr_irq_set_enabled(
- &pwrmgr_, static_cast<dif_pwrmgr_irq_t>(32), irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pwrmgr_irq_set_enabled(
+ &pwrmgr_, static_cast<dif_pwrmgr_irq_t>(32), irq_state));
}
TEST_F(IrqSetEnabledTest, Success) {
@@ -234,9 +223,8 @@
irq_state = kDifToggleEnabled;
EXPECT_MASK32(PWRMGR_INTR_ENABLE_REG_OFFSET,
{{PWRMGR_INTR_ENABLE_WAKEUP_BIT, 0x1, true}});
- EXPECT_EQ(
- dif_pwrmgr_irq_set_enabled(&pwrmgr_, kDifPwrmgrIrqWakeup, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_pwrmgr_irq_set_enabled(&pwrmgr_, kDifPwrmgrIrqWakeup, irq_state));
}
class IrqDisableAllTest : public PwrmgrTest {};
@@ -244,14 +232,14 @@
TEST_F(IrqDisableAllTest, NullArgs) {
dif_pwrmgr_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_pwrmgr_irq_disable_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pwrmgr_irq_disable_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_pwrmgr_irq_disable_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pwrmgr_irq_disable_all(nullptr, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessNoSnapshot) {
EXPECT_WRITE32(PWRMGR_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_pwrmgr_irq_disable_all(&pwrmgr_, nullptr), kDifOk);
+ EXPECT_DIF_OK(dif_pwrmgr_irq_disable_all(&pwrmgr_, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessSnapshotAllDisabled) {
@@ -259,7 +247,7 @@
EXPECT_READ32(PWRMGR_INTR_ENABLE_REG_OFFSET, 0);
EXPECT_WRITE32(PWRMGR_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_pwrmgr_irq_disable_all(&pwrmgr_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_pwrmgr_irq_disable_all(&pwrmgr_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -269,7 +257,7 @@
EXPECT_READ32(PWRMGR_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
EXPECT_WRITE32(PWRMGR_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_pwrmgr_irq_disable_all(&pwrmgr_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_pwrmgr_irq_disable_all(&pwrmgr_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -278,11 +266,11 @@
TEST_F(IrqRestoreAllTest, NullArgs) {
dif_pwrmgr_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_pwrmgr_irq_restore_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pwrmgr_irq_restore_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_pwrmgr_irq_restore_all(&pwrmgr_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pwrmgr_irq_restore_all(&pwrmgr_, nullptr));
- EXPECT_EQ(dif_pwrmgr_irq_restore_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_pwrmgr_irq_restore_all(nullptr, nullptr));
}
TEST_F(IrqRestoreAllTest, SuccessAllEnabled) {
@@ -291,14 +279,14 @@
EXPECT_WRITE32(PWRMGR_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_pwrmgr_irq_restore_all(&pwrmgr_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_pwrmgr_irq_restore_all(&pwrmgr_, &irq_snapshot));
}
TEST_F(IrqRestoreAllTest, SuccessAllDisabled) {
dif_pwrmgr_irq_enable_snapshot_t irq_snapshot = 0;
EXPECT_WRITE32(PWRMGR_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_pwrmgr_irq_restore_all(&pwrmgr_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_pwrmgr_irq_restore_all(&pwrmgr_, &irq_snapshot));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_rom_ctrl_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_rom_ctrl_autogen_unittest.cc
index 45af794..8aebc86 100644
--- a/sw/device/lib/dif/autogen/dif_rom_ctrl_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_rom_ctrl_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "rom_ctrl_regs.h" // Generated.
@@ -28,32 +29,29 @@
class InitTest : public RomCtrlTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_rom_ctrl_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rom_ctrl_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_rom_ctrl_init(dev().region(), &rom_ctrl_), kDifOk);
+ EXPECT_DIF_OK(dif_rom_ctrl_init(dev().region(), &rom_ctrl_));
}
class AlertForceTest : public RomCtrlTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_rom_ctrl_alert_force(nullptr, kDifRomCtrlAlertFatal),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rom_ctrl_alert_force(nullptr, kDifRomCtrlAlertFatal));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(
- dif_rom_ctrl_alert_force(nullptr, static_cast<dif_rom_ctrl_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_rom_ctrl_alert_force(nullptr, static_cast<dif_rom_ctrl_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(ROM_CTRL_ALERT_TEST_REG_OFFSET,
{{ROM_CTRL_ALERT_TEST_FATAL_BIT, true}});
- EXPECT_EQ(dif_rom_ctrl_alert_force(&rom_ctrl_, kDifRomCtrlAlertFatal),
- kDifOk);
+ EXPECT_DIF_OK(dif_rom_ctrl_alert_force(&rom_ctrl_, kDifRomCtrlAlertFatal));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_rstmgr_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_rstmgr_autogen_unittest.cc
index c274c16..fecf60c 100644
--- a/sw/device/lib/dif/autogen/dif_rstmgr_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_rstmgr_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "rstmgr_regs.h" // Generated.
@@ -28,38 +29,35 @@
class InitTest : public RstmgrTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_rstmgr_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rstmgr_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_rstmgr_init(dev().region(), &rstmgr_), kDifOk);
+ EXPECT_DIF_OK(dif_rstmgr_init(dev().region(), &rstmgr_));
}
class AlertForceTest : public RstmgrTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_rstmgr_alert_force(nullptr, kDifRstmgrAlertFatalFault),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rstmgr_alert_force(nullptr, kDifRstmgrAlertFatalFault));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(
- dif_rstmgr_alert_force(nullptr, static_cast<dif_rstmgr_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_rstmgr_alert_force(nullptr, static_cast<dif_rstmgr_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(RSTMGR_ALERT_TEST_REG_OFFSET,
{{RSTMGR_ALERT_TEST_FATAL_FAULT_BIT, true}});
- EXPECT_EQ(dif_rstmgr_alert_force(&rstmgr_, kDifRstmgrAlertFatalFault),
- kDifOk);
+ EXPECT_DIF_OK(dif_rstmgr_alert_force(&rstmgr_, kDifRstmgrAlertFatalFault));
// Force last alert.
EXPECT_WRITE32(RSTMGR_ALERT_TEST_REG_OFFSET,
{{RSTMGR_ALERT_TEST_FATAL_CNSTY_FAULT_BIT, true}});
- EXPECT_EQ(dif_rstmgr_alert_force(&rstmgr_, kDifRstmgrAlertFatalCnstyFault),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_rstmgr_alert_force(&rstmgr_, kDifRstmgrAlertFatalCnstyFault));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_rv_plic_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_rv_plic_autogen_unittest.cc
index d7a4e7e..06b59aa 100644
--- a/sw/device/lib/dif/autogen/dif_rv_plic_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_rv_plic_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "rv_plic_regs.h" // Generated.
@@ -28,32 +29,30 @@
class InitTest : public RvPlicTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_rv_plic_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rv_plic_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_rv_plic_init(dev().region(), &rv_plic_), kDifOk);
+ EXPECT_DIF_OK(dif_rv_plic_init(dev().region(), &rv_plic_));
}
class AlertForceTest : public RvPlicTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_rv_plic_alert_force(nullptr, kDifRvPlicAlertFatalFault),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_rv_plic_alert_force(nullptr, kDifRvPlicAlertFatalFault));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(
- dif_rv_plic_alert_force(nullptr, static_cast<dif_rv_plic_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_rv_plic_alert_force(nullptr, static_cast<dif_rv_plic_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(RV_PLIC_ALERT_TEST_REG_OFFSET,
{{RV_PLIC_ALERT_TEST_FATAL_FAULT_BIT, true}});
- EXPECT_EQ(dif_rv_plic_alert_force(&rv_plic_, kDifRvPlicAlertFatalFault),
- kDifOk);
+ EXPECT_DIF_OK(dif_rv_plic_alert_force(&rv_plic_, kDifRvPlicAlertFatalFault));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_rv_timer_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_rv_timer_autogen_unittest.cc
index 0381ccf..02910a5 100644
--- a/sw/device/lib/dif/autogen/dif_rv_timer_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_rv_timer_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "rv_timer_regs.h" // Generated.
@@ -28,32 +29,31 @@
class InitTest : public RvTimerTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_rv_timer_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rv_timer_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_rv_timer_init(dev().region(), &rv_timer_), kDifOk);
+ EXPECT_DIF_OK(dif_rv_timer_init(dev().region(), &rv_timer_));
}
class AlertForceTest : public RvTimerTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_rv_timer_alert_force(nullptr, kDifRvTimerAlertFatalFault),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_rv_timer_alert_force(nullptr, kDifRvTimerAlertFatalFault));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(
- dif_rv_timer_alert_force(nullptr, static_cast<dif_rv_timer_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_rv_timer_alert_force(nullptr, static_cast<dif_rv_timer_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(RV_TIMER_ALERT_TEST_REG_OFFSET,
{{RV_TIMER_ALERT_TEST_FATAL_FAULT_BIT, true}});
- EXPECT_EQ(dif_rv_timer_alert_force(&rv_timer_, kDifRvTimerAlertFatalFault),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_rv_timer_alert_force(&rv_timer_, kDifRvTimerAlertFatalFault));
}
class IrqGetStateTest : public RvTimerTest {};
@@ -61,11 +61,11 @@
TEST_F(IrqGetStateTest, NullArgs) {
dif_rv_timer_irq_state_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_rv_timer_irq_get_state(nullptr, 0, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rv_timer_irq_get_state(nullptr, 0, &irq_snapshot));
- EXPECT_EQ(dif_rv_timer_irq_get_state(&rv_timer_, 0, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rv_timer_irq_get_state(&rv_timer_, 0, nullptr));
- EXPECT_EQ(dif_rv_timer_irq_get_state(nullptr, 0, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rv_timer_irq_get_state(nullptr, 0, nullptr));
}
TEST_F(IrqGetStateTest, SuccessAllRaised) {
@@ -73,7 +73,7 @@
EXPECT_READ32(RV_TIMER_INTR_STATE0_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_rv_timer_irq_get_state(&rv_timer_, 0, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_rv_timer_irq_get_state(&rv_timer_, 0, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -81,7 +81,7 @@
dif_rv_timer_irq_state_snapshot_t irq_snapshot = 0;
EXPECT_READ32(RV_TIMER_INTR_STATE0_REG_OFFSET, 0);
- EXPECT_EQ(dif_rv_timer_irq_get_state(&rv_timer_, 0, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_rv_timer_irq_get_state(&rv_timer_, 0, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -90,25 +90,21 @@
TEST_F(IrqIsPendingTest, NullArgs) {
bool is_pending;
- EXPECT_EQ(dif_rv_timer_irq_is_pending(
- nullptr, kDifRvTimerIrqTimerExpiredHart0Timer0, &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rv_timer_irq_is_pending(
+ nullptr, kDifRvTimerIrqTimerExpiredHart0Timer0, &is_pending));
- EXPECT_EQ(dif_rv_timer_irq_is_pending(
- &rv_timer_, kDifRvTimerIrqTimerExpiredHart0Timer0, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rv_timer_irq_is_pending(
+ &rv_timer_, kDifRvTimerIrqTimerExpiredHart0Timer0, nullptr));
- EXPECT_EQ(dif_rv_timer_irq_is_pending(
- nullptr, kDifRvTimerIrqTimerExpiredHart0Timer0, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rv_timer_irq_is_pending(
+ nullptr, kDifRvTimerIrqTimerExpiredHart0Timer0, nullptr));
}
TEST_F(IrqIsPendingTest, BadIrq) {
bool is_pending;
// All interrupt CSRs are 32 bit so interrupt 32 will be invalid.
- EXPECT_EQ(dif_rv_timer_irq_is_pending(
- &rv_timer_, static_cast<dif_rv_timer_irq_t>(32), &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rv_timer_irq_is_pending(
+ &rv_timer_, static_cast<dif_rv_timer_irq_t>(32), &is_pending));
}
TEST_F(IrqIsPendingTest, Success) {
@@ -117,71 +113,64 @@
// Get the first IRQ state.
irq_state = false;
EXPECT_READ32(RV_TIMER_INTR_STATE0_REG_OFFSET, {{0, true}});
- EXPECT_EQ(dif_rv_timer_irq_is_pending(
- &rv_timer_, kDifRvTimerIrqTimerExpiredHart0Timer0, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_rv_timer_irq_is_pending(
+ &rv_timer_, kDifRvTimerIrqTimerExpiredHart0Timer0, &irq_state));
EXPECT_TRUE(irq_state);
}
class AcknowledgeAllTest : public RvTimerTest {};
TEST_F(AcknowledgeAllTest, NullArgs) {
- EXPECT_EQ(dif_rv_timer_irq_acknowledge_all(nullptr, 0), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rv_timer_irq_acknowledge_all(nullptr, 0));
}
TEST_F(AcknowledgeAllTest, BadHartId) {
- EXPECT_EQ(dif_rv_timer_irq_acknowledge_all(nullptr, 1), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rv_timer_irq_acknowledge_all(nullptr, 1));
}
TEST_F(AcknowledgeAllTest, Success) {
EXPECT_WRITE32(RV_TIMER_INTR_STATE0_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_rv_timer_irq_acknowledge_all(&rv_timer_, 0), kDifOk);
+ EXPECT_DIF_OK(dif_rv_timer_irq_acknowledge_all(&rv_timer_, 0));
}
class IrqAcknowledgeTest : public RvTimerTest {};
TEST_F(IrqAcknowledgeTest, NullArgs) {
- EXPECT_EQ(dif_rv_timer_irq_acknowledge(nullptr,
- kDifRvTimerIrqTimerExpiredHart0Timer0),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rv_timer_irq_acknowledge(
+ nullptr, kDifRvTimerIrqTimerExpiredHart0Timer0));
}
TEST_F(IrqAcknowledgeTest, BadIrq) {
- EXPECT_EQ(dif_rv_timer_irq_acknowledge(nullptr,
- static_cast<dif_rv_timer_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rv_timer_irq_acknowledge(
+ nullptr, static_cast<dif_rv_timer_irq_t>(32)));
}
TEST_F(IrqAcknowledgeTest, Success) {
// Clear the first IRQ state.
EXPECT_WRITE32(RV_TIMER_INTR_STATE0_REG_OFFSET, {{0, true}});
- EXPECT_EQ(dif_rv_timer_irq_acknowledge(&rv_timer_,
- kDifRvTimerIrqTimerExpiredHart0Timer0),
- kDifOk);
+ EXPECT_DIF_OK(dif_rv_timer_irq_acknowledge(
+ &rv_timer_, kDifRvTimerIrqTimerExpiredHart0Timer0));
}
class IrqForceTest : public RvTimerTest {};
TEST_F(IrqForceTest, NullArgs) {
- EXPECT_EQ(
- dif_rv_timer_irq_force(nullptr, kDifRvTimerIrqTimerExpiredHart0Timer0),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_rv_timer_irq_force(nullptr, kDifRvTimerIrqTimerExpiredHart0Timer0));
}
TEST_F(IrqForceTest, BadIrq) {
- EXPECT_EQ(
- dif_rv_timer_irq_force(nullptr, static_cast<dif_rv_timer_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_rv_timer_irq_force(nullptr, static_cast<dif_rv_timer_irq_t>(32)));
}
TEST_F(IrqForceTest, Success) {
// Force first IRQ.
EXPECT_WRITE32(RV_TIMER_INTR_TEST0_REG_OFFSET, {{0, true}});
- EXPECT_EQ(
- dif_rv_timer_irq_force(&rv_timer_, kDifRvTimerIrqTimerExpiredHart0Timer0),
- kDifOk);
+ EXPECT_DIF_OK(dif_rv_timer_irq_force(&rv_timer_,
+ kDifRvTimerIrqTimerExpiredHart0Timer0));
}
class IrqGetEnabledTest : public RvTimerTest {};
@@ -189,25 +178,21 @@
TEST_F(IrqGetEnabledTest, NullArgs) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_rv_timer_irq_get_enabled(
- nullptr, kDifRvTimerIrqTimerExpiredHart0Timer0, &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rv_timer_irq_get_enabled(
+ nullptr, kDifRvTimerIrqTimerExpiredHart0Timer0, &irq_state));
- EXPECT_EQ(dif_rv_timer_irq_get_enabled(
- &rv_timer_, kDifRvTimerIrqTimerExpiredHart0Timer0, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rv_timer_irq_get_enabled(
+ &rv_timer_, kDifRvTimerIrqTimerExpiredHart0Timer0, nullptr));
- EXPECT_EQ(dif_rv_timer_irq_get_enabled(
- nullptr, kDifRvTimerIrqTimerExpiredHart0Timer0, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rv_timer_irq_get_enabled(
+ nullptr, kDifRvTimerIrqTimerExpiredHart0Timer0, nullptr));
}
TEST_F(IrqGetEnabledTest, BadIrq) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_rv_timer_irq_get_enabled(
- &rv_timer_, static_cast<dif_rv_timer_irq_t>(32), &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rv_timer_irq_get_enabled(
+ &rv_timer_, static_cast<dif_rv_timer_irq_t>(32), &irq_state));
}
TEST_F(IrqGetEnabledTest, Success) {
@@ -216,9 +201,8 @@
// First IRQ is enabled.
irq_state = kDifToggleDisabled;
EXPECT_READ32(RV_TIMER_INTR_ENABLE0_REG_OFFSET, {{0, true}});
- EXPECT_EQ(dif_rv_timer_irq_get_enabled(
- &rv_timer_, kDifRvTimerIrqTimerExpiredHart0Timer0, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_rv_timer_irq_get_enabled(
+ &rv_timer_, kDifRvTimerIrqTimerExpiredHart0Timer0, &irq_state));
EXPECT_EQ(irq_state, kDifToggleEnabled);
}
@@ -227,17 +211,15 @@
TEST_F(IrqSetEnabledTest, NullArgs) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_rv_timer_irq_set_enabled(
- nullptr, kDifRvTimerIrqTimerExpiredHart0Timer0, irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rv_timer_irq_set_enabled(
+ nullptr, kDifRvTimerIrqTimerExpiredHart0Timer0, irq_state));
}
TEST_F(IrqSetEnabledTest, BadIrq) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_rv_timer_irq_set_enabled(
- &rv_timer_, static_cast<dif_rv_timer_irq_t>(32), irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rv_timer_irq_set_enabled(
+ &rv_timer_, static_cast<dif_rv_timer_irq_t>(32), irq_state));
}
TEST_F(IrqSetEnabledTest, Success) {
@@ -246,9 +228,8 @@
// Enable first IRQ.
irq_state = kDifToggleEnabled;
EXPECT_MASK32(RV_TIMER_INTR_ENABLE0_REG_OFFSET, {{0, 0x1, true}});
- EXPECT_EQ(dif_rv_timer_irq_set_enabled(
- &rv_timer_, kDifRvTimerIrqTimerExpiredHart0Timer0, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_rv_timer_irq_set_enabled(
+ &rv_timer_, kDifRvTimerIrqTimerExpiredHart0Timer0, irq_state));
}
class IrqDisableAllTest : public RvTimerTest {};
@@ -256,15 +237,14 @@
TEST_F(IrqDisableAllTest, NullArgs) {
dif_rv_timer_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_rv_timer_irq_disable_all(nullptr, 0, &irq_snapshot),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rv_timer_irq_disable_all(nullptr, 0, &irq_snapshot));
- EXPECT_EQ(dif_rv_timer_irq_disable_all(nullptr, 0, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rv_timer_irq_disable_all(nullptr, 0, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessNoSnapshot) {
EXPECT_WRITE32(RV_TIMER_INTR_ENABLE0_REG_OFFSET, 0);
- EXPECT_EQ(dif_rv_timer_irq_disable_all(&rv_timer_, 0, nullptr), kDifOk);
+ EXPECT_DIF_OK(dif_rv_timer_irq_disable_all(&rv_timer_, 0, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessSnapshotAllDisabled) {
@@ -272,7 +252,7 @@
EXPECT_READ32(RV_TIMER_INTR_ENABLE0_REG_OFFSET, 0);
EXPECT_WRITE32(RV_TIMER_INTR_ENABLE0_REG_OFFSET, 0);
- EXPECT_EQ(dif_rv_timer_irq_disable_all(&rv_timer_, 0, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_rv_timer_irq_disable_all(&rv_timer_, 0, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -282,7 +262,7 @@
EXPECT_READ32(RV_TIMER_INTR_ENABLE0_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
EXPECT_WRITE32(RV_TIMER_INTR_ENABLE0_REG_OFFSET, 0);
- EXPECT_EQ(dif_rv_timer_irq_disable_all(&rv_timer_, 0, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_rv_timer_irq_disable_all(&rv_timer_, 0, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -291,12 +271,11 @@
TEST_F(IrqRestoreAllTest, NullArgs) {
dif_rv_timer_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_rv_timer_irq_restore_all(nullptr, 0, &irq_snapshot),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rv_timer_irq_restore_all(nullptr, 0, &irq_snapshot));
- EXPECT_EQ(dif_rv_timer_irq_restore_all(&rv_timer_, 0, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rv_timer_irq_restore_all(&rv_timer_, 0, nullptr));
- EXPECT_EQ(dif_rv_timer_irq_restore_all(nullptr, 0, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_rv_timer_irq_restore_all(nullptr, 0, nullptr));
}
TEST_F(IrqRestoreAllTest, SuccessAllEnabled) {
@@ -305,14 +284,14 @@
EXPECT_WRITE32(RV_TIMER_INTR_ENABLE0_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_rv_timer_irq_restore_all(&rv_timer_, 0, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_rv_timer_irq_restore_all(&rv_timer_, 0, &irq_snapshot));
}
TEST_F(IrqRestoreAllTest, SuccessAllDisabled) {
dif_rv_timer_irq_enable_snapshot_t irq_snapshot = 0;
EXPECT_WRITE32(RV_TIMER_INTR_ENABLE0_REG_OFFSET, 0);
- EXPECT_EQ(dif_rv_timer_irq_restore_all(&rv_timer_, 0, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_rv_timer_irq_restore_all(&rv_timer_, 0, &irq_snapshot));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_spi_device_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_spi_device_autogen_unittest.cc
index d99066d..b34ca48 100644
--- a/sw/device/lib/dif/autogen/dif_spi_device_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_spi_device_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "spi_device_regs.h" // Generated.
@@ -28,33 +29,31 @@
class InitTest : public SpiDeviceTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_spi_device_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_device_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_spi_device_init(dev().region(), &spi_device_), kDifOk);
+ EXPECT_DIF_OK(dif_spi_device_init(dev().region(), &spi_device_));
}
class AlertForceTest : public SpiDeviceTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_spi_device_alert_force(nullptr, kDifSpiDeviceAlertFatalFault),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_spi_device_alert_force(nullptr, kDifSpiDeviceAlertFatalFault));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(dif_spi_device_alert_force(nullptr,
- static_cast<dif_spi_device_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_device_alert_force(
+ nullptr, static_cast<dif_spi_device_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(SPI_DEVICE_ALERT_TEST_REG_OFFSET,
{{SPI_DEVICE_ALERT_TEST_FATAL_FAULT_BIT, true}});
- EXPECT_EQ(
- dif_spi_device_alert_force(&spi_device_, kDifSpiDeviceAlertFatalFault),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_spi_device_alert_force(&spi_device_, kDifSpiDeviceAlertFatalFault));
}
class IrqGetStateTest : public SpiDeviceTest {};
@@ -62,11 +61,11 @@
TEST_F(IrqGetStateTest, NullArgs) {
dif_spi_device_irq_state_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_spi_device_irq_get_state(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_device_irq_get_state(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_spi_device_irq_get_state(&spi_device_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_device_irq_get_state(&spi_device_, nullptr));
- EXPECT_EQ(dif_spi_device_irq_get_state(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_device_irq_get_state(nullptr, nullptr));
}
TEST_F(IrqGetStateTest, SuccessAllRaised) {
@@ -74,7 +73,7 @@
EXPECT_READ32(SPI_DEVICE_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_spi_device_irq_get_state(&spi_device_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_spi_device_irq_get_state(&spi_device_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -82,7 +81,7 @@
dif_spi_device_irq_state_snapshot_t irq_snapshot = 0;
EXPECT_READ32(SPI_DEVICE_INTR_STATE_REG_OFFSET, 0);
- EXPECT_EQ(dif_spi_device_irq_get_state(&spi_device_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_spi_device_irq_get_state(&spi_device_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -91,26 +90,21 @@
TEST_F(IrqIsPendingTest, NullArgs) {
bool is_pending;
- EXPECT_EQ(dif_spi_device_irq_is_pending(
- nullptr, kDifSpiDeviceIrqGenericRxFull, &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_device_irq_is_pending(
+ nullptr, kDifSpiDeviceIrqGenericRxFull, &is_pending));
- EXPECT_EQ(dif_spi_device_irq_is_pending(
- &spi_device_, kDifSpiDeviceIrqGenericRxFull, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_device_irq_is_pending(
+ &spi_device_, kDifSpiDeviceIrqGenericRxFull, nullptr));
- EXPECT_EQ(dif_spi_device_irq_is_pending(
- nullptr, kDifSpiDeviceIrqGenericRxFull, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_device_irq_is_pending(
+ nullptr, kDifSpiDeviceIrqGenericRxFull, nullptr));
}
TEST_F(IrqIsPendingTest, BadIrq) {
bool is_pending;
// All interrupt CSRs are 32 bit so interrupt 32 will be invalid.
- EXPECT_EQ(
- dif_spi_device_irq_is_pending(
- &spi_device_, static_cast<dif_spi_device_irq_t>(32), &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_device_irq_is_pending(
+ &spi_device_, static_cast<dif_spi_device_irq_t>(32), &is_pending));
}
TEST_F(IrqIsPendingTest, Success) {
@@ -120,91 +114,82 @@
irq_state = false;
EXPECT_READ32(SPI_DEVICE_INTR_STATE_REG_OFFSET,
{{SPI_DEVICE_INTR_STATE_GENERIC_RX_FULL_BIT, true}});
- EXPECT_EQ(dif_spi_device_irq_is_pending(
- &spi_device_, kDifSpiDeviceIrqGenericRxFull, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_spi_device_irq_is_pending(
+ &spi_device_, kDifSpiDeviceIrqGenericRxFull, &irq_state));
EXPECT_TRUE(irq_state);
// Get the last IRQ state.
irq_state = true;
EXPECT_READ32(SPI_DEVICE_INTR_STATE_REG_OFFSET,
{{SPI_DEVICE_INTR_STATE_TPM_HEADER_NOT_EMPTY_BIT, false}});
- EXPECT_EQ(dif_spi_device_irq_is_pending(
- &spi_device_, kDifSpiDeviceIrqTpmHeaderNotEmpty, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_spi_device_irq_is_pending(
+ &spi_device_, kDifSpiDeviceIrqTpmHeaderNotEmpty, &irq_state));
EXPECT_FALSE(irq_state);
}
class AcknowledgeAllTest : public SpiDeviceTest {};
TEST_F(AcknowledgeAllTest, NullArgs) {
- EXPECT_EQ(dif_spi_device_irq_acknowledge_all(nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_device_irq_acknowledge_all(nullptr));
}
TEST_F(AcknowledgeAllTest, Success) {
EXPECT_WRITE32(SPI_DEVICE_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_spi_device_irq_acknowledge_all(&spi_device_), kDifOk);
+ EXPECT_DIF_OK(dif_spi_device_irq_acknowledge_all(&spi_device_));
}
class IrqAcknowledgeTest : public SpiDeviceTest {};
TEST_F(IrqAcknowledgeTest, NullArgs) {
- EXPECT_EQ(
- dif_spi_device_irq_acknowledge(nullptr, kDifSpiDeviceIrqGenericRxFull),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_spi_device_irq_acknowledge(nullptr, kDifSpiDeviceIrqGenericRxFull));
}
TEST_F(IrqAcknowledgeTest, BadIrq) {
- EXPECT_EQ(dif_spi_device_irq_acknowledge(
- nullptr, static_cast<dif_spi_device_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_device_irq_acknowledge(
+ nullptr, static_cast<dif_spi_device_irq_t>(32)));
}
TEST_F(IrqAcknowledgeTest, Success) {
// Clear the first IRQ state.
EXPECT_WRITE32(SPI_DEVICE_INTR_STATE_REG_OFFSET,
{{SPI_DEVICE_INTR_STATE_GENERIC_RX_FULL_BIT, true}});
- EXPECT_EQ(dif_spi_device_irq_acknowledge(&spi_device_,
- kDifSpiDeviceIrqGenericRxFull),
- kDifOk);
+ EXPECT_DIF_OK(dif_spi_device_irq_acknowledge(&spi_device_,
+ kDifSpiDeviceIrqGenericRxFull));
// Clear the last IRQ state.
EXPECT_WRITE32(SPI_DEVICE_INTR_STATE_REG_OFFSET,
{{SPI_DEVICE_INTR_STATE_TPM_HEADER_NOT_EMPTY_BIT, true}});
- EXPECT_EQ(dif_spi_device_irq_acknowledge(&spi_device_,
- kDifSpiDeviceIrqTpmHeaderNotEmpty),
- kDifOk);
+ EXPECT_DIF_OK(dif_spi_device_irq_acknowledge(
+ &spi_device_, kDifSpiDeviceIrqTpmHeaderNotEmpty));
}
class IrqForceTest : public SpiDeviceTest {};
TEST_F(IrqForceTest, NullArgs) {
- EXPECT_EQ(dif_spi_device_irq_force(nullptr, kDifSpiDeviceIrqGenericRxFull),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_spi_device_irq_force(nullptr, kDifSpiDeviceIrqGenericRxFull));
}
TEST_F(IrqForceTest, BadIrq) {
- EXPECT_EQ(
- dif_spi_device_irq_force(nullptr, static_cast<dif_spi_device_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_spi_device_irq_force(nullptr, static_cast<dif_spi_device_irq_t>(32)));
}
TEST_F(IrqForceTest, Success) {
// Force first IRQ.
EXPECT_WRITE32(SPI_DEVICE_INTR_TEST_REG_OFFSET,
{{SPI_DEVICE_INTR_TEST_GENERIC_RX_FULL_BIT, true}});
- EXPECT_EQ(
- dif_spi_device_irq_force(&spi_device_, kDifSpiDeviceIrqGenericRxFull),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_spi_device_irq_force(&spi_device_, kDifSpiDeviceIrqGenericRxFull));
// Force last IRQ.
EXPECT_WRITE32(SPI_DEVICE_INTR_TEST_REG_OFFSET,
{{SPI_DEVICE_INTR_TEST_TPM_HEADER_NOT_EMPTY_BIT, true}});
- EXPECT_EQ(
- dif_spi_device_irq_force(&spi_device_, kDifSpiDeviceIrqTpmHeaderNotEmpty),
- kDifOk);
+ EXPECT_DIF_OK(dif_spi_device_irq_force(&spi_device_,
+ kDifSpiDeviceIrqTpmHeaderNotEmpty));
}
class IrqGetEnabledTest : public SpiDeviceTest {};
@@ -212,26 +197,21 @@
TEST_F(IrqGetEnabledTest, NullArgs) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_spi_device_irq_get_enabled(
- nullptr, kDifSpiDeviceIrqGenericRxFull, &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_device_irq_get_enabled(
+ nullptr, kDifSpiDeviceIrqGenericRxFull, &irq_state));
- EXPECT_EQ(dif_spi_device_irq_get_enabled(
- &spi_device_, kDifSpiDeviceIrqGenericRxFull, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_device_irq_get_enabled(
+ &spi_device_, kDifSpiDeviceIrqGenericRxFull, nullptr));
- EXPECT_EQ(dif_spi_device_irq_get_enabled(
- nullptr, kDifSpiDeviceIrqGenericRxFull, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_device_irq_get_enabled(
+ nullptr, kDifSpiDeviceIrqGenericRxFull, nullptr));
}
TEST_F(IrqGetEnabledTest, BadIrq) {
dif_toggle_t irq_state;
- EXPECT_EQ(
- dif_spi_device_irq_get_enabled(
- &spi_device_, static_cast<dif_spi_device_irq_t>(32), &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_device_irq_get_enabled(
+ &spi_device_, static_cast<dif_spi_device_irq_t>(32), &irq_state));
}
TEST_F(IrqGetEnabledTest, Success) {
@@ -241,18 +221,16 @@
irq_state = kDifToggleDisabled;
EXPECT_READ32(SPI_DEVICE_INTR_ENABLE_REG_OFFSET,
{{SPI_DEVICE_INTR_ENABLE_GENERIC_RX_FULL_BIT, true}});
- EXPECT_EQ(dif_spi_device_irq_get_enabled(
- &spi_device_, kDifSpiDeviceIrqGenericRxFull, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_spi_device_irq_get_enabled(
+ &spi_device_, kDifSpiDeviceIrqGenericRxFull, &irq_state));
EXPECT_EQ(irq_state, kDifToggleEnabled);
// Last IRQ is disabled.
irq_state = kDifToggleEnabled;
EXPECT_READ32(SPI_DEVICE_INTR_ENABLE_REG_OFFSET,
{{SPI_DEVICE_INTR_ENABLE_TPM_HEADER_NOT_EMPTY_BIT, false}});
- EXPECT_EQ(dif_spi_device_irq_get_enabled(
- &spi_device_, kDifSpiDeviceIrqTpmHeaderNotEmpty, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_spi_device_irq_get_enabled(
+ &spi_device_, kDifSpiDeviceIrqTpmHeaderNotEmpty, &irq_state));
EXPECT_EQ(irq_state, kDifToggleDisabled);
}
@@ -261,17 +239,15 @@
TEST_F(IrqSetEnabledTest, NullArgs) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_spi_device_irq_set_enabled(
- nullptr, kDifSpiDeviceIrqGenericRxFull, irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_device_irq_set_enabled(
+ nullptr, kDifSpiDeviceIrqGenericRxFull, irq_state));
}
TEST_F(IrqSetEnabledTest, BadIrq) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_spi_device_irq_set_enabled(
- &spi_device_, static_cast<dif_spi_device_irq_t>(32), irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_device_irq_set_enabled(
+ &spi_device_, static_cast<dif_spi_device_irq_t>(32), irq_state));
}
TEST_F(IrqSetEnabledTest, Success) {
@@ -281,18 +257,16 @@
irq_state = kDifToggleEnabled;
EXPECT_MASK32(SPI_DEVICE_INTR_ENABLE_REG_OFFSET,
{{SPI_DEVICE_INTR_ENABLE_GENERIC_RX_FULL_BIT, 0x1, true}});
- EXPECT_EQ(dif_spi_device_irq_set_enabled(
- &spi_device_, kDifSpiDeviceIrqGenericRxFull, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_spi_device_irq_set_enabled(
+ &spi_device_, kDifSpiDeviceIrqGenericRxFull, irq_state));
// Disable last IRQ.
irq_state = kDifToggleDisabled;
EXPECT_MASK32(
SPI_DEVICE_INTR_ENABLE_REG_OFFSET,
{{SPI_DEVICE_INTR_ENABLE_TPM_HEADER_NOT_EMPTY_BIT, 0x1, false}});
- EXPECT_EQ(dif_spi_device_irq_set_enabled(
- &spi_device_, kDifSpiDeviceIrqTpmHeaderNotEmpty, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_spi_device_irq_set_enabled(
+ &spi_device_, kDifSpiDeviceIrqTpmHeaderNotEmpty, irq_state));
}
class IrqDisableAllTest : public SpiDeviceTest {};
@@ -300,14 +274,14 @@
TEST_F(IrqDisableAllTest, NullArgs) {
dif_spi_device_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_spi_device_irq_disable_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_device_irq_disable_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_spi_device_irq_disable_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_device_irq_disable_all(nullptr, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessNoSnapshot) {
EXPECT_WRITE32(SPI_DEVICE_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_spi_device_irq_disable_all(&spi_device_, nullptr), kDifOk);
+ EXPECT_DIF_OK(dif_spi_device_irq_disable_all(&spi_device_, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessSnapshotAllDisabled) {
@@ -315,8 +289,7 @@
EXPECT_READ32(SPI_DEVICE_INTR_ENABLE_REG_OFFSET, 0);
EXPECT_WRITE32(SPI_DEVICE_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_spi_device_irq_disable_all(&spi_device_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(dif_spi_device_irq_disable_all(&spi_device_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -326,8 +299,7 @@
EXPECT_READ32(SPI_DEVICE_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
EXPECT_WRITE32(SPI_DEVICE_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_spi_device_irq_disable_all(&spi_device_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(dif_spi_device_irq_disable_all(&spi_device_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -336,11 +308,11 @@
TEST_F(IrqRestoreAllTest, NullArgs) {
dif_spi_device_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_spi_device_irq_restore_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_device_irq_restore_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_spi_device_irq_restore_all(&spi_device_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_device_irq_restore_all(&spi_device_, nullptr));
- EXPECT_EQ(dif_spi_device_irq_restore_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_device_irq_restore_all(nullptr, nullptr));
}
TEST_F(IrqRestoreAllTest, SuccessAllEnabled) {
@@ -349,16 +321,14 @@
EXPECT_WRITE32(SPI_DEVICE_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_spi_device_irq_restore_all(&spi_device_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(dif_spi_device_irq_restore_all(&spi_device_, &irq_snapshot));
}
TEST_F(IrqRestoreAllTest, SuccessAllDisabled) {
dif_spi_device_irq_enable_snapshot_t irq_snapshot = 0;
EXPECT_WRITE32(SPI_DEVICE_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_spi_device_irq_restore_all(&spi_device_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(dif_spi_device_irq_restore_all(&spi_device_, &irq_snapshot));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_spi_host_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_spi_host_autogen_unittest.cc
index ee10255..d8e47aa 100644
--- a/sw/device/lib/dif/autogen/dif_spi_host_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_spi_host_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "spi_host_regs.h" // Generated.
@@ -28,32 +29,31 @@
class InitTest : public SpiHostTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_spi_host_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_host_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_spi_host_init(dev().region(), &spi_host_), kDifOk);
+ EXPECT_DIF_OK(dif_spi_host_init(dev().region(), &spi_host_));
}
class AlertForceTest : public SpiHostTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_spi_host_alert_force(nullptr, kDifSpiHostAlertFatalFault),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_spi_host_alert_force(nullptr, kDifSpiHostAlertFatalFault));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(
- dif_spi_host_alert_force(nullptr, static_cast<dif_spi_host_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_spi_host_alert_force(nullptr, static_cast<dif_spi_host_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(SPI_HOST_ALERT_TEST_REG_OFFSET,
{{SPI_HOST_ALERT_TEST_FATAL_FAULT_BIT, true}});
- EXPECT_EQ(dif_spi_host_alert_force(&spi_host_, kDifSpiHostAlertFatalFault),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_spi_host_alert_force(&spi_host_, kDifSpiHostAlertFatalFault));
}
class IrqGetStateTest : public SpiHostTest {};
@@ -61,11 +61,11 @@
TEST_F(IrqGetStateTest, NullArgs) {
dif_spi_host_irq_state_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_spi_host_irq_get_state(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_host_irq_get_state(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_spi_host_irq_get_state(&spi_host_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_host_irq_get_state(&spi_host_, nullptr));
- EXPECT_EQ(dif_spi_host_irq_get_state(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_host_irq_get_state(nullptr, nullptr));
}
TEST_F(IrqGetStateTest, SuccessAllRaised) {
@@ -73,7 +73,7 @@
EXPECT_READ32(SPI_HOST_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_spi_host_irq_get_state(&spi_host_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_spi_host_irq_get_state(&spi_host_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -81,7 +81,7 @@
dif_spi_host_irq_state_snapshot_t irq_snapshot = 0;
EXPECT_READ32(SPI_HOST_INTR_STATE_REG_OFFSET, 0);
- EXPECT_EQ(dif_spi_host_irq_get_state(&spi_host_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_spi_host_irq_get_state(&spi_host_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -90,24 +90,21 @@
TEST_F(IrqIsPendingTest, NullArgs) {
bool is_pending;
- EXPECT_EQ(
- dif_spi_host_irq_is_pending(nullptr, kDifSpiHostIrqError, &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_spi_host_irq_is_pending(nullptr, kDifSpiHostIrqError, &is_pending));
- EXPECT_EQ(
- dif_spi_host_irq_is_pending(&spi_host_, kDifSpiHostIrqError, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_spi_host_irq_is_pending(&spi_host_, kDifSpiHostIrqError, nullptr));
- EXPECT_EQ(dif_spi_host_irq_is_pending(nullptr, kDifSpiHostIrqError, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_spi_host_irq_is_pending(nullptr, kDifSpiHostIrqError, nullptr));
}
TEST_F(IrqIsPendingTest, BadIrq) {
bool is_pending;
// All interrupt CSRs are 32 bit so interrupt 32 will be invalid.
- EXPECT_EQ(dif_spi_host_irq_is_pending(
- &spi_host_, static_cast<dif_spi_host_irq_t>(32), &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_host_irq_is_pending(
+ &spi_host_, static_cast<dif_spi_host_irq_t>(32), &is_pending));
}
TEST_F(IrqIsPendingTest, Success) {
@@ -117,83 +114,77 @@
irq_state = false;
EXPECT_READ32(SPI_HOST_INTR_STATE_REG_OFFSET,
{{SPI_HOST_INTR_STATE_ERROR_BIT, true}});
- EXPECT_EQ(
- dif_spi_host_irq_is_pending(&spi_host_, kDifSpiHostIrqError, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_spi_host_irq_is_pending(&spi_host_, kDifSpiHostIrqError, &irq_state));
EXPECT_TRUE(irq_state);
// Get the last IRQ state.
irq_state = true;
EXPECT_READ32(SPI_HOST_INTR_STATE_REG_OFFSET,
{{SPI_HOST_INTR_STATE_SPI_EVENT_BIT, false}});
- EXPECT_EQ(dif_spi_host_irq_is_pending(&spi_host_, kDifSpiHostIrqSpiEvent,
- &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_spi_host_irq_is_pending(&spi_host_, kDifSpiHostIrqSpiEvent,
+ &irq_state));
EXPECT_FALSE(irq_state);
}
class AcknowledgeAllTest : public SpiHostTest {};
TEST_F(AcknowledgeAllTest, NullArgs) {
- EXPECT_EQ(dif_spi_host_irq_acknowledge_all(nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_host_irq_acknowledge_all(nullptr));
}
TEST_F(AcknowledgeAllTest, Success) {
EXPECT_WRITE32(SPI_HOST_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_spi_host_irq_acknowledge_all(&spi_host_), kDifOk);
+ EXPECT_DIF_OK(dif_spi_host_irq_acknowledge_all(&spi_host_));
}
class IrqAcknowledgeTest : public SpiHostTest {};
TEST_F(IrqAcknowledgeTest, NullArgs) {
- EXPECT_EQ(dif_spi_host_irq_acknowledge(nullptr, kDifSpiHostIrqError),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_host_irq_acknowledge(nullptr, kDifSpiHostIrqError));
}
TEST_F(IrqAcknowledgeTest, BadIrq) {
- EXPECT_EQ(dif_spi_host_irq_acknowledge(nullptr,
- static_cast<dif_spi_host_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_host_irq_acknowledge(
+ nullptr, static_cast<dif_spi_host_irq_t>(32)));
}
TEST_F(IrqAcknowledgeTest, Success) {
// Clear the first IRQ state.
EXPECT_WRITE32(SPI_HOST_INTR_STATE_REG_OFFSET,
{{SPI_HOST_INTR_STATE_ERROR_BIT, true}});
- EXPECT_EQ(dif_spi_host_irq_acknowledge(&spi_host_, kDifSpiHostIrqError),
- kDifOk);
+ EXPECT_DIF_OK(dif_spi_host_irq_acknowledge(&spi_host_, kDifSpiHostIrqError));
// Clear the last IRQ state.
EXPECT_WRITE32(SPI_HOST_INTR_STATE_REG_OFFSET,
{{SPI_HOST_INTR_STATE_SPI_EVENT_BIT, true}});
- EXPECT_EQ(dif_spi_host_irq_acknowledge(&spi_host_, kDifSpiHostIrqSpiEvent),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_spi_host_irq_acknowledge(&spi_host_, kDifSpiHostIrqSpiEvent));
}
class IrqForceTest : public SpiHostTest {};
TEST_F(IrqForceTest, NullArgs) {
- EXPECT_EQ(dif_spi_host_irq_force(nullptr, kDifSpiHostIrqError), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_host_irq_force(nullptr, kDifSpiHostIrqError));
}
TEST_F(IrqForceTest, BadIrq) {
- EXPECT_EQ(
- dif_spi_host_irq_force(nullptr, static_cast<dif_spi_host_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_spi_host_irq_force(nullptr, static_cast<dif_spi_host_irq_t>(32)));
}
TEST_F(IrqForceTest, Success) {
// Force first IRQ.
EXPECT_WRITE32(SPI_HOST_INTR_TEST_REG_OFFSET,
{{SPI_HOST_INTR_TEST_ERROR_BIT, true}});
- EXPECT_EQ(dif_spi_host_irq_force(&spi_host_, kDifSpiHostIrqError), kDifOk);
+ EXPECT_DIF_OK(dif_spi_host_irq_force(&spi_host_, kDifSpiHostIrqError));
// Force last IRQ.
EXPECT_WRITE32(SPI_HOST_INTR_TEST_REG_OFFSET,
{{SPI_HOST_INTR_TEST_SPI_EVENT_BIT, true}});
- EXPECT_EQ(dif_spi_host_irq_force(&spi_host_, kDifSpiHostIrqSpiEvent), kDifOk);
+ EXPECT_DIF_OK(dif_spi_host_irq_force(&spi_host_, kDifSpiHostIrqSpiEvent));
}
class IrqGetEnabledTest : public SpiHostTest {};
@@ -201,24 +192,21 @@
TEST_F(IrqGetEnabledTest, NullArgs) {
dif_toggle_t irq_state;
- EXPECT_EQ(
- dif_spi_host_irq_get_enabled(nullptr, kDifSpiHostIrqError, &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_spi_host_irq_get_enabled(nullptr, kDifSpiHostIrqError, &irq_state));
- EXPECT_EQ(
- dif_spi_host_irq_get_enabled(&spi_host_, kDifSpiHostIrqError, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_spi_host_irq_get_enabled(&spi_host_, kDifSpiHostIrqError, nullptr));
- EXPECT_EQ(dif_spi_host_irq_get_enabled(nullptr, kDifSpiHostIrqError, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_spi_host_irq_get_enabled(nullptr, kDifSpiHostIrqError, nullptr));
}
TEST_F(IrqGetEnabledTest, BadIrq) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_spi_host_irq_get_enabled(
- &spi_host_, static_cast<dif_spi_host_irq_t>(32), &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_host_irq_get_enabled(
+ &spi_host_, static_cast<dif_spi_host_irq_t>(32), &irq_state));
}
TEST_F(IrqGetEnabledTest, Success) {
@@ -228,18 +216,16 @@
irq_state = kDifToggleDisabled;
EXPECT_READ32(SPI_HOST_INTR_ENABLE_REG_OFFSET,
{{SPI_HOST_INTR_ENABLE_ERROR_BIT, true}});
- EXPECT_EQ(
- dif_spi_host_irq_get_enabled(&spi_host_, kDifSpiHostIrqError, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_spi_host_irq_get_enabled(&spi_host_, kDifSpiHostIrqError,
+ &irq_state));
EXPECT_EQ(irq_state, kDifToggleEnabled);
// Last IRQ is disabled.
irq_state = kDifToggleEnabled;
EXPECT_READ32(SPI_HOST_INTR_ENABLE_REG_OFFSET,
{{SPI_HOST_INTR_ENABLE_SPI_EVENT_BIT, false}});
- EXPECT_EQ(dif_spi_host_irq_get_enabled(&spi_host_, kDifSpiHostIrqSpiEvent,
- &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_spi_host_irq_get_enabled(&spi_host_, kDifSpiHostIrqSpiEvent,
+ &irq_state));
EXPECT_EQ(irq_state, kDifToggleDisabled);
}
@@ -248,17 +234,15 @@
TEST_F(IrqSetEnabledTest, NullArgs) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(
- dif_spi_host_irq_set_enabled(nullptr, kDifSpiHostIrqError, irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_spi_host_irq_set_enabled(nullptr, kDifSpiHostIrqError, irq_state));
}
TEST_F(IrqSetEnabledTest, BadIrq) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_spi_host_irq_set_enabled(
- &spi_host_, static_cast<dif_spi_host_irq_t>(32), irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_host_irq_set_enabled(
+ &spi_host_, static_cast<dif_spi_host_irq_t>(32), irq_state));
}
TEST_F(IrqSetEnabledTest, Success) {
@@ -268,17 +252,15 @@
irq_state = kDifToggleEnabled;
EXPECT_MASK32(SPI_HOST_INTR_ENABLE_REG_OFFSET,
{{SPI_HOST_INTR_ENABLE_ERROR_BIT, 0x1, true}});
- EXPECT_EQ(
- dif_spi_host_irq_set_enabled(&spi_host_, kDifSpiHostIrqError, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_spi_host_irq_set_enabled(&spi_host_, kDifSpiHostIrqError, irq_state));
// Disable last IRQ.
irq_state = kDifToggleDisabled;
EXPECT_MASK32(SPI_HOST_INTR_ENABLE_REG_OFFSET,
{{SPI_HOST_INTR_ENABLE_SPI_EVENT_BIT, 0x1, false}});
- EXPECT_EQ(dif_spi_host_irq_set_enabled(&spi_host_, kDifSpiHostIrqSpiEvent,
- irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_spi_host_irq_set_enabled(&spi_host_, kDifSpiHostIrqSpiEvent,
+ irq_state));
}
class IrqDisableAllTest : public SpiHostTest {};
@@ -286,14 +268,14 @@
TEST_F(IrqDisableAllTest, NullArgs) {
dif_spi_host_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_spi_host_irq_disable_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_host_irq_disable_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_spi_host_irq_disable_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_host_irq_disable_all(nullptr, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessNoSnapshot) {
EXPECT_WRITE32(SPI_HOST_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_spi_host_irq_disable_all(&spi_host_, nullptr), kDifOk);
+ EXPECT_DIF_OK(dif_spi_host_irq_disable_all(&spi_host_, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessSnapshotAllDisabled) {
@@ -301,7 +283,7 @@
EXPECT_READ32(SPI_HOST_INTR_ENABLE_REG_OFFSET, 0);
EXPECT_WRITE32(SPI_HOST_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_spi_host_irq_disable_all(&spi_host_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_spi_host_irq_disable_all(&spi_host_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -311,7 +293,7 @@
EXPECT_READ32(SPI_HOST_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
EXPECT_WRITE32(SPI_HOST_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_spi_host_irq_disable_all(&spi_host_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_spi_host_irq_disable_all(&spi_host_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -320,11 +302,11 @@
TEST_F(IrqRestoreAllTest, NullArgs) {
dif_spi_host_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_spi_host_irq_restore_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_host_irq_restore_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_spi_host_irq_restore_all(&spi_host_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_host_irq_restore_all(&spi_host_, nullptr));
- EXPECT_EQ(dif_spi_host_irq_restore_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_spi_host_irq_restore_all(nullptr, nullptr));
}
TEST_F(IrqRestoreAllTest, SuccessAllEnabled) {
@@ -333,14 +315,14 @@
EXPECT_WRITE32(SPI_HOST_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_spi_host_irq_restore_all(&spi_host_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_spi_host_irq_restore_all(&spi_host_, &irq_snapshot));
}
TEST_F(IrqRestoreAllTest, SuccessAllDisabled) {
dif_spi_host_irq_enable_snapshot_t irq_snapshot = 0;
EXPECT_WRITE32(SPI_HOST_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_spi_host_irq_restore_all(&spi_host_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_spi_host_irq_restore_all(&spi_host_, &irq_snapshot));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_sram_ctrl_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_sram_ctrl_autogen_unittest.cc
index 6b61484..9d00567 100644
--- a/sw/device/lib/dif/autogen/dif_sram_ctrl_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_sram_ctrl_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "sram_ctrl_regs.h" // Generated.
@@ -28,32 +29,31 @@
class InitTest : public SramCtrlTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_sram_ctrl_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_sram_ctrl_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_sram_ctrl_init(dev().region(), &sram_ctrl_), kDifOk);
+ EXPECT_DIF_OK(dif_sram_ctrl_init(dev().region(), &sram_ctrl_));
}
class AlertForceTest : public SramCtrlTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_sram_ctrl_alert_force(nullptr, kDifSramCtrlAlertFatalError),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_sram_ctrl_alert_force(nullptr, kDifSramCtrlAlertFatalError));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(dif_sram_ctrl_alert_force(nullptr,
- static_cast<dif_sram_ctrl_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_sram_ctrl_alert_force(
+ nullptr, static_cast<dif_sram_ctrl_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(SRAM_CTRL_ALERT_TEST_REG_OFFSET,
{{SRAM_CTRL_ALERT_TEST_FATAL_ERROR_BIT, true}});
- EXPECT_EQ(dif_sram_ctrl_alert_force(&sram_ctrl_, kDifSramCtrlAlertFatalError),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_sram_ctrl_alert_force(&sram_ctrl_, kDifSramCtrlAlertFatalError));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_sysrst_ctrl_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_sysrst_ctrl_autogen_unittest.cc
index 6ec13fa..e76dde5 100644
--- a/sw/device/lib/dif/autogen/dif_sysrst_ctrl_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_sysrst_ctrl_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "sysrst_ctrl_regs.h" // Generated.
@@ -28,33 +29,31 @@
class InitTest : public SysrstCtrlTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_sysrst_ctrl_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_sysrst_ctrl_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_sysrst_ctrl_init(dev().region(), &sysrst_ctrl_), kDifOk);
+ EXPECT_DIF_OK(dif_sysrst_ctrl_init(dev().region(), &sysrst_ctrl_));
}
class AlertForceTest : public SysrstCtrlTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_sysrst_ctrl_alert_force(nullptr, kDifSysrstCtrlAlertFatalFault),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_sysrst_ctrl_alert_force(nullptr, kDifSysrstCtrlAlertFatalFault));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(dif_sysrst_ctrl_alert_force(
- nullptr, static_cast<dif_sysrst_ctrl_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_sysrst_ctrl_alert_force(
+ nullptr, static_cast<dif_sysrst_ctrl_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(SYSRST_CTRL_ALERT_TEST_REG_OFFSET,
{{SYSRST_CTRL_ALERT_TEST_FATAL_FAULT_BIT, true}});
- EXPECT_EQ(
- dif_sysrst_ctrl_alert_force(&sysrst_ctrl_, kDifSysrstCtrlAlertFatalFault),
- kDifOk);
+ EXPECT_DIF_OK(dif_sysrst_ctrl_alert_force(&sysrst_ctrl_,
+ kDifSysrstCtrlAlertFatalFault));
}
class IrqGetStateTest : public SysrstCtrlTest {};
@@ -62,11 +61,11 @@
TEST_F(IrqGetStateTest, NullArgs) {
dif_sysrst_ctrl_irq_state_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_sysrst_ctrl_irq_get_state(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_sysrst_ctrl_irq_get_state(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_sysrst_ctrl_irq_get_state(&sysrst_ctrl_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_sysrst_ctrl_irq_get_state(&sysrst_ctrl_, nullptr));
- EXPECT_EQ(dif_sysrst_ctrl_irq_get_state(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_sysrst_ctrl_irq_get_state(nullptr, nullptr));
}
TEST_F(IrqGetStateTest, SuccessAllRaised) {
@@ -74,8 +73,7 @@
EXPECT_READ32(SYSRST_CTRL_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_sysrst_ctrl_irq_get_state(&sysrst_ctrl_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(dif_sysrst_ctrl_irq_get_state(&sysrst_ctrl_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -83,8 +81,7 @@
dif_sysrst_ctrl_irq_state_snapshot_t irq_snapshot = 0;
EXPECT_READ32(SYSRST_CTRL_INTR_STATE_REG_OFFSET, 0);
- EXPECT_EQ(dif_sysrst_ctrl_irq_get_state(&sysrst_ctrl_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(dif_sysrst_ctrl_irq_get_state(&sysrst_ctrl_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -93,26 +90,21 @@
TEST_F(IrqIsPendingTest, NullArgs) {
bool is_pending;
- EXPECT_EQ(dif_sysrst_ctrl_irq_is_pending(nullptr, kDifSysrstCtrlIrqSysrstCtrl,
- &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_sysrst_ctrl_irq_is_pending(
+ nullptr, kDifSysrstCtrlIrqSysrstCtrl, &is_pending));
- EXPECT_EQ(dif_sysrst_ctrl_irq_is_pending(
- &sysrst_ctrl_, kDifSysrstCtrlIrqSysrstCtrl, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_sysrst_ctrl_irq_is_pending(
+ &sysrst_ctrl_, kDifSysrstCtrlIrqSysrstCtrl, nullptr));
- EXPECT_EQ(dif_sysrst_ctrl_irq_is_pending(nullptr, kDifSysrstCtrlIrqSysrstCtrl,
- nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_sysrst_ctrl_irq_is_pending(
+ nullptr, kDifSysrstCtrlIrqSysrstCtrl, nullptr));
}
TEST_F(IrqIsPendingTest, BadIrq) {
bool is_pending;
// All interrupt CSRs are 32 bit so interrupt 32 will be invalid.
- EXPECT_EQ(
- dif_sysrst_ctrl_irq_is_pending(
- &sysrst_ctrl_, static_cast<dif_sysrst_ctrl_irq_t>(32), &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_sysrst_ctrl_irq_is_pending(
+ &sysrst_ctrl_, static_cast<dif_sysrst_ctrl_irq_t>(32), &is_pending));
}
TEST_F(IrqIsPendingTest, Success) {
@@ -122,68 +114,62 @@
irq_state = false;
EXPECT_READ32(SYSRST_CTRL_INTR_STATE_REG_OFFSET,
{{SYSRST_CTRL_INTR_STATE_SYSRST_CTRL_BIT, true}});
- EXPECT_EQ(dif_sysrst_ctrl_irq_is_pending(
- &sysrst_ctrl_, kDifSysrstCtrlIrqSysrstCtrl, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_sysrst_ctrl_irq_is_pending(
+ &sysrst_ctrl_, kDifSysrstCtrlIrqSysrstCtrl, &irq_state));
EXPECT_TRUE(irq_state);
}
class AcknowledgeAllTest : public SysrstCtrlTest {};
TEST_F(AcknowledgeAllTest, NullArgs) {
- EXPECT_EQ(dif_sysrst_ctrl_irq_acknowledge_all(nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_sysrst_ctrl_irq_acknowledge_all(nullptr));
}
TEST_F(AcknowledgeAllTest, Success) {
EXPECT_WRITE32(SYSRST_CTRL_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_sysrst_ctrl_irq_acknowledge_all(&sysrst_ctrl_), kDifOk);
+ EXPECT_DIF_OK(dif_sysrst_ctrl_irq_acknowledge_all(&sysrst_ctrl_));
}
class IrqAcknowledgeTest : public SysrstCtrlTest {};
TEST_F(IrqAcknowledgeTest, NullArgs) {
- EXPECT_EQ(
- dif_sysrst_ctrl_irq_acknowledge(nullptr, kDifSysrstCtrlIrqSysrstCtrl),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_sysrst_ctrl_irq_acknowledge(nullptr, kDifSysrstCtrlIrqSysrstCtrl));
}
TEST_F(IrqAcknowledgeTest, BadIrq) {
- EXPECT_EQ(dif_sysrst_ctrl_irq_acknowledge(
- nullptr, static_cast<dif_sysrst_ctrl_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_sysrst_ctrl_irq_acknowledge(
+ nullptr, static_cast<dif_sysrst_ctrl_irq_t>(32)));
}
TEST_F(IrqAcknowledgeTest, Success) {
// Clear the first IRQ state.
EXPECT_WRITE32(SYSRST_CTRL_INTR_STATE_REG_OFFSET,
{{SYSRST_CTRL_INTR_STATE_SYSRST_CTRL_BIT, true}});
- EXPECT_EQ(dif_sysrst_ctrl_irq_acknowledge(&sysrst_ctrl_,
- kDifSysrstCtrlIrqSysrstCtrl),
- kDifOk);
+ EXPECT_DIF_OK(dif_sysrst_ctrl_irq_acknowledge(&sysrst_ctrl_,
+ kDifSysrstCtrlIrqSysrstCtrl));
}
class IrqForceTest : public SysrstCtrlTest {};
TEST_F(IrqForceTest, NullArgs) {
- EXPECT_EQ(dif_sysrst_ctrl_irq_force(nullptr, kDifSysrstCtrlIrqSysrstCtrl),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_sysrst_ctrl_irq_force(nullptr, kDifSysrstCtrlIrqSysrstCtrl));
}
TEST_F(IrqForceTest, BadIrq) {
- EXPECT_EQ(dif_sysrst_ctrl_irq_force(nullptr,
- static_cast<dif_sysrst_ctrl_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_sysrst_ctrl_irq_force(
+ nullptr, static_cast<dif_sysrst_ctrl_irq_t>(32)));
}
TEST_F(IrqForceTest, Success) {
// Force first IRQ.
EXPECT_WRITE32(SYSRST_CTRL_INTR_TEST_REG_OFFSET,
{{SYSRST_CTRL_INTR_TEST_SYSRST_CTRL_BIT, true}});
- EXPECT_EQ(
- dif_sysrst_ctrl_irq_force(&sysrst_ctrl_, kDifSysrstCtrlIrqSysrstCtrl),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_sysrst_ctrl_irq_force(&sysrst_ctrl_, kDifSysrstCtrlIrqSysrstCtrl));
}
class IrqGetEnabledTest : public SysrstCtrlTest {};
@@ -191,26 +177,21 @@
TEST_F(IrqGetEnabledTest, NullArgs) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_sysrst_ctrl_irq_get_enabled(
- nullptr, kDifSysrstCtrlIrqSysrstCtrl, &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_sysrst_ctrl_irq_get_enabled(
+ nullptr, kDifSysrstCtrlIrqSysrstCtrl, &irq_state));
- EXPECT_EQ(dif_sysrst_ctrl_irq_get_enabled(
- &sysrst_ctrl_, kDifSysrstCtrlIrqSysrstCtrl, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_sysrst_ctrl_irq_get_enabled(
+ &sysrst_ctrl_, kDifSysrstCtrlIrqSysrstCtrl, nullptr));
- EXPECT_EQ(dif_sysrst_ctrl_irq_get_enabled(
- nullptr, kDifSysrstCtrlIrqSysrstCtrl, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_sysrst_ctrl_irq_get_enabled(
+ nullptr, kDifSysrstCtrlIrqSysrstCtrl, nullptr));
}
TEST_F(IrqGetEnabledTest, BadIrq) {
dif_toggle_t irq_state;
- EXPECT_EQ(
- dif_sysrst_ctrl_irq_get_enabled(
- &sysrst_ctrl_, static_cast<dif_sysrst_ctrl_irq_t>(32), &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_sysrst_ctrl_irq_get_enabled(
+ &sysrst_ctrl_, static_cast<dif_sysrst_ctrl_irq_t>(32), &irq_state));
}
TEST_F(IrqGetEnabledTest, Success) {
@@ -220,9 +201,8 @@
irq_state = kDifToggleDisabled;
EXPECT_READ32(SYSRST_CTRL_INTR_ENABLE_REG_OFFSET,
{{SYSRST_CTRL_INTR_ENABLE_SYSRST_CTRL_BIT, true}});
- EXPECT_EQ(dif_sysrst_ctrl_irq_get_enabled(
- &sysrst_ctrl_, kDifSysrstCtrlIrqSysrstCtrl, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_sysrst_ctrl_irq_get_enabled(
+ &sysrst_ctrl_, kDifSysrstCtrlIrqSysrstCtrl, &irq_state));
EXPECT_EQ(irq_state, kDifToggleEnabled);
}
@@ -231,18 +211,15 @@
TEST_F(IrqSetEnabledTest, NullArgs) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_sysrst_ctrl_irq_set_enabled(
- nullptr, kDifSysrstCtrlIrqSysrstCtrl, irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_sysrst_ctrl_irq_set_enabled(
+ nullptr, kDifSysrstCtrlIrqSysrstCtrl, irq_state));
}
TEST_F(IrqSetEnabledTest, BadIrq) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(
- dif_sysrst_ctrl_irq_set_enabled(
- &sysrst_ctrl_, static_cast<dif_sysrst_ctrl_irq_t>(32), irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_sysrst_ctrl_irq_set_enabled(
+ &sysrst_ctrl_, static_cast<dif_sysrst_ctrl_irq_t>(32), irq_state));
}
TEST_F(IrqSetEnabledTest, Success) {
@@ -252,9 +229,8 @@
irq_state = kDifToggleEnabled;
EXPECT_MASK32(SYSRST_CTRL_INTR_ENABLE_REG_OFFSET,
{{SYSRST_CTRL_INTR_ENABLE_SYSRST_CTRL_BIT, 0x1, true}});
- EXPECT_EQ(dif_sysrst_ctrl_irq_set_enabled(
- &sysrst_ctrl_, kDifSysrstCtrlIrqSysrstCtrl, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_sysrst_ctrl_irq_set_enabled(
+ &sysrst_ctrl_, kDifSysrstCtrlIrqSysrstCtrl, irq_state));
}
class IrqDisableAllTest : public SysrstCtrlTest {};
@@ -262,15 +238,14 @@
TEST_F(IrqDisableAllTest, NullArgs) {
dif_sysrst_ctrl_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_sysrst_ctrl_irq_disable_all(nullptr, &irq_snapshot),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_sysrst_ctrl_irq_disable_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_sysrst_ctrl_irq_disable_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_sysrst_ctrl_irq_disable_all(nullptr, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessNoSnapshot) {
EXPECT_WRITE32(SYSRST_CTRL_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_sysrst_ctrl_irq_disable_all(&sysrst_ctrl_, nullptr), kDifOk);
+ EXPECT_DIF_OK(dif_sysrst_ctrl_irq_disable_all(&sysrst_ctrl_, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessSnapshotAllDisabled) {
@@ -278,8 +253,7 @@
EXPECT_READ32(SYSRST_CTRL_INTR_ENABLE_REG_OFFSET, 0);
EXPECT_WRITE32(SYSRST_CTRL_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_sysrst_ctrl_irq_disable_all(&sysrst_ctrl_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(dif_sysrst_ctrl_irq_disable_all(&sysrst_ctrl_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -289,8 +263,7 @@
EXPECT_READ32(SYSRST_CTRL_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
EXPECT_WRITE32(SYSRST_CTRL_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_sysrst_ctrl_irq_disable_all(&sysrst_ctrl_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(dif_sysrst_ctrl_irq_disable_all(&sysrst_ctrl_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -299,13 +272,11 @@
TEST_F(IrqRestoreAllTest, NullArgs) {
dif_sysrst_ctrl_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_sysrst_ctrl_irq_restore_all(nullptr, &irq_snapshot),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_sysrst_ctrl_irq_restore_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_sysrst_ctrl_irq_restore_all(&sysrst_ctrl_, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_sysrst_ctrl_irq_restore_all(&sysrst_ctrl_, nullptr));
- EXPECT_EQ(dif_sysrst_ctrl_irq_restore_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_sysrst_ctrl_irq_restore_all(nullptr, nullptr));
}
TEST_F(IrqRestoreAllTest, SuccessAllEnabled) {
@@ -314,16 +285,14 @@
EXPECT_WRITE32(SYSRST_CTRL_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_sysrst_ctrl_irq_restore_all(&sysrst_ctrl_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(dif_sysrst_ctrl_irq_restore_all(&sysrst_ctrl_, &irq_snapshot));
}
TEST_F(IrqRestoreAllTest, SuccessAllDisabled) {
dif_sysrst_ctrl_irq_enable_snapshot_t irq_snapshot = 0;
EXPECT_WRITE32(SYSRST_CTRL_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_sysrst_ctrl_irq_restore_all(&sysrst_ctrl_, &irq_snapshot),
- kDifOk);
+ EXPECT_DIF_OK(dif_sysrst_ctrl_irq_restore_all(&sysrst_ctrl_, &irq_snapshot));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_uart_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_uart_autogen_unittest.cc
index 5e8be5a..05dcda8 100644
--- a/sw/device/lib/dif/autogen/dif_uart_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_uart_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "uart_regs.h" // Generated.
@@ -28,29 +29,29 @@
class InitTest : public UartTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_uart_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_uart_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_uart_init(dev().region(), &uart_), kDifOk);
+ EXPECT_DIF_OK(dif_uart_init(dev().region(), &uart_));
}
class AlertForceTest : public UartTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_uart_alert_force(nullptr, kDifUartAlertFatalFault), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_uart_alert_force(nullptr, kDifUartAlertFatalFault));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(dif_uart_alert_force(nullptr, static_cast<dif_uart_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_uart_alert_force(nullptr, static_cast<dif_uart_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(UART_ALERT_TEST_REG_OFFSET,
{{UART_ALERT_TEST_FATAL_FAULT_BIT, true}});
- EXPECT_EQ(dif_uart_alert_force(&uart_, kDifUartAlertFatalFault), kDifOk);
+ EXPECT_DIF_OK(dif_uart_alert_force(&uart_, kDifUartAlertFatalFault));
}
class IrqGetStateTest : public UartTest {};
@@ -58,11 +59,11 @@
TEST_F(IrqGetStateTest, NullArgs) {
dif_uart_irq_state_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_uart_irq_get_state(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_uart_irq_get_state(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_uart_irq_get_state(&uart_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_uart_irq_get_state(&uart_, nullptr));
- EXPECT_EQ(dif_uart_irq_get_state(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_uart_irq_get_state(nullptr, nullptr));
}
TEST_F(IrqGetStateTest, SuccessAllRaised) {
@@ -70,7 +71,7 @@
EXPECT_READ32(UART_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_uart_irq_get_state(&uart_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_uart_irq_get_state(&uart_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -78,7 +79,7 @@
dif_uart_irq_state_snapshot_t irq_snapshot = 0;
EXPECT_READ32(UART_INTR_STATE_REG_OFFSET, 0);
- EXPECT_EQ(dif_uart_irq_get_state(&uart_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_uart_irq_get_state(&uart_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -87,23 +88,21 @@
TEST_F(IrqIsPendingTest, NullArgs) {
bool is_pending;
- EXPECT_EQ(
- dif_uart_irq_is_pending(nullptr, kDifUartIrqTxWatermark, &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_uart_irq_is_pending(nullptr, kDifUartIrqTxWatermark, &is_pending));
- EXPECT_EQ(dif_uart_irq_is_pending(&uart_, kDifUartIrqTxWatermark, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_uart_irq_is_pending(&uart_, kDifUartIrqTxWatermark, nullptr));
- EXPECT_EQ(dif_uart_irq_is_pending(nullptr, kDifUartIrqTxWatermark, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_uart_irq_is_pending(nullptr, kDifUartIrqTxWatermark, nullptr));
}
TEST_F(IrqIsPendingTest, BadIrq) {
bool is_pending;
// All interrupt CSRs are 32 bit so interrupt 32 will be invalid.
- EXPECT_EQ(dif_uart_irq_is_pending(&uart_, static_cast<dif_uart_irq_t>(32),
- &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_uart_irq_is_pending(
+ &uart_, static_cast<dif_uart_irq_t>(32), &is_pending));
}
TEST_F(IrqIsPendingTest, Success) {
@@ -113,77 +112,76 @@
irq_state = false;
EXPECT_READ32(UART_INTR_STATE_REG_OFFSET,
{{UART_INTR_STATE_TX_WATERMARK_BIT, true}});
- EXPECT_EQ(dif_uart_irq_is_pending(&uart_, kDifUartIrqTxWatermark, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_uart_irq_is_pending(&uart_, kDifUartIrqTxWatermark, &irq_state));
EXPECT_TRUE(irq_state);
// Get the last IRQ state.
irq_state = true;
EXPECT_READ32(UART_INTR_STATE_REG_OFFSET,
{{UART_INTR_STATE_RX_PARITY_ERR_BIT, false}});
- EXPECT_EQ(dif_uart_irq_is_pending(&uart_, kDifUartIrqRxParityErr, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_uart_irq_is_pending(&uart_, kDifUartIrqRxParityErr, &irq_state));
EXPECT_FALSE(irq_state);
}
class AcknowledgeAllTest : public UartTest {};
TEST_F(AcknowledgeAllTest, NullArgs) {
- EXPECT_EQ(dif_uart_irq_acknowledge_all(nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_uart_irq_acknowledge_all(nullptr));
}
TEST_F(AcknowledgeAllTest, Success) {
EXPECT_WRITE32(UART_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_uart_irq_acknowledge_all(&uart_), kDifOk);
+ EXPECT_DIF_OK(dif_uart_irq_acknowledge_all(&uart_));
}
class IrqAcknowledgeTest : public UartTest {};
TEST_F(IrqAcknowledgeTest, NullArgs) {
- EXPECT_EQ(dif_uart_irq_acknowledge(nullptr, kDifUartIrqTxWatermark),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_uart_irq_acknowledge(nullptr, kDifUartIrqTxWatermark));
}
TEST_F(IrqAcknowledgeTest, BadIrq) {
- EXPECT_EQ(dif_uart_irq_acknowledge(nullptr, static_cast<dif_uart_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_uart_irq_acknowledge(nullptr, static_cast<dif_uart_irq_t>(32)));
}
TEST_F(IrqAcknowledgeTest, Success) {
// Clear the first IRQ state.
EXPECT_WRITE32(UART_INTR_STATE_REG_OFFSET,
{{UART_INTR_STATE_TX_WATERMARK_BIT, true}});
- EXPECT_EQ(dif_uart_irq_acknowledge(&uart_, kDifUartIrqTxWatermark), kDifOk);
+ EXPECT_DIF_OK(dif_uart_irq_acknowledge(&uart_, kDifUartIrqTxWatermark));
// Clear the last IRQ state.
EXPECT_WRITE32(UART_INTR_STATE_REG_OFFSET,
{{UART_INTR_STATE_RX_PARITY_ERR_BIT, true}});
- EXPECT_EQ(dif_uart_irq_acknowledge(&uart_, kDifUartIrqRxParityErr), kDifOk);
+ EXPECT_DIF_OK(dif_uart_irq_acknowledge(&uart_, kDifUartIrqRxParityErr));
}
class IrqForceTest : public UartTest {};
TEST_F(IrqForceTest, NullArgs) {
- EXPECT_EQ(dif_uart_irq_force(nullptr, kDifUartIrqTxWatermark), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_uart_irq_force(nullptr, kDifUartIrqTxWatermark));
}
TEST_F(IrqForceTest, BadIrq) {
- EXPECT_EQ(dif_uart_irq_force(nullptr, static_cast<dif_uart_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_uart_irq_force(nullptr, static_cast<dif_uart_irq_t>(32)));
}
TEST_F(IrqForceTest, Success) {
// Force first IRQ.
EXPECT_WRITE32(UART_INTR_TEST_REG_OFFSET,
{{UART_INTR_TEST_TX_WATERMARK_BIT, true}});
- EXPECT_EQ(dif_uart_irq_force(&uart_, kDifUartIrqTxWatermark), kDifOk);
+ EXPECT_DIF_OK(dif_uart_irq_force(&uart_, kDifUartIrqTxWatermark));
// Force last IRQ.
EXPECT_WRITE32(UART_INTR_TEST_REG_OFFSET,
{{UART_INTR_TEST_RX_PARITY_ERR_BIT, true}});
- EXPECT_EQ(dif_uart_irq_force(&uart_, kDifUartIrqRxParityErr), kDifOk);
+ EXPECT_DIF_OK(dif_uart_irq_force(&uart_, kDifUartIrqRxParityErr));
}
class IrqGetEnabledTest : public UartTest {};
@@ -191,23 +189,21 @@
TEST_F(IrqGetEnabledTest, NullArgs) {
dif_toggle_t irq_state;
- EXPECT_EQ(
- dif_uart_irq_get_enabled(nullptr, kDifUartIrqTxWatermark, &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_uart_irq_get_enabled(nullptr, kDifUartIrqTxWatermark, &irq_state));
- EXPECT_EQ(dif_uart_irq_get_enabled(&uart_, kDifUartIrqTxWatermark, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_uart_irq_get_enabled(&uart_, kDifUartIrqTxWatermark, nullptr));
- EXPECT_EQ(dif_uart_irq_get_enabled(nullptr, kDifUartIrqTxWatermark, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_uart_irq_get_enabled(nullptr, kDifUartIrqTxWatermark, nullptr));
}
TEST_F(IrqGetEnabledTest, BadIrq) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_uart_irq_get_enabled(&uart_, static_cast<dif_uart_irq_t>(32),
- &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_uart_irq_get_enabled(
+ &uart_, static_cast<dif_uart_irq_t>(32), &irq_state));
}
TEST_F(IrqGetEnabledTest, Success) {
@@ -217,18 +213,16 @@
irq_state = kDifToggleDisabled;
EXPECT_READ32(UART_INTR_ENABLE_REG_OFFSET,
{{UART_INTR_ENABLE_TX_WATERMARK_BIT, true}});
- EXPECT_EQ(
- dif_uart_irq_get_enabled(&uart_, kDifUartIrqTxWatermark, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_uart_irq_get_enabled(&uart_, kDifUartIrqTxWatermark, &irq_state));
EXPECT_EQ(irq_state, kDifToggleEnabled);
// Last IRQ is disabled.
irq_state = kDifToggleEnabled;
EXPECT_READ32(UART_INTR_ENABLE_REG_OFFSET,
{{UART_INTR_ENABLE_RX_PARITY_ERR_BIT, false}});
- EXPECT_EQ(
- dif_uart_irq_get_enabled(&uart_, kDifUartIrqRxParityErr, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_uart_irq_get_enabled(&uart_, kDifUartIrqRxParityErr, &irq_state));
EXPECT_EQ(irq_state, kDifToggleDisabled);
}
@@ -237,17 +231,15 @@
TEST_F(IrqSetEnabledTest, NullArgs) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(
- dif_uart_irq_set_enabled(nullptr, kDifUartIrqTxWatermark, irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_uart_irq_set_enabled(nullptr, kDifUartIrqTxWatermark, irq_state));
}
TEST_F(IrqSetEnabledTest, BadIrq) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_uart_irq_set_enabled(&uart_, static_cast<dif_uart_irq_t>(32),
- irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_uart_irq_set_enabled(
+ &uart_, static_cast<dif_uart_irq_t>(32), irq_state));
}
TEST_F(IrqSetEnabledTest, Success) {
@@ -257,15 +249,15 @@
irq_state = kDifToggleEnabled;
EXPECT_MASK32(UART_INTR_ENABLE_REG_OFFSET,
{{UART_INTR_ENABLE_TX_WATERMARK_BIT, 0x1, true}});
- EXPECT_EQ(dif_uart_irq_set_enabled(&uart_, kDifUartIrqTxWatermark, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_uart_irq_set_enabled(&uart_, kDifUartIrqTxWatermark, irq_state));
// Disable last IRQ.
irq_state = kDifToggleDisabled;
EXPECT_MASK32(UART_INTR_ENABLE_REG_OFFSET,
{{UART_INTR_ENABLE_RX_PARITY_ERR_BIT, 0x1, false}});
- EXPECT_EQ(dif_uart_irq_set_enabled(&uart_, kDifUartIrqRxParityErr, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_uart_irq_set_enabled(&uart_, kDifUartIrqRxParityErr, irq_state));
}
class IrqDisableAllTest : public UartTest {};
@@ -273,14 +265,14 @@
TEST_F(IrqDisableAllTest, NullArgs) {
dif_uart_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_uart_irq_disable_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_uart_irq_disable_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_uart_irq_disable_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_uart_irq_disable_all(nullptr, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessNoSnapshot) {
EXPECT_WRITE32(UART_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_uart_irq_disable_all(&uart_, nullptr), kDifOk);
+ EXPECT_DIF_OK(dif_uart_irq_disable_all(&uart_, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessSnapshotAllDisabled) {
@@ -288,7 +280,7 @@
EXPECT_READ32(UART_INTR_ENABLE_REG_OFFSET, 0);
EXPECT_WRITE32(UART_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_uart_irq_disable_all(&uart_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_uart_irq_disable_all(&uart_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -298,7 +290,7 @@
EXPECT_READ32(UART_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
EXPECT_WRITE32(UART_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_uart_irq_disable_all(&uart_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_uart_irq_disable_all(&uart_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -307,11 +299,11 @@
TEST_F(IrqRestoreAllTest, NullArgs) {
dif_uart_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_uart_irq_restore_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_uart_irq_restore_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_uart_irq_restore_all(&uart_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_uart_irq_restore_all(&uart_, nullptr));
- EXPECT_EQ(dif_uart_irq_restore_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_uart_irq_restore_all(nullptr, nullptr));
}
TEST_F(IrqRestoreAllTest, SuccessAllEnabled) {
@@ -320,14 +312,14 @@
EXPECT_WRITE32(UART_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_uart_irq_restore_all(&uart_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_uart_irq_restore_all(&uart_, &irq_snapshot));
}
TEST_F(IrqRestoreAllTest, SuccessAllDisabled) {
dif_uart_irq_enable_snapshot_t irq_snapshot = 0;
EXPECT_WRITE32(UART_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_uart_irq_restore_all(&uart_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_uart_irq_restore_all(&uart_, &irq_snapshot));
}
} // namespace
diff --git a/sw/device/lib/dif/autogen/dif_usbdev_autogen_unittest.cc b/sw/device/lib/dif/autogen/dif_usbdev_autogen_unittest.cc
index b7feb73..779bca5 100644
--- a/sw/device/lib/dif/autogen/dif_usbdev_autogen_unittest.cc
+++ b/sw/device/lib/dif/autogen/dif_usbdev_autogen_unittest.cc
@@ -10,6 +10,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "usbdev_regs.h" // Generated.
@@ -28,32 +29,29 @@
class InitTest : public UsbdevTest {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_usbdev_init(dev().region(), nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_usbdev_init(dev().region(), nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_usbdev_init(dev().region(), &usbdev_), kDifOk);
+ EXPECT_DIF_OK(dif_usbdev_init(dev().region(), &usbdev_));
}
class AlertForceTest : public UsbdevTest {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_usbdev_alert_force(nullptr, kDifUsbdevAlertFatalFault),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_usbdev_alert_force(nullptr, kDifUsbdevAlertFatalFault));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(
- dif_usbdev_alert_force(nullptr, static_cast<dif_usbdev_alert_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_usbdev_alert_force(nullptr, static_cast<dif_usbdev_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(USBDEV_ALERT_TEST_REG_OFFSET,
{{USBDEV_ALERT_TEST_FATAL_FAULT_BIT, true}});
- EXPECT_EQ(dif_usbdev_alert_force(&usbdev_, kDifUsbdevAlertFatalFault),
- kDifOk);
+ EXPECT_DIF_OK(dif_usbdev_alert_force(&usbdev_, kDifUsbdevAlertFatalFault));
}
class IrqGetStateTest : public UsbdevTest {};
@@ -61,11 +59,11 @@
TEST_F(IrqGetStateTest, NullArgs) {
dif_usbdev_irq_state_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_usbdev_irq_get_state(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_usbdev_irq_get_state(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_usbdev_irq_get_state(&usbdev_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_usbdev_irq_get_state(&usbdev_, nullptr));
- EXPECT_EQ(dif_usbdev_irq_get_state(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_usbdev_irq_get_state(nullptr, nullptr));
}
TEST_F(IrqGetStateTest, SuccessAllRaised) {
@@ -73,7 +71,7 @@
EXPECT_READ32(USBDEV_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_usbdev_irq_get_state(&usbdev_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_usbdev_irq_get_state(&usbdev_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -81,7 +79,7 @@
dif_usbdev_irq_state_snapshot_t irq_snapshot = 0;
EXPECT_READ32(USBDEV_INTR_STATE_REG_OFFSET, 0);
- EXPECT_EQ(dif_usbdev_irq_get_state(&usbdev_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_usbdev_irq_get_state(&usbdev_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -90,25 +88,21 @@
TEST_F(IrqIsPendingTest, NullArgs) {
bool is_pending;
- EXPECT_EQ(
- dif_usbdev_irq_is_pending(nullptr, kDifUsbdevIrqPktReceived, &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_usbdev_irq_is_pending(nullptr, kDifUsbdevIrqPktReceived,
+ &is_pending));
- EXPECT_EQ(
- dif_usbdev_irq_is_pending(&usbdev_, kDifUsbdevIrqPktReceived, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_usbdev_irq_is_pending(&usbdev_, kDifUsbdevIrqPktReceived, nullptr));
- EXPECT_EQ(
- dif_usbdev_irq_is_pending(nullptr, kDifUsbdevIrqPktReceived, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_usbdev_irq_is_pending(nullptr, kDifUsbdevIrqPktReceived, nullptr));
}
TEST_F(IrqIsPendingTest, BadIrq) {
bool is_pending;
// All interrupt CSRs are 32 bit so interrupt 32 will be invalid.
- EXPECT_EQ(dif_usbdev_irq_is_pending(
- &usbdev_, static_cast<dif_usbdev_irq_t>(32), &is_pending),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_usbdev_irq_is_pending(
+ &usbdev_, static_cast<dif_usbdev_irq_t>(32), &is_pending));
}
TEST_F(IrqIsPendingTest, Success) {
@@ -118,83 +112,77 @@
irq_state = false;
EXPECT_READ32(USBDEV_INTR_STATE_REG_OFFSET,
{{USBDEV_INTR_STATE_PKT_RECEIVED_BIT, true}});
- EXPECT_EQ(
- dif_usbdev_irq_is_pending(&usbdev_, kDifUsbdevIrqPktReceived, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_usbdev_irq_is_pending(&usbdev_, kDifUsbdevIrqPktReceived,
+ &irq_state));
EXPECT_TRUE(irq_state);
// Get the last IRQ state.
irq_state = true;
EXPECT_READ32(USBDEV_INTR_STATE_REG_OFFSET,
{{USBDEV_INTR_STATE_LINK_OUT_ERR_BIT, false}});
- EXPECT_EQ(
- dif_usbdev_irq_is_pending(&usbdev_, kDifUsbdevIrqLinkOutErr, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_usbdev_irq_is_pending(&usbdev_, kDifUsbdevIrqLinkOutErr, &irq_state));
EXPECT_FALSE(irq_state);
}
class AcknowledgeAllTest : public UsbdevTest {};
TEST_F(AcknowledgeAllTest, NullArgs) {
- EXPECT_EQ(dif_usbdev_irq_acknowledge_all(nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_usbdev_irq_acknowledge_all(nullptr));
}
TEST_F(AcknowledgeAllTest, Success) {
EXPECT_WRITE32(USBDEV_INTR_STATE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_usbdev_irq_acknowledge_all(&usbdev_), kDifOk);
+ EXPECT_DIF_OK(dif_usbdev_irq_acknowledge_all(&usbdev_));
}
class IrqAcknowledgeTest : public UsbdevTest {};
TEST_F(IrqAcknowledgeTest, NullArgs) {
- EXPECT_EQ(dif_usbdev_irq_acknowledge(nullptr, kDifUsbdevIrqPktReceived),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_usbdev_irq_acknowledge(nullptr, kDifUsbdevIrqPktReceived));
}
TEST_F(IrqAcknowledgeTest, BadIrq) {
- EXPECT_EQ(
- dif_usbdev_irq_acknowledge(nullptr, static_cast<dif_usbdev_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_usbdev_irq_acknowledge(nullptr, static_cast<dif_usbdev_irq_t>(32)));
}
TEST_F(IrqAcknowledgeTest, Success) {
// Clear the first IRQ state.
EXPECT_WRITE32(USBDEV_INTR_STATE_REG_OFFSET,
{{USBDEV_INTR_STATE_PKT_RECEIVED_BIT, true}});
- EXPECT_EQ(dif_usbdev_irq_acknowledge(&usbdev_, kDifUsbdevIrqPktReceived),
- kDifOk);
+ EXPECT_DIF_OK(dif_usbdev_irq_acknowledge(&usbdev_, kDifUsbdevIrqPktReceived));
// Clear the last IRQ state.
EXPECT_WRITE32(USBDEV_INTR_STATE_REG_OFFSET,
{{USBDEV_INTR_STATE_LINK_OUT_ERR_BIT, true}});
- EXPECT_EQ(dif_usbdev_irq_acknowledge(&usbdev_, kDifUsbdevIrqLinkOutErr),
- kDifOk);
+ EXPECT_DIF_OK(dif_usbdev_irq_acknowledge(&usbdev_, kDifUsbdevIrqLinkOutErr));
}
class IrqForceTest : public UsbdevTest {};
TEST_F(IrqForceTest, NullArgs) {
- EXPECT_EQ(dif_usbdev_irq_force(nullptr, kDifUsbdevIrqPktReceived),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_usbdev_irq_force(nullptr, kDifUsbdevIrqPktReceived));
}
TEST_F(IrqForceTest, BadIrq) {
- EXPECT_EQ(dif_usbdev_irq_force(nullptr, static_cast<dif_usbdev_irq_t>(32)),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_usbdev_irq_force(nullptr, static_cast<dif_usbdev_irq_t>(32)));
}
TEST_F(IrqForceTest, Success) {
// Force first IRQ.
EXPECT_WRITE32(USBDEV_INTR_TEST_REG_OFFSET,
{{USBDEV_INTR_TEST_PKT_RECEIVED_BIT, true}});
- EXPECT_EQ(dif_usbdev_irq_force(&usbdev_, kDifUsbdevIrqPktReceived), kDifOk);
+ EXPECT_DIF_OK(dif_usbdev_irq_force(&usbdev_, kDifUsbdevIrqPktReceived));
// Force last IRQ.
EXPECT_WRITE32(USBDEV_INTR_TEST_REG_OFFSET,
{{USBDEV_INTR_TEST_LINK_OUT_ERR_BIT, true}});
- EXPECT_EQ(dif_usbdev_irq_force(&usbdev_, kDifUsbdevIrqLinkOutErr), kDifOk);
+ EXPECT_DIF_OK(dif_usbdev_irq_force(&usbdev_, kDifUsbdevIrqLinkOutErr));
}
class IrqGetEnabledTest : public UsbdevTest {};
@@ -202,25 +190,21 @@
TEST_F(IrqGetEnabledTest, NullArgs) {
dif_toggle_t irq_state;
- EXPECT_EQ(
- dif_usbdev_irq_get_enabled(nullptr, kDifUsbdevIrqPktReceived, &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_usbdev_irq_get_enabled(
+ nullptr, kDifUsbdevIrqPktReceived, &irq_state));
- EXPECT_EQ(
- dif_usbdev_irq_get_enabled(&usbdev_, kDifUsbdevIrqPktReceived, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_usbdev_irq_get_enabled(&usbdev_, kDifUsbdevIrqPktReceived, nullptr));
- EXPECT_EQ(
- dif_usbdev_irq_get_enabled(nullptr, kDifUsbdevIrqPktReceived, nullptr),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_usbdev_irq_get_enabled(nullptr, kDifUsbdevIrqPktReceived, nullptr));
}
TEST_F(IrqGetEnabledTest, BadIrq) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_usbdev_irq_get_enabled(
- &usbdev_, static_cast<dif_usbdev_irq_t>(32), &irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_usbdev_irq_get_enabled(
+ &usbdev_, static_cast<dif_usbdev_irq_t>(32), &irq_state));
}
TEST_F(IrqGetEnabledTest, Success) {
@@ -230,18 +214,16 @@
irq_state = kDifToggleDisabled;
EXPECT_READ32(USBDEV_INTR_ENABLE_REG_OFFSET,
{{USBDEV_INTR_ENABLE_PKT_RECEIVED_BIT, true}});
- EXPECT_EQ(dif_usbdev_irq_get_enabled(&usbdev_, kDifUsbdevIrqPktReceived,
- &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_usbdev_irq_get_enabled(&usbdev_, kDifUsbdevIrqPktReceived,
+ &irq_state));
EXPECT_EQ(irq_state, kDifToggleEnabled);
// Last IRQ is disabled.
irq_state = kDifToggleEnabled;
EXPECT_READ32(USBDEV_INTR_ENABLE_REG_OFFSET,
{{USBDEV_INTR_ENABLE_LINK_OUT_ERR_BIT, false}});
- EXPECT_EQ(
- dif_usbdev_irq_get_enabled(&usbdev_, kDifUsbdevIrqLinkOutErr, &irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_usbdev_irq_get_enabled(&usbdev_, kDifUsbdevIrqLinkOutErr,
+ &irq_state));
EXPECT_EQ(irq_state, kDifToggleDisabled);
}
@@ -250,17 +232,15 @@
TEST_F(IrqSetEnabledTest, NullArgs) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(
- dif_usbdev_irq_set_enabled(nullptr, kDifUsbdevIrqPktReceived, irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(
+ dif_usbdev_irq_set_enabled(nullptr, kDifUsbdevIrqPktReceived, irq_state));
}
TEST_F(IrqSetEnabledTest, BadIrq) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_usbdev_irq_set_enabled(
- &usbdev_, static_cast<dif_usbdev_irq_t>(32), irq_state),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_usbdev_irq_set_enabled(
+ &usbdev_, static_cast<dif_usbdev_irq_t>(32), irq_state));
}
TEST_F(IrqSetEnabledTest, Success) {
@@ -270,17 +250,15 @@
irq_state = kDifToggleEnabled;
EXPECT_MASK32(USBDEV_INTR_ENABLE_REG_OFFSET,
{{USBDEV_INTR_ENABLE_PKT_RECEIVED_BIT, 0x1, true}});
- EXPECT_EQ(
- dif_usbdev_irq_set_enabled(&usbdev_, kDifUsbdevIrqPktReceived, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(dif_usbdev_irq_set_enabled(&usbdev_, kDifUsbdevIrqPktReceived,
+ irq_state));
// Disable last IRQ.
irq_state = kDifToggleDisabled;
EXPECT_MASK32(USBDEV_INTR_ENABLE_REG_OFFSET,
{{USBDEV_INTR_ENABLE_LINK_OUT_ERR_BIT, 0x1, false}});
- EXPECT_EQ(
- dif_usbdev_irq_set_enabled(&usbdev_, kDifUsbdevIrqLinkOutErr, irq_state),
- kDifOk);
+ EXPECT_DIF_OK(
+ dif_usbdev_irq_set_enabled(&usbdev_, kDifUsbdevIrqLinkOutErr, irq_state));
}
class IrqDisableAllTest : public UsbdevTest {};
@@ -288,14 +266,14 @@
TEST_F(IrqDisableAllTest, NullArgs) {
dif_usbdev_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_usbdev_irq_disable_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_usbdev_irq_disable_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_usbdev_irq_disable_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_usbdev_irq_disable_all(nullptr, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessNoSnapshot) {
EXPECT_WRITE32(USBDEV_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_usbdev_irq_disable_all(&usbdev_, nullptr), kDifOk);
+ EXPECT_DIF_OK(dif_usbdev_irq_disable_all(&usbdev_, nullptr));
}
TEST_F(IrqDisableAllTest, SuccessSnapshotAllDisabled) {
@@ -303,7 +281,7 @@
EXPECT_READ32(USBDEV_INTR_ENABLE_REG_OFFSET, 0);
EXPECT_WRITE32(USBDEV_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_usbdev_irq_disable_all(&usbdev_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_usbdev_irq_disable_all(&usbdev_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -313,7 +291,7 @@
EXPECT_READ32(USBDEV_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
EXPECT_WRITE32(USBDEV_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_usbdev_irq_disable_all(&usbdev_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_usbdev_irq_disable_all(&usbdev_, &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -322,11 +300,11 @@
TEST_F(IrqRestoreAllTest, NullArgs) {
dif_usbdev_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_usbdev_irq_restore_all(nullptr, &irq_snapshot), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_usbdev_irq_restore_all(nullptr, &irq_snapshot));
- EXPECT_EQ(dif_usbdev_irq_restore_all(&usbdev_, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_usbdev_irq_restore_all(&usbdev_, nullptr));
- EXPECT_EQ(dif_usbdev_irq_restore_all(nullptr, nullptr), kDifBadArg);
+ EXPECT_DIF_BADARG(dif_usbdev_irq_restore_all(nullptr, nullptr));
}
TEST_F(IrqRestoreAllTest, SuccessAllEnabled) {
@@ -335,14 +313,14 @@
EXPECT_WRITE32(USBDEV_INTR_ENABLE_REG_OFFSET,
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_usbdev_irq_restore_all(&usbdev_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_usbdev_irq_restore_all(&usbdev_, &irq_snapshot));
}
TEST_F(IrqRestoreAllTest, SuccessAllDisabled) {
dif_usbdev_irq_enable_snapshot_t irq_snapshot = 0;
EXPECT_WRITE32(USBDEV_INTR_ENABLE_REG_OFFSET, 0);
- EXPECT_EQ(dif_usbdev_irq_restore_all(&usbdev_, &irq_snapshot), kDifOk);
+ EXPECT_DIF_OK(dif_usbdev_irq_restore_all(&usbdev_, &irq_snapshot));
}
} // namespace
diff --git a/util/make_new_dif/templates/dif_autogen_unittest.cc.tpl b/util/make_new_dif/templates/dif_autogen_unittest.cc.tpl
index 333db57..3c1aeb7 100644
--- a/util/make_new_dif/templates/dif_autogen_unittest.cc.tpl
+++ b/util/make_new_dif/templates/dif_autogen_unittest.cc.tpl
@@ -21,6 +21,7 @@
#include "gtest/gtest.h"
#include "sw/device/lib/base/mmio.h"
#include "sw/device/lib/base/testing/mock_mmio.h"
+#include "sw/device/lib/dif/dif_test_base.h"
#include "${ip.name_snake}_regs.h" // Generated.
@@ -39,53 +40,47 @@
class InitTest : public ${ip.name_camel}Test {};
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_${ip.name_snake}_init(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_init(
dev().region(),
- nullptr),
- kDifBadArg);
+ nullptr));
}
TEST_F(InitTest, Success) {
- EXPECT_EQ(dif_${ip.name_snake}_init(
+ EXPECT_DIF_OK(dif_${ip.name_snake}_init(
dev().region(),
- &${ip.name_snake}_),
- kDifOk);
+ &${ip.name_snake}_));
}
% if ip.alerts:
class AlertForceTest : public ${ip.name_camel}Test {};
TEST_F(AlertForceTest, NullArgs) {
- EXPECT_EQ(dif_${ip.name_snake}_alert_force(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_alert_force(
nullptr,
- kDif${ip.name_camel}Alert${ip.alerts[0].name_camel}),
- kDifBadArg);
+ kDif${ip.name_camel}Alert${ip.alerts[0].name_camel}));
}
TEST_F(AlertForceTest, BadAlert) {
- EXPECT_EQ(dif_${ip.name_snake}_alert_force(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_alert_force(
nullptr,
- static_cast<dif_${ip.name_snake}_alert_t>(32)),
- kDifBadArg);
+ static_cast<dif_${ip.name_snake}_alert_t>(32)));
}
TEST_F(AlertForceTest, Success) {
// Force first alert.
EXPECT_WRITE32(${ip.name_upper}_ALERT_TEST_REG_OFFSET,
{{${ip.name_upper}_ALERT_TEST_${ip.alerts[0].name_upper}_BIT, true}});
- EXPECT_EQ(dif_${ip.name_snake}_alert_force(
+ EXPECT_DIF_OK(dif_${ip.name_snake}_alert_force(
&${ip.name_snake}_,
- kDif${ip.name_camel}Alert${ip.alerts[0].name_camel}),
- kDifOk);
+ kDif${ip.name_camel}Alert${ip.alerts[0].name_camel}));
% if len(ip.alerts) > 1:
// Force last alert.
EXPECT_WRITE32(${ip.name_upper}_ALERT_TEST_REG_OFFSET,
{{${ip.name_upper}_ALERT_TEST_${ip.alerts[-1].name_upper}_BIT, true}});
- EXPECT_EQ(dif_${ip.name_snake}_alert_force(
+ EXPECT_DIF_OK(dif_${ip.name_snake}_alert_force(
&${ip.name_snake}_,
- kDif${ip.name_camel}Alert${ip.alerts[-1].name_camel}),
- kDifOk);
+ kDif${ip.name_camel}Alert${ip.alerts[-1].name_camel}));
% endif
}
@@ -97,29 +92,26 @@
TEST_F(IrqGetStateTest, NullArgs) {
dif_${ip.name_snake}_irq_state_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_${ip.name_snake}_irq_get_state(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_irq_get_state(
nullptr,
% if ip.name_snake == "rv_timer":
0,
% endif
- &irq_snapshot),
- kDifBadArg);
+ &irq_snapshot));
- EXPECT_EQ(dif_${ip.name_snake}_irq_get_state(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_irq_get_state(
&${ip.name_snake}_,
% if ip.name_snake == "rv_timer":
0,
% endif
- nullptr),
- kDifBadArg);
+ nullptr));
- EXPECT_EQ(dif_${ip.name_snake}_irq_get_state(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_irq_get_state(
nullptr,
% if ip.name_snake == "rv_timer":
0,
% endif
- nullptr),
- kDifBadArg);
+ nullptr));
}
TEST_F(IrqGetStateTest, SuccessAllRaised) {
@@ -131,13 +123,12 @@
EXPECT_READ32(${ip.name_upper}_INTR_STATE_REG_OFFSET,
% endif
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_${ip.name_snake}_irq_get_state(
+ EXPECT_DIF_OK(dif_${ip.name_snake}_irq_get_state(
&${ip.name_snake}_,
% if ip.name_snake == "rv_timer":
0,
% endif
- &irq_snapshot),
- kDifOk);
+ &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -149,13 +140,12 @@
% else:
EXPECT_READ32(${ip.name_upper}_INTR_STATE_REG_OFFSET, 0);
% endif
- EXPECT_EQ(dif_${ip.name_snake}_irq_get_state(
+ EXPECT_DIF_OK(dif_${ip.name_snake}_irq_get_state(
&${ip.name_snake}_,
% if ip.name_snake == "rv_timer":
0,
% endif
- &irq_snapshot),
- kDifOk);
+ &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -164,45 +154,41 @@
TEST_F(IrqIsPendingTest, NullArgs) {
bool is_pending;
- EXPECT_EQ(dif_${ip.name_snake}_irq_is_pending(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_irq_is_pending(
nullptr,
% if ip.irqs[0].width > 1:
kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}0,
% else:
kDif${ip.name_camel}Irq${ip.irqs[0].name_camel},
% endif
- &is_pending),
- kDifBadArg);
+ &is_pending));
- EXPECT_EQ(dif_${ip.name_snake}_irq_is_pending(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_irq_is_pending(
&${ip.name_snake}_,
% if ip.irqs[0].width > 1:
kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}0,
% else:
kDif${ip.name_camel}Irq${ip.irqs[0].name_camel},
% endif
- nullptr),
- kDifBadArg);
+ nullptr));
- EXPECT_EQ(dif_${ip.name_snake}_irq_is_pending(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_irq_is_pending(
nullptr,
% if ip.irqs[0].width > 1:
kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}0,
% else:
kDif${ip.name_camel}Irq${ip.irqs[0].name_camel},
% endif
- nullptr),
- kDifBadArg);
+ nullptr));
}
TEST_F(IrqIsPendingTest, BadIrq) {
bool is_pending;
// All interrupt CSRs are 32 bit so interrupt 32 will be invalid.
- EXPECT_EQ(dif_${ip.name_snake}_irq_is_pending(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_irq_is_pending(
&${ip.name_snake}_,
static_cast<dif_${ip.name_snake}_irq_t>(32),
- &is_pending),
- kDifBadArg);
+ &is_pending));
}
TEST_F(IrqIsPendingTest, Success) {
@@ -221,15 +207,14 @@
{{${ip.name_upper}_INTR_STATE_${ip.irqs[0].name_upper}_BIT, true}});
% endif
% endif
- EXPECT_EQ(dif_${ip.name_snake}_irq_is_pending(
+ EXPECT_DIF_OK(dif_${ip.name_snake}_irq_is_pending(
&${ip.name_snake}_,
% if ip.irqs[0].width > 1:
kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}0,
% else:
kDif${ip.name_camel}Irq${ip.irqs[0].name_camel},
% endif
- &irq_state),
- kDifOk);
+ &irq_state));
EXPECT_TRUE(irq_state);
% if len(ip.irqs) > 1 or ip.irqs[0].width > 1:
@@ -247,15 +232,14 @@
{{${ip.name_upper}_INTR_STATE_${ip.irqs[-1].name_upper}_BIT, false}});
% endif
% endif
- EXPECT_EQ(dif_${ip.name_snake}_irq_is_pending(
+ EXPECT_DIF_OK(dif_${ip.name_snake}_irq_is_pending(
&${ip.name_snake}_,
% if ip.irqs[0].width > 1:
kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}${ip.irqs[0].width - 1},
% else:
kDif${ip.name_camel}Irq${ip.irqs[-1].name_camel},
% endif
- &irq_state),
- kDifOk);
+ &irq_state));
EXPECT_FALSE(irq_state);
% endif
}
@@ -263,20 +247,18 @@
class AcknowledgeAllTest : public ${ip.name_camel}Test {};
TEST_F(AcknowledgeAllTest, NullArgs) {
- EXPECT_EQ(dif_${ip.name_snake}_irq_acknowledge_all(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_irq_acknowledge_all(
nullptr
% if ip.name_snake == "rv_timer":
, 0
% endif
- ),
- kDifBadArg);
+ ));
}
% if ip.name_snake == "rv_timer":
TEST_F(AcknowledgeAllTest, BadHartId) {
- EXPECT_EQ(dif_${ip.name_snake}_irq_acknowledge_all(
- nullptr, ${ip.parameters["N_HARTS"].default}),
- kDifBadArg);
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_irq_acknowledge_all(
+ nullptr, ${ip.parameters["N_HARTS"].default}));
}
% endif
@@ -288,33 +270,30 @@
% endif
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_${ip.name_snake}_irq_acknowledge_all(
+ EXPECT_DIF_OK(dif_${ip.name_snake}_irq_acknowledge_all(
&${ip.name_snake}_
% if ip.name_snake == "rv_timer":
, 0
% endif
- ),
- kDifOk);
+ ));
}
class IrqAcknowledgeTest : public ${ip.name_camel}Test {};
TEST_F(IrqAcknowledgeTest, NullArgs) {
- EXPECT_EQ(dif_${ip.name_snake}_irq_acknowledge(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_irq_acknowledge(
nullptr,
% if ip.irqs[0].width > 1:
- kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}0),
+ kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}0));
% else:
- kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}),
+ kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}));
% endif
- kDifBadArg);
}
TEST_F(IrqAcknowledgeTest, BadIrq) {
- EXPECT_EQ(dif_${ip.name_snake}_irq_acknowledge(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_irq_acknowledge(
nullptr,
- static_cast<dif_${ip.name_snake}_irq_t>(32)),
- kDifBadArg);
+ static_cast<dif_${ip.name_snake}_irq_t>(32)));
}
TEST_F(IrqAcknowledgeTest, Success) {
@@ -330,14 +309,13 @@
{{${ip.name_upper}_INTR_STATE_${ip.irqs[0].name_upper}_BIT, true}});
% endif
% endif
- EXPECT_EQ(dif_${ip.name_snake}_irq_acknowledge(
+ EXPECT_DIF_OK(dif_${ip.name_snake}_irq_acknowledge(
&${ip.name_snake}_,
% if ip.irqs[0].width > 1:
- kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}0),
+ kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}0));
% else:
- kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}),
+ kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}));
% endif
- kDifOk);
% if len(ip.irqs) > 1 or ip.irqs[0].width > 1:
// Clear the last IRQ state.
@@ -353,35 +331,32 @@
{{${ip.name_upper}_INTR_STATE_${ip.irqs[-1].name_upper}_BIT, true}});
% endif
% endif
- EXPECT_EQ(dif_${ip.name_snake}_irq_acknowledge(
+ EXPECT_DIF_OK(dif_${ip.name_snake}_irq_acknowledge(
&${ip.name_snake}_,
% if ip.irqs[0].width > 1:
- kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}${ip.irqs[0].width - 1}),
+ kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}${ip.irqs[0].width - 1}));
% else:
- kDif${ip.name_camel}Irq${ip.irqs[-1].name_camel}),
+ kDif${ip.name_camel}Irq${ip.irqs[-1].name_camel}));
% endif
- kDifOk);
% endif
}
class IrqForceTest : public ${ip.name_camel}Test {};
TEST_F(IrqForceTest, NullArgs) {
- EXPECT_EQ(dif_${ip.name_snake}_irq_force(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_irq_force(
nullptr,
% if ip.irqs[0].width > 1:
- kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}0),
+ kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}0));
% else:
- kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}),
+ kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}));
% endif
- kDifBadArg);
}
TEST_F(IrqForceTest, BadIrq) {
- EXPECT_EQ(dif_${ip.name_snake}_irq_force(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_irq_force(
nullptr,
- static_cast<dif_${ip.name_snake}_irq_t>(32)),
- kDifBadArg);
+ static_cast<dif_${ip.name_snake}_irq_t>(32)));
}
TEST_F(IrqForceTest, Success) {
@@ -397,14 +372,13 @@
{{${ip.name_upper}_INTR_TEST_${ip.irqs[0].name_upper}_BIT, true}});
% endif
% endif
- EXPECT_EQ(dif_${ip.name_snake}_irq_force(
+ EXPECT_DIF_OK(dif_${ip.name_snake}_irq_force(
&${ip.name_snake}_,
% if ip.irqs[0].width > 1:
- kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}0),
+ kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}0));
% else:
- kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}),
+ kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}));
% endif
- kDifOk);
% if len(ip.irqs) > 1 or ip.irqs[0].width > 1:
// Force last IRQ.
@@ -420,14 +394,13 @@
{{${ip.name_upper}_INTR_TEST_${ip.irqs[-1].name_upper}_BIT, true}});
% endif
% endif
- EXPECT_EQ(dif_${ip.name_snake}_irq_force(
+ EXPECT_DIF_OK(dif_${ip.name_snake}_irq_force(
&${ip.name_snake}_,
% if ip.irqs[0].width > 1:
- kDif${ip.name_camel}Irq${ip.irqs[-1].name_camel}${ip.irqs[0].width - 1}),
+ kDif${ip.name_camel}Irq${ip.irqs[-1].name_camel}${ip.irqs[0].width - 1}));
% else:
- kDif${ip.name_camel}Irq${ip.irqs[-1].name_camel}),
+ kDif${ip.name_camel}Irq${ip.irqs[-1].name_camel}));
% endif
- kDifOk);
% endif
}
@@ -437,45 +410,41 @@
TEST_F(IrqGetEnabledTest, NullArgs) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_${ip.name_snake}_irq_get_enabled(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_irq_get_enabled(
nullptr,
% if ip.irqs[0].width > 1:
kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}0,
% else:
kDif${ip.name_camel}Irq${ip.irqs[0].name_camel},
% endif
- &irq_state),
- kDifBadArg);
+ &irq_state));
- EXPECT_EQ(dif_${ip.name_snake}_irq_get_enabled(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_irq_get_enabled(
&${ip.name_snake}_,
% if ip.irqs[0].width > 1:
kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}0,
% else:
kDif${ip.name_camel}Irq${ip.irqs[0].name_camel},
% endif
- nullptr),
- kDifBadArg);
+ nullptr));
- EXPECT_EQ(dif_${ip.name_snake}_irq_get_enabled(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_irq_get_enabled(
nullptr,
% if ip.irqs[0].width > 1:
kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}0,
% else:
kDif${ip.name_camel}Irq${ip.irqs[0].name_camel},
% endif
- nullptr),
- kDifBadArg);
+ nullptr));
}
TEST_F(IrqGetEnabledTest, BadIrq) {
dif_toggle_t irq_state;
- EXPECT_EQ(dif_${ip.name_snake}_irq_get_enabled(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_irq_get_enabled(
&${ip.name_snake}_,
static_cast<dif_${ip.name_snake}_irq_t>(32),
- &irq_state),
- kDifBadArg);
+ &irq_state));
}
TEST_F(IrqGetEnabledTest, Success) {
@@ -494,15 +463,14 @@
{{${ip.name_upper}_INTR_ENABLE_${ip.irqs[0].name_upper}_BIT, true}});
% endif
% endif
- EXPECT_EQ(dif_${ip.name_snake}_irq_get_enabled(
+ EXPECT_DIF_OK(dif_${ip.name_snake}_irq_get_enabled(
&${ip.name_snake}_,
% if ip.irqs[0].width > 1:
kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}0,
% else:
kDif${ip.name_camel}Irq${ip.irqs[0].name_camel},
% endif
- &irq_state),
- kDifOk);
+ &irq_state));
EXPECT_EQ(irq_state, kDifToggleEnabled);
% if len(ip.irqs) > 1 or ip.irqs[0].width > 1:
@@ -520,15 +488,14 @@
{{${ip.name_upper}_INTR_ENABLE_${ip.irqs[-1].name_upper}_BIT, false}});
% endif
% endif
- EXPECT_EQ(dif_${ip.name_snake}_irq_get_enabled(
+ EXPECT_DIF_OK(dif_${ip.name_snake}_irq_get_enabled(
&${ip.name_snake}_,
% if ip.irqs[0].width > 1:
kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}${ip.irqs[0].width - 1},
% else:
kDif${ip.name_camel}Irq${ip.irqs[-1].name_camel},
% endif
- &irq_state),
- kDifOk);
+ &irq_state));
EXPECT_EQ(irq_state, kDifToggleDisabled);
% endif
}
@@ -538,25 +505,23 @@
TEST_F(IrqSetEnabledTest, NullArgs) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_${ip.name_snake}_irq_set_enabled(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_irq_set_enabled(
nullptr,
% if ip.irqs[0].width > 1:
kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}0,
% else:
kDif${ip.name_camel}Irq${ip.irqs[0].name_camel},
% endif
- irq_state),
- kDifBadArg);
+ irq_state));
}
TEST_F(IrqSetEnabledTest, BadIrq) {
dif_toggle_t irq_state = kDifToggleEnabled;
- EXPECT_EQ(dif_${ip.name_snake}_irq_set_enabled(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_irq_set_enabled(
&${ip.name_snake}_,
static_cast<dif_${ip.name_snake}_irq_t>(32),
- irq_state),
- kDifBadArg);
+ irq_state));
}
TEST_F(IrqSetEnabledTest, Success) {
@@ -575,15 +540,14 @@
{{${ip.name_upper}_INTR_ENABLE_${ip.irqs[0].name_upper}_BIT, 0x1, true}});
% endif
% endif
- EXPECT_EQ(dif_${ip.name_snake}_irq_set_enabled(
+ EXPECT_DIF_OK(dif_${ip.name_snake}_irq_set_enabled(
&${ip.name_snake}_,
% if ip.irqs[0].width > 1:
kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}0,
% else:
kDif${ip.name_camel}Irq${ip.irqs[0].name_camel},
% endif
- irq_state),
- kDifOk);
+ irq_state));
% if len(ip.irqs) > 1 or ip.irqs[0].width > 1:
// Disable last IRQ.
@@ -600,15 +564,14 @@
{{${ip.name_upper}_INTR_ENABLE_${ip.irqs[-1].name_upper}_BIT, 0x1, false}});
% endif
% endif
- EXPECT_EQ(dif_${ip.name_snake}_irq_set_enabled(
+ EXPECT_DIF_OK(dif_${ip.name_snake}_irq_set_enabled(
&${ip.name_snake}_,
% if ip.irqs[0].width > 1:
kDif${ip.name_camel}Irq${ip.irqs[0].name_camel}${ip.irqs[0].width - 1},
% else:
kDif${ip.name_camel}Irq${ip.irqs[-1].name_camel},
% endif
- irq_state),
- kDifOk);
+ irq_state));
% endif
}
@@ -617,21 +580,19 @@
TEST_F(IrqDisableAllTest, NullArgs) {
dif_${ip.name_snake}_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_${ip.name_snake}_irq_disable_all(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_irq_disable_all(
nullptr,
% if ip.name_snake == "rv_timer":
0,
% endif
- &irq_snapshot),
- kDifBadArg);
+ &irq_snapshot));
- EXPECT_EQ(dif_${ip.name_snake}_irq_disable_all(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_irq_disable_all(
nullptr,
% if ip.name_snake == "rv_timer":
0,
% endif
- nullptr),
- kDifBadArg);
+ nullptr));
}
TEST_F(IrqDisableAllTest, SuccessNoSnapshot) {
@@ -640,13 +601,12 @@
% else:
EXPECT_WRITE32(${ip.name_upper}_INTR_ENABLE_REG_OFFSET, 0);
% endif
- EXPECT_EQ(dif_${ip.name_snake}_irq_disable_all(
+ EXPECT_DIF_OK(dif_${ip.name_snake}_irq_disable_all(
&${ip.name_snake}_,
% if ip.name_snake == "rv_timer":
0,
% endif
- nullptr),
- kDifOk);
+ nullptr));
}
TEST_F(IrqDisableAllTest, SuccessSnapshotAllDisabled) {
@@ -659,13 +619,12 @@
EXPECT_READ32(${ip.name_upper}_INTR_ENABLE_REG_OFFSET, 0);
EXPECT_WRITE32(${ip.name_upper}_INTR_ENABLE_REG_OFFSET, 0);
% endif
- EXPECT_EQ(dif_${ip.name_snake}_irq_disable_all(
+ EXPECT_DIF_OK(dif_${ip.name_snake}_irq_disable_all(
&${ip.name_snake}_,
% if ip.name_snake == "rv_timer":
0,
% endif
- &irq_snapshot),
- kDifOk);
+ &irq_snapshot));
EXPECT_EQ(irq_snapshot, 0);
}
@@ -681,13 +640,12 @@
std::numeric_limits<uint32_t>::max());
EXPECT_WRITE32(${ip.name_upper}_INTR_ENABLE_REG_OFFSET, 0);
% endif
- EXPECT_EQ(dif_${ip.name_snake}_irq_disable_all(
+ EXPECT_DIF_OK(dif_${ip.name_snake}_irq_disable_all(
&${ip.name_snake}_,
% if ip.name_snake == "rv_timer":
0,
% endif
- &irq_snapshot),
- kDifOk);
+ &irq_snapshot));
EXPECT_EQ(irq_snapshot, std::numeric_limits<uint32_t>::max());
}
@@ -696,29 +654,26 @@
TEST_F(IrqRestoreAllTest, NullArgs) {
dif_${ip.name_snake}_irq_enable_snapshot_t irq_snapshot = 0;
- EXPECT_EQ(dif_${ip.name_snake}_irq_restore_all(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_irq_restore_all(
nullptr,
% if ip.name_snake == "rv_timer":
0,
% endif
- &irq_snapshot),
- kDifBadArg);
+ &irq_snapshot));
- EXPECT_EQ(dif_${ip.name_snake}_irq_restore_all(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_irq_restore_all(
&${ip.name_snake}_,
% if ip.name_snake == "rv_timer":
0,
% endif
- nullptr),
- kDifBadArg);
+ nullptr));
- EXPECT_EQ(dif_${ip.name_snake}_irq_restore_all(
+ EXPECT_DIF_BADARG(dif_${ip.name_snake}_irq_restore_all(
nullptr,
% if ip.name_snake == "rv_timer":
0,
% endif
- nullptr),
- kDifBadArg);
+ nullptr));
}
TEST_F(IrqRestoreAllTest, SuccessAllEnabled) {
@@ -731,13 +686,12 @@
EXPECT_WRITE32(${ip.name_upper}_INTR_ENABLE_REG_OFFSET,
% endif
std::numeric_limits<uint32_t>::max());
- EXPECT_EQ(dif_${ip.name_snake}_irq_restore_all(
+ EXPECT_DIF_OK(dif_${ip.name_snake}_irq_restore_all(
&${ip.name_snake}_,
% if ip.name_snake == "rv_timer":
0,
% endif
- &irq_snapshot),
- kDifOk);
+ &irq_snapshot));
}
TEST_F(IrqRestoreAllTest, SuccessAllDisabled) {
@@ -748,13 +702,12 @@
% else:
EXPECT_WRITE32(${ip.name_upper}_INTR_ENABLE_REG_OFFSET, 0);
% endif
- EXPECT_EQ(dif_${ip.name_snake}_irq_restore_all(
+ EXPECT_DIF_OK(dif_${ip.name_snake}_irq_restore_all(
&${ip.name_snake}_,
% if ip.name_snake == "rv_timer":
0,
% endif
- &irq_snapshot),
- kDifOk);
+ &irq_snapshot));
}
% endif
