[flash] Fix default region sizing
- Addresses #2755
- Ensures the last region when there are power of 2 regions can be covered
- This fix is techincally only needed only when number of pages are powers of 2
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.hjson b/hw/ip/flash_ctrl/data/flash_ctrl.hjson
index 05d192f..1edaaee 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.hjson
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.hjson
@@ -293,14 +293,14 @@
''',
resval: "0"
},
- { bits: "24:16",
+ { bits: "25:16", // need to template this term long term for flash size
name: "SIZE",
desc: '''
Region size in number of pages
''',
resval: "0"
},
- { bits: "25",
+ { bits: "28",
name: "PARTITION",
desc: '''
Region partition select
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
index 436ea28..f8bae22 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
@@ -312,7 +312,7 @@
//default region
assign region_cfgs[MpRegions].base.q = '0;
- assign region_cfgs[MpRegions].size.q = {AllPagesW{1'b1}};
+ assign region_cfgs[MpRegions].size.q = NumBanks * PagesPerBank;
assign region_cfgs[MpRegions].en.q = 1'b1;
assign region_cfgs[MpRegions].rd_en.q = reg2hw.default_region.rd_en.q;
assign region_cfgs[MpRegions].prog_en.q = reg2hw.default_region.prog_en.q;
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
index cf3e44f..5a3e6f6 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
@@ -121,7 +121,7 @@
logic [8:0] q;
} base;
struct packed {
- logic [8:0] q;
+ logic [9:0] q;
} size;
struct packed {
logic q;
@@ -240,12 +240,12 @@
// Register to internal design logic //
///////////////////////////////////////
typedef struct packed {
- flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [304:299]
- flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [298:293]
- flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [292:281]
- flash_ctrl_reg2hw_control_reg_t control; // [280:264]
- flash_ctrl_reg2hw_addr_reg_t addr; // [263:232]
- flash_ctrl_reg2hw_mp_region_cfg_mreg_t [7:0] mp_region_cfg; // [231:48]
+ flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [312:307]
+ flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [306:301]
+ flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [300:289]
+ flash_ctrl_reg2hw_control_reg_t control; // [288:272]
+ flash_ctrl_reg2hw_addr_reg_t addr; // [271:240]
+ flash_ctrl_reg2hw_mp_region_cfg_mreg_t [7:0] mp_region_cfg; // [239:48]
flash_ctrl_reg2hw_default_region_reg_t default_region; // [47:45]
flash_ctrl_reg2hw_mp_bank_cfg_mreg_t [1:0] mp_bank_cfg; // [44:43]
flash_ctrl_reg2hw_scratch_reg_t scratch; // [42:11]
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv
index c076989..f7da02c 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv
@@ -207,8 +207,8 @@
logic [8:0] mp_region_cfg0_base0_qs;
logic [8:0] mp_region_cfg0_base0_wd;
logic mp_region_cfg0_base0_we;
- logic [8:0] mp_region_cfg0_size0_qs;
- logic [8:0] mp_region_cfg0_size0_wd;
+ logic [9:0] mp_region_cfg0_size0_qs;
+ logic [9:0] mp_region_cfg0_size0_wd;
logic mp_region_cfg0_size0_we;
logic mp_region_cfg0_partition0_qs;
logic mp_region_cfg0_partition0_wd;
@@ -228,8 +228,8 @@
logic [8:0] mp_region_cfg1_base1_qs;
logic [8:0] mp_region_cfg1_base1_wd;
logic mp_region_cfg1_base1_we;
- logic [8:0] mp_region_cfg1_size1_qs;
- logic [8:0] mp_region_cfg1_size1_wd;
+ logic [9:0] mp_region_cfg1_size1_qs;
+ logic [9:0] mp_region_cfg1_size1_wd;
logic mp_region_cfg1_size1_we;
logic mp_region_cfg1_partition1_qs;
logic mp_region_cfg1_partition1_wd;
@@ -249,8 +249,8 @@
logic [8:0] mp_region_cfg2_base2_qs;
logic [8:0] mp_region_cfg2_base2_wd;
logic mp_region_cfg2_base2_we;
- logic [8:0] mp_region_cfg2_size2_qs;
- logic [8:0] mp_region_cfg2_size2_wd;
+ logic [9:0] mp_region_cfg2_size2_qs;
+ logic [9:0] mp_region_cfg2_size2_wd;
logic mp_region_cfg2_size2_we;
logic mp_region_cfg2_partition2_qs;
logic mp_region_cfg2_partition2_wd;
@@ -270,8 +270,8 @@
logic [8:0] mp_region_cfg3_base3_qs;
logic [8:0] mp_region_cfg3_base3_wd;
logic mp_region_cfg3_base3_we;
- logic [8:0] mp_region_cfg3_size3_qs;
- logic [8:0] mp_region_cfg3_size3_wd;
+ logic [9:0] mp_region_cfg3_size3_qs;
+ logic [9:0] mp_region_cfg3_size3_wd;
logic mp_region_cfg3_size3_we;
logic mp_region_cfg3_partition3_qs;
logic mp_region_cfg3_partition3_wd;
@@ -291,8 +291,8 @@
logic [8:0] mp_region_cfg4_base4_qs;
logic [8:0] mp_region_cfg4_base4_wd;
logic mp_region_cfg4_base4_we;
- logic [8:0] mp_region_cfg4_size4_qs;
- logic [8:0] mp_region_cfg4_size4_wd;
+ logic [9:0] mp_region_cfg4_size4_qs;
+ logic [9:0] mp_region_cfg4_size4_wd;
logic mp_region_cfg4_size4_we;
logic mp_region_cfg4_partition4_qs;
logic mp_region_cfg4_partition4_wd;
@@ -312,8 +312,8 @@
logic [8:0] mp_region_cfg5_base5_qs;
logic [8:0] mp_region_cfg5_base5_wd;
logic mp_region_cfg5_base5_we;
- logic [8:0] mp_region_cfg5_size5_qs;
- logic [8:0] mp_region_cfg5_size5_wd;
+ logic [9:0] mp_region_cfg5_size5_qs;
+ logic [9:0] mp_region_cfg5_size5_wd;
logic mp_region_cfg5_size5_we;
logic mp_region_cfg5_partition5_qs;
logic mp_region_cfg5_partition5_wd;
@@ -333,8 +333,8 @@
logic [8:0] mp_region_cfg6_base6_qs;
logic [8:0] mp_region_cfg6_base6_wd;
logic mp_region_cfg6_base6_we;
- logic [8:0] mp_region_cfg6_size6_qs;
- logic [8:0] mp_region_cfg6_size6_wd;
+ logic [9:0] mp_region_cfg6_size6_qs;
+ logic [9:0] mp_region_cfg6_size6_wd;
logic mp_region_cfg6_size6_we;
logic mp_region_cfg6_partition6_qs;
logic mp_region_cfg6_partition6_wd;
@@ -354,8 +354,8 @@
logic [8:0] mp_region_cfg7_base7_qs;
logic [8:0] mp_region_cfg7_base7_wd;
logic mp_region_cfg7_base7_we;
- logic [8:0] mp_region_cfg7_size7_qs;
- logic [8:0] mp_region_cfg7_size7_wd;
+ logic [9:0] mp_region_cfg7_size7_qs;
+ logic [9:0] mp_region_cfg7_size7_wd;
logic mp_region_cfg7_size7_we;
logic mp_region_cfg7_partition7_qs;
logic mp_region_cfg7_partition7_wd;
@@ -1156,11 +1156,11 @@
);
- // F[size0]: 24:16
+ // F[size0]: 25:16
prim_subreg #(
- .DW (9),
+ .DW (10),
.SWACCESS("RW"),
- .RESVAL (9'h0)
+ .RESVAL (10'h0)
) u_mp_region_cfg0_size0 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
@@ -1182,7 +1182,7 @@
);
- // F[partition0]: 25:25
+ // F[partition0]: 28:28
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
@@ -1341,11 +1341,11 @@
);
- // F[size1]: 24:16
+ // F[size1]: 25:16
prim_subreg #(
- .DW (9),
+ .DW (10),
.SWACCESS("RW"),
- .RESVAL (9'h0)
+ .RESVAL (10'h0)
) u_mp_region_cfg1_size1 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
@@ -1367,7 +1367,7 @@
);
- // F[partition1]: 25:25
+ // F[partition1]: 28:28
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
@@ -1526,11 +1526,11 @@
);
- // F[size2]: 24:16
+ // F[size2]: 25:16
prim_subreg #(
- .DW (9),
+ .DW (10),
.SWACCESS("RW"),
- .RESVAL (9'h0)
+ .RESVAL (10'h0)
) u_mp_region_cfg2_size2 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
@@ -1552,7 +1552,7 @@
);
- // F[partition2]: 25:25
+ // F[partition2]: 28:28
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
@@ -1711,11 +1711,11 @@
);
- // F[size3]: 24:16
+ // F[size3]: 25:16
prim_subreg #(
- .DW (9),
+ .DW (10),
.SWACCESS("RW"),
- .RESVAL (9'h0)
+ .RESVAL (10'h0)
) u_mp_region_cfg3_size3 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
@@ -1737,7 +1737,7 @@
);
- // F[partition3]: 25:25
+ // F[partition3]: 28:28
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
@@ -1896,11 +1896,11 @@
);
- // F[size4]: 24:16
+ // F[size4]: 25:16
prim_subreg #(
- .DW (9),
+ .DW (10),
.SWACCESS("RW"),
- .RESVAL (9'h0)
+ .RESVAL (10'h0)
) u_mp_region_cfg4_size4 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
@@ -1922,7 +1922,7 @@
);
- // F[partition4]: 25:25
+ // F[partition4]: 28:28
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
@@ -2081,11 +2081,11 @@
);
- // F[size5]: 24:16
+ // F[size5]: 25:16
prim_subreg #(
- .DW (9),
+ .DW (10),
.SWACCESS("RW"),
- .RESVAL (9'h0)
+ .RESVAL (10'h0)
) u_mp_region_cfg5_size5 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
@@ -2107,7 +2107,7 @@
);
- // F[partition5]: 25:25
+ // F[partition5]: 28:28
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
@@ -2266,11 +2266,11 @@
);
- // F[size6]: 24:16
+ // F[size6]: 25:16
prim_subreg #(
- .DW (9),
+ .DW (10),
.SWACCESS("RW"),
- .RESVAL (9'h0)
+ .RESVAL (10'h0)
) u_mp_region_cfg6_size6 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
@@ -2292,7 +2292,7 @@
);
- // F[partition6]: 25:25
+ // F[partition6]: 28:28
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
@@ -2451,11 +2451,11 @@
);
- // F[size7]: 24:16
+ // F[size7]: 25:16
prim_subreg #(
- .DW (9),
+ .DW (10),
.SWACCESS("RW"),
- .RESVAL (9'h0)
+ .RESVAL (10'h0)
) u_mp_region_cfg7_size7 (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
@@ -2477,7 +2477,7 @@
);
- // F[partition7]: 25:25
+ // F[partition7]: 28:28
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
@@ -3090,10 +3090,10 @@
assign mp_region_cfg0_base0_wd = reg_wdata[12:4];
assign mp_region_cfg0_size0_we = addr_hit[7] & reg_we & ~wr_err;
- assign mp_region_cfg0_size0_wd = reg_wdata[24:16];
+ assign mp_region_cfg0_size0_wd = reg_wdata[25:16];
assign mp_region_cfg0_partition0_we = addr_hit[7] & reg_we & ~wr_err;
- assign mp_region_cfg0_partition0_wd = reg_wdata[25];
+ assign mp_region_cfg0_partition0_wd = reg_wdata[28];
assign mp_region_cfg1_en1_we = addr_hit[8] & reg_we & ~wr_err;
assign mp_region_cfg1_en1_wd = reg_wdata[0];
@@ -3111,10 +3111,10 @@
assign mp_region_cfg1_base1_wd = reg_wdata[12:4];
assign mp_region_cfg1_size1_we = addr_hit[8] & reg_we & ~wr_err;
- assign mp_region_cfg1_size1_wd = reg_wdata[24:16];
+ assign mp_region_cfg1_size1_wd = reg_wdata[25:16];
assign mp_region_cfg1_partition1_we = addr_hit[8] & reg_we & ~wr_err;
- assign mp_region_cfg1_partition1_wd = reg_wdata[25];
+ assign mp_region_cfg1_partition1_wd = reg_wdata[28];
assign mp_region_cfg2_en2_we = addr_hit[9] & reg_we & ~wr_err;
assign mp_region_cfg2_en2_wd = reg_wdata[0];
@@ -3132,10 +3132,10 @@
assign mp_region_cfg2_base2_wd = reg_wdata[12:4];
assign mp_region_cfg2_size2_we = addr_hit[9] & reg_we & ~wr_err;
- assign mp_region_cfg2_size2_wd = reg_wdata[24:16];
+ assign mp_region_cfg2_size2_wd = reg_wdata[25:16];
assign mp_region_cfg2_partition2_we = addr_hit[9] & reg_we & ~wr_err;
- assign mp_region_cfg2_partition2_wd = reg_wdata[25];
+ assign mp_region_cfg2_partition2_wd = reg_wdata[28];
assign mp_region_cfg3_en3_we = addr_hit[10] & reg_we & ~wr_err;
assign mp_region_cfg3_en3_wd = reg_wdata[0];
@@ -3153,10 +3153,10 @@
assign mp_region_cfg3_base3_wd = reg_wdata[12:4];
assign mp_region_cfg3_size3_we = addr_hit[10] & reg_we & ~wr_err;
- assign mp_region_cfg3_size3_wd = reg_wdata[24:16];
+ assign mp_region_cfg3_size3_wd = reg_wdata[25:16];
assign mp_region_cfg3_partition3_we = addr_hit[10] & reg_we & ~wr_err;
- assign mp_region_cfg3_partition3_wd = reg_wdata[25];
+ assign mp_region_cfg3_partition3_wd = reg_wdata[28];
assign mp_region_cfg4_en4_we = addr_hit[11] & reg_we & ~wr_err;
assign mp_region_cfg4_en4_wd = reg_wdata[0];
@@ -3174,10 +3174,10 @@
assign mp_region_cfg4_base4_wd = reg_wdata[12:4];
assign mp_region_cfg4_size4_we = addr_hit[11] & reg_we & ~wr_err;
- assign mp_region_cfg4_size4_wd = reg_wdata[24:16];
+ assign mp_region_cfg4_size4_wd = reg_wdata[25:16];
assign mp_region_cfg4_partition4_we = addr_hit[11] & reg_we & ~wr_err;
- assign mp_region_cfg4_partition4_wd = reg_wdata[25];
+ assign mp_region_cfg4_partition4_wd = reg_wdata[28];
assign mp_region_cfg5_en5_we = addr_hit[12] & reg_we & ~wr_err;
assign mp_region_cfg5_en5_wd = reg_wdata[0];
@@ -3195,10 +3195,10 @@
assign mp_region_cfg5_base5_wd = reg_wdata[12:4];
assign mp_region_cfg5_size5_we = addr_hit[12] & reg_we & ~wr_err;
- assign mp_region_cfg5_size5_wd = reg_wdata[24:16];
+ assign mp_region_cfg5_size5_wd = reg_wdata[25:16];
assign mp_region_cfg5_partition5_we = addr_hit[12] & reg_we & ~wr_err;
- assign mp_region_cfg5_partition5_wd = reg_wdata[25];
+ assign mp_region_cfg5_partition5_wd = reg_wdata[28];
assign mp_region_cfg6_en6_we = addr_hit[13] & reg_we & ~wr_err;
assign mp_region_cfg6_en6_wd = reg_wdata[0];
@@ -3216,10 +3216,10 @@
assign mp_region_cfg6_base6_wd = reg_wdata[12:4];
assign mp_region_cfg6_size6_we = addr_hit[13] & reg_we & ~wr_err;
- assign mp_region_cfg6_size6_wd = reg_wdata[24:16];
+ assign mp_region_cfg6_size6_wd = reg_wdata[25:16];
assign mp_region_cfg6_partition6_we = addr_hit[13] & reg_we & ~wr_err;
- assign mp_region_cfg6_partition6_wd = reg_wdata[25];
+ assign mp_region_cfg6_partition6_wd = reg_wdata[28];
assign mp_region_cfg7_en7_we = addr_hit[14] & reg_we & ~wr_err;
assign mp_region_cfg7_en7_wd = reg_wdata[0];
@@ -3237,10 +3237,10 @@
assign mp_region_cfg7_base7_wd = reg_wdata[12:4];
assign mp_region_cfg7_size7_we = addr_hit[14] & reg_we & ~wr_err;
- assign mp_region_cfg7_size7_wd = reg_wdata[24:16];
+ assign mp_region_cfg7_size7_wd = reg_wdata[25:16];
assign mp_region_cfg7_partition7_we = addr_hit[14] & reg_we & ~wr_err;
- assign mp_region_cfg7_partition7_wd = reg_wdata[25];
+ assign mp_region_cfg7_partition7_wd = reg_wdata[28];
assign default_region_rd_en_we = addr_hit[15] & reg_we & ~wr_err;
assign default_region_rd_en_wd = reg_wdata[0];
@@ -3349,8 +3349,8 @@
reg_rdata_next[2] = mp_region_cfg0_prog_en0_qs;
reg_rdata_next[3] = mp_region_cfg0_erase_en0_qs;
reg_rdata_next[12:4] = mp_region_cfg0_base0_qs;
- reg_rdata_next[24:16] = mp_region_cfg0_size0_qs;
- reg_rdata_next[25] = mp_region_cfg0_partition0_qs;
+ reg_rdata_next[25:16] = mp_region_cfg0_size0_qs;
+ reg_rdata_next[28] = mp_region_cfg0_partition0_qs;
end
addr_hit[8]: begin
@@ -3359,8 +3359,8 @@
reg_rdata_next[2] = mp_region_cfg1_prog_en1_qs;
reg_rdata_next[3] = mp_region_cfg1_erase_en1_qs;
reg_rdata_next[12:4] = mp_region_cfg1_base1_qs;
- reg_rdata_next[24:16] = mp_region_cfg1_size1_qs;
- reg_rdata_next[25] = mp_region_cfg1_partition1_qs;
+ reg_rdata_next[25:16] = mp_region_cfg1_size1_qs;
+ reg_rdata_next[28] = mp_region_cfg1_partition1_qs;
end
addr_hit[9]: begin
@@ -3369,8 +3369,8 @@
reg_rdata_next[2] = mp_region_cfg2_prog_en2_qs;
reg_rdata_next[3] = mp_region_cfg2_erase_en2_qs;
reg_rdata_next[12:4] = mp_region_cfg2_base2_qs;
- reg_rdata_next[24:16] = mp_region_cfg2_size2_qs;
- reg_rdata_next[25] = mp_region_cfg2_partition2_qs;
+ reg_rdata_next[25:16] = mp_region_cfg2_size2_qs;
+ reg_rdata_next[28] = mp_region_cfg2_partition2_qs;
end
addr_hit[10]: begin
@@ -3379,8 +3379,8 @@
reg_rdata_next[2] = mp_region_cfg3_prog_en3_qs;
reg_rdata_next[3] = mp_region_cfg3_erase_en3_qs;
reg_rdata_next[12:4] = mp_region_cfg3_base3_qs;
- reg_rdata_next[24:16] = mp_region_cfg3_size3_qs;
- reg_rdata_next[25] = mp_region_cfg3_partition3_qs;
+ reg_rdata_next[25:16] = mp_region_cfg3_size3_qs;
+ reg_rdata_next[28] = mp_region_cfg3_partition3_qs;
end
addr_hit[11]: begin
@@ -3389,8 +3389,8 @@
reg_rdata_next[2] = mp_region_cfg4_prog_en4_qs;
reg_rdata_next[3] = mp_region_cfg4_erase_en4_qs;
reg_rdata_next[12:4] = mp_region_cfg4_base4_qs;
- reg_rdata_next[24:16] = mp_region_cfg4_size4_qs;
- reg_rdata_next[25] = mp_region_cfg4_partition4_qs;
+ reg_rdata_next[25:16] = mp_region_cfg4_size4_qs;
+ reg_rdata_next[28] = mp_region_cfg4_partition4_qs;
end
addr_hit[12]: begin
@@ -3399,8 +3399,8 @@
reg_rdata_next[2] = mp_region_cfg5_prog_en5_qs;
reg_rdata_next[3] = mp_region_cfg5_erase_en5_qs;
reg_rdata_next[12:4] = mp_region_cfg5_base5_qs;
- reg_rdata_next[24:16] = mp_region_cfg5_size5_qs;
- reg_rdata_next[25] = mp_region_cfg5_partition5_qs;
+ reg_rdata_next[25:16] = mp_region_cfg5_size5_qs;
+ reg_rdata_next[28] = mp_region_cfg5_partition5_qs;
end
addr_hit[13]: begin
@@ -3409,8 +3409,8 @@
reg_rdata_next[2] = mp_region_cfg6_prog_en6_qs;
reg_rdata_next[3] = mp_region_cfg6_erase_en6_qs;
reg_rdata_next[12:4] = mp_region_cfg6_base6_qs;
- reg_rdata_next[24:16] = mp_region_cfg6_size6_qs;
- reg_rdata_next[25] = mp_region_cfg6_partition6_qs;
+ reg_rdata_next[25:16] = mp_region_cfg6_size6_qs;
+ reg_rdata_next[28] = mp_region_cfg6_partition6_qs;
end
addr_hit[14]: begin
@@ -3419,8 +3419,8 @@
reg_rdata_next[2] = mp_region_cfg7_prog_en7_qs;
reg_rdata_next[3] = mp_region_cfg7_erase_en7_qs;
reg_rdata_next[12:4] = mp_region_cfg7_base7_qs;
- reg_rdata_next[24:16] = mp_region_cfg7_size7_qs;
- reg_rdata_next[25] = mp_region_cfg7_partition7_qs;
+ reg_rdata_next[25:16] = mp_region_cfg7_size7_qs;
+ reg_rdata_next[28] = mp_region_cfg7_partition7_qs;
end
addr_hit[15]: begin
diff --git a/hw/ip/flash_ctrl/rtl/flash_mp.sv b/hw/ip/flash_ctrl/rtl/flash_mp.sv
index 785d7d3..31e7fae 100644
--- a/hw/ip/flash_ctrl/rtl/flash_mp.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_mp.sv
@@ -55,7 +55,8 @@
localparam int LastValidInfoPage = InfosPerBank - 1;
// There could be multiple region matches due to region overlap
- logic [AllPagesW-1:0] region_end[TotalRegions];
+ // region_end is +1 bit from however bits are needed to address regions
+ logic [AllPagesW:0] region_end[TotalRegions];
logic [TotalRegions-1:0] region_match;
logic [TotalRegions-1:0] region_sel;
logic [TotalRegions-1:0] rd_en;
@@ -76,11 +77,11 @@
// check for region match
always_comb begin
for (int unsigned i = 0; i < TotalRegions; i++) begin: region_comps
- region_end[i] = region_cfgs_i[i].base.q + region_cfgs_i[i].size.q;
+ region_end[i] = {1'b0, region_cfgs_i[i].base.q} + region_cfgs_i[i].size.q;
// region matches if address within range and if the partition matches
region_match[i] = req_addr_i >= region_cfgs_i[i].base.q &
- req_addr_i < region_end[i] &
+ {1'b0, req_addr_i} < region_end[i] &
req_part_i == region_cfgs_i[i].partition.q &
region_cfgs_i[i].en.q &
req_i;
