| commit | 88a861588795ccd2c43603096cd007600412ec2f | [log] [tgz] |
|---|---|---|
| author | Eunchan Kim <eunchan@opentitan.org> | Mon Apr 13 16:12:08 2020 -0700 |
| committer | Eunchan Kim <eunchan@opentitan.org> | Thu Apr 16 09:38:39 2020 -0700 |
| tree | b89d5b0b0e27de8d238ec09c1f22a1d153955b84 | |
| parent | ab72a5fe1b6e990e9f0a4f79db395852ef712d5c [diff] |
[rv_plic] Change PRIO number starting from 1 As discussed in #1823, this PR is to match the PRIO* registers name to the ID read in CC register. Previously, ID read from CC register is not matched with the offset of PRIO0, IS, IE, IP. For example, if the software read 0x3 value from CC register, its corresponding bit in IS is IS[2]. PLIC now generates ID w.r.t the interrupt source bit position. RISC-V PLIC spec requires to return ID value 0 when no interrupt. So, topgen ties bit0 of interrupt source signal to 0. By doing in this way, reggen doesn't have to support arithmetic operation to the parameter. Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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$ sudo apt install curl python3 python3-pip $ pip3 install --user -r python-requirements.txt
$ ./util/build_docs.py --preview
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