[top] Change pad variant array to packed logic
The default assignment to the unpacked array caused issues in DC, and
also caused the assignment order to be the reverse of the port
assignment order when using vector concatenation, which is inconvenient.
Hence, this is changed to a packed array of logics.
Signed-off-by: Michael Schaffner <msf@google.com>
diff --git a/hw/ip/padctrl/rtl/padring.sv b/hw/ip/padctrl/rtl/padring.sv
index f11f5c9..02ef426 100644
--- a/hw/ip/padctrl/rtl/padring.sv
+++ b/hw/ip/padctrl/rtl/padring.sv
@@ -18,8 +18,8 @@
parameter logic [NDioPads-1:0] ConnectDioOut = '1,
// 0: bidir, 1: input, 2: tolerant, 3: open drain
- parameter int MioPadVariant [NMioPads] = '{default: 0},
- parameter int DioPadVariant [NDioPads] = '{default: 0}
+ parameter logic [1:0][NDioPads-1:0] MioPadVariant = '0,
+ parameter logic [1:0][NDioPads-1:0] DioPadVariant = '0
) (
// pad input
input wire clk_pad_i,
diff --git a/hw/top_earlgrey/rtl/top_earlgrey_asic.sv b/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
index 18e05e3..b2415cf 100644
--- a/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
+++ b/hw/top_earlgrey/rtl/top_earlgrey_asic.sv
@@ -78,8 +78,8 @@
.ConnectDioIn ( 15'h7F63 ),
.ConnectDioOut ( 15'h7F63 ),
// Pad types
- .MioPadVariant ( '{default: 0} ),
- .DioPadVariant ( '{default: 0} )
+ .MioPadVariant ( '0 ),
+ .DioPadVariant ( '0 )
) padring (
// Clk / Rst
.clk_pad_i ( IO_CLK ),
