[dv/flash] add controls to RW & OTF vseqs
Signed-off-by: Eitan Shapira <eitanshapira89@gmail.com>
diff --git a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_base_vseq.sv b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_base_vseq.sv
index 82d8113..501ef4a 100644
--- a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_base_vseq.sv
+++ b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_base_vseq.sv
@@ -463,7 +463,6 @@
uvm_reg_data_t data;
bit [31:0] intr_st;
bit wait_done = 0;
- int prog_timeout_ns = 100000; // 100 us
`uvm_info("flash_ctrl_intr_write", $sformatf("num_wd: %0d crd:%0d", flash_op.num_words,
cfg.wr_crd), UVM_MEDIUM)
@@ -473,7 +472,8 @@
cfg.wr_crd = 4 - curr_wr;
end,
"wait for wr_crd timeout",
- prog_timeout_ns, "flash_ctrl_intr_write")
+ // Defined in the seq_cfg, default is 10ms.
+ cfg.seq_cfg.prog_timeout_ns, "flash_ctrl_intr_write")
flash_ctrl_start_op(flash_op);
@@ -488,7 +488,8 @@
cfg.intr_vif.pins[FlashCtrlIntrProgLvl] == 1 ||
cfg.intr_vif.pins[FlashCtrlIntrOpDone] == 1);,
"wait prog intr timeout",
- prog_timeout_ns, "flash_ctrl_intr_write")
+ // Defined in the seq_cfg, default is 10ms.
+ cfg.seq_cfg.prog_timeout_ns, "flash_ctrl_intr_write")
csr_rd(.ptr(ral.intr_state), .value(data));
intr_st = data;
diff --git a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_otf_base_vseq.sv b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_otf_base_vseq.sv
index f4f25f8..f379478 100644
--- a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_otf_base_vseq.sv
+++ b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_otf_base_vseq.sv
@@ -92,6 +92,13 @@
solve rand_op.addr before rand_op.otf_addr;
solve rand_op.addr before rand_op.num_words;
+ if (cfg.seq_cfg.op_readonly_on_info_partition) {
+ rand_op.partition == FlashPartInfo -> rand_op.op == flash_ctrl_pkg::FlashOpRead;
+ }
+ if (cfg.seq_cfg.op_readonly_on_info1_partition) {
+ rand_op.partition == FlashPartInfo1 -> rand_op.op == flash_ctrl_pkg::FlashOpRead;
+ }
+
rand_op.partition dist { FlashPartData := 1, [FlashPartInfo:FlashPartInfo2] :/ 1};
rand_op.addr[TL_AW-1:BusAddrByteW] == 'h0;
rand_op.addr[1:0] == 'h0;
@@ -436,7 +443,7 @@
`uvm_create_obj(flash_otf_item, exp_item)
exp_item.cmd = flash_op;
- exp_item.dq = flash_program_data;
+ exp_item.dq = cfg.calculate_expected_data(flash_op, flash_program_data);
exp_item.region = my_region;
// Scramble data
exp_item.scramble(otp_addr_key, otp_data_key, flash_op.otf_addr);
diff --git a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_rw_vseq.sv b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_rw_vseq.sv
index c0943df..5402c4e 100644
--- a/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_rw_vseq.sv
+++ b/hw/ip/flash_ctrl/dv/env/seq_lib/flash_ctrl_rw_vseq.sv
@@ -9,6 +9,7 @@
int num, bank;
virtual task body();
+ int otf_wr_pct_temp;
cfg.clk_rst_vif.wait_clks(5);
fork
@@ -22,6 +23,17 @@
end else begin
num = ctrl_info_num;
end
+ // If the partition that selected configured as read-only, skip the program
+ if ((cfg.otf_wr_pct != 0) &&
+ ((cfg.seq_cfg.op_readonly_on_info_partition &&
+ rand_op.partition == FlashPartInfo) ||
+ (cfg.seq_cfg.op_readonly_on_info1_partition &&
+ rand_op.partition == FlashPartInfo1))) begin
+ otf_wr_pct_temp = cfg.otf_wr_pct;
+ cfg.otf_wr_pct = 0;
+ end else begin
+ cfg.otf_wr_pct = otf_wr_pct_temp;
+ end
randcase
cfg.otf_wr_pct:prog_flash(ctrl, bank, num, fractions);
cfg.otf_rd_pct:read_flash(ctrl, bank, num, fractions);
diff --git a/hw/ip/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson b/hw/ip/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson
index d77b0ad..08552a0 100644
--- a/hw/ip/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson
+++ b/hw/ip/flash_ctrl/dv/flash_ctrl_base_sim_cfg.hjson
@@ -213,7 +213,7 @@
{
name: flash_ctrl_rw
uvm_test_seq: flash_ctrl_rw_vseq
- run_opts: ["+scb_otf_en=1"]
+ run_opts: ["+scb_otf_en=1", "+test_timeout_ns=5_000_000_000"]
reseed: 20
}
{
