| commit | 8520647a7e1df72c97c22a20450030bcbf099aa3 | [log] [tgz] |
|---|---|---|
| author | Pirmin Vogel <vogelpi@lowrisc.org> | Thu Oct 01 13:02:22 2020 +0200 |
| committer | Pirmin Vogel <vogelpi@lowrisc.org> | Mon Oct 05 10:56:24 2020 +0200 |
| tree | 7da51473419594742d1bab277916557f88288f65 | |
| parent | bf7659c48fd7987341074f4900b2170c447fb515 [diff] |
[fpga] Reduce the main system clock frequency to 10 MHz This commit lowers the main system clock frequency on FPGA to 10 MHz. Consequently, the peripheral clock frequency derived inside clkmgr is lowered to 2.5 MHz, and the UART baudrate needs to be lowered to 115200 baud. With this change, the FPGA build again meets the timing and thus the timing check for the FPGA build during CI is re-enabled. This resolves lowRISC/OpenTitan#2508. Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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