[doc] Reference SIFA paper in Secure HW Design Guidelines
Signed-off-by: Andreas Kurth <adk@lowrisc.org>
diff --git a/doc/security/implementation_guidelines/hardware/index.md b/doc/security/implementation_guidelines/hardware/index.md
index 0e6b44f..d25afbc 100644
--- a/doc/security/implementation_guidelines/hardware/index.md
+++ b/doc/security/implementation_guidelines/hardware/index.md
@@ -65,7 +65,7 @@
inverted or forced by an adversary. State of the art fault attacks can stimulate
two nodes in close succession; robustness to this type of attack depends on the
declared threat model. Designers need to be well aware of the power of an attack
-like SIFA, which can bypass "conventional" fault countermeasures (e.g.
+like SIFA [[15](#ref-15)], which can bypass "conventional" fault countermeasures (e.g.
redundancy/detectors) and requires only modest numbers of traces.
For increased resistance against side channel leakage (typically: power,
@@ -382,6 +382,9 @@
[<span id="ref-14">14</span>]: Fault Mitigation Patterns -
https://www.riscure.com/uploads/2020/05/Riscure_Whitepaper_Fault_Mitigation_Patterns_final.pdf
+[<span id="ref-15">15</span>]: SIFA: Exploiting Ineffective Fault Inductions on Symmetric Cryptography -
+https://eprint.iacr.org/2018/071.pdf
+
<!-- Footnotes themselves at the bottom. -->
## Notes
