| commit | 8354735c3e8c6f0d63b14a86f9b2cc4da447a7b6 | [log] [tgz] |
|---|---|---|
| author | Timothy Trippel <ttrippel@google.com> | Fri Nov 12 22:25:13 2021 +0000 |
| committer | Miguel Young <mcyoung@google.com> | Tue Nov 16 15:23:08 2021 -0500 |
| tree | b4aadb024f16c7221f47ec388576698deaf4764e | |
| parent | 37b06428a243344ecf00aca1baf9aa2637aa272b [diff] |
[sw/ottf] Fix processing of `mepc` on synchronous IRQ. When an IRQ is fired on RISC-V processors, the PC is stored in the `mepc` register. This address is then used as the return address when the `mret` instruction is called upon returning from an ISR. When the IRQ is synchronous, e.g. an exception, the `mepc` address must be updated to point to the **_next_** instruction **_after_** the instruction that caused the exception, otherwise we will get stuck in a continuous exception cycle. Since we support RISC-V compressed instructions, we must first check whether the faulting instruction is compressed (i.e., 16-bits) or not (i.e., 32-bits) in order to know what offset (2 or 4) to add to the `mepc` before returning from the ISR. Until now, the OTTF ISR handlers assume the trapped instruction was uncompressed. This fixes #9208. Signed-off-by: Timothy Trippel <ttrippel@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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