[rom_ctrl] Instantiate scrambling primitives for rom_ctrl Also update SW build scripts so that we install the scrambled binaries to build-bin as well and update all the documentation examples to show how to use the new filename. Note that we don't update top_englishbreakfast to match: that doesn't have a rom_ctrl, so shouldn't take a scrambled ROM image. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
diff --git a/hw/top_earlgrey/chip_earlgrey_nexysvideo.core b/hw/top_earlgrey/chip_earlgrey_nexysvideo.core index 2836fab..e46352b 100644 --- a/hw/top_earlgrey/chip_earlgrey_nexysvideo.core +++ b/hw/top_earlgrey/chip_earlgrey_nexysvideo.core
@@ -35,14 +35,14 @@ parameters: # XXX: This parameter needs to be absolute, or relative to the *.runs/synth_1 # directory. It's best to pass it as absolute path when invoking fusesoc, e.g. - # --BootRomInitFile=$PWD/build-bin/sw/device/boot_rom/boot_rom_fpga_nexysvideo.32.vmem + # --BootRomInitFile=$PWD/build-bin/sw/device/boot_rom/boot_rom_fpga_nexysvideo.scr.40.vmem # XXX: The VMEM file should be added to the sources of the Vivado project to # make the Vivado dependency tracking work. However this requires changes to # fusesoc first. BootRomInitFile: datatype: str - description: Boot ROM initialization file in 32 bit vmem hex format - default: "../../../../../build-bin/sw/device/boot_rom/boot_rom_fpga_nexysvideo.32.vmem" + description: Scrambled boot ROM initialization file in 40 bit vmem hex format + default: "../../../../../build-bin/sw/device/boot_rom/boot_rom_fpga_nexysvideo.scr.40.vmem" paramtype: vlogparam OtpCtrlMemInitFile: datatype: str
diff --git a/hw/top_earlgrey/chip_earlgrey_verilator.cc b/hw/top_earlgrey/chip_earlgrey_verilator.cc index 7b5856a..348817e 100644 --- a/hw/top_earlgrey/chip_earlgrey_verilator.cc +++ b/hw/top_earlgrey/chip_earlgrey_verilator.cc
@@ -21,9 +21,9 @@ "u_prim_ram_1p_adv.u_mem." "gen_generic.u_impl_generic"); - MemArea rom( - top_scope + ".u_rom_ctrl.u_rom.u_prim_rom.gen_generic.u_impl_generic", - 0x4000 / 4, 4); + MemArea rom(top_scope + (".u_rom_ctrl.u_rom.u_rom." + "u_prim_rom.gen_generic.u_impl_generic"), + 0x4000 / 4, 4); MemArea ram(top_scope + ".u_ram1p_ram_main." + ram1p_adv_scope, 0x20000 / 4, 4); MemArea flash(top_scope +
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index af28623..0336d02 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -5040,6 +5040,26 @@ expose: "true" name_top: RomCtrlBootRomInitFile } + { + name: RndCnstScrNonce + desc: Fixed nonce used for address / data scrambling + type: bit [63:0] + randcount: 64 + randtype: data + name_top: RndCnstRomCtrlScrNonce + default: 0xfc00de9d9734c3fe + randwidth: 64 + } + { + name: RndCnstScrKey + desc: Randomised constant used as a scrambling key for ROM data + type: bit [127:0] + randcount: 128 + randtype: data + name_top: RndCnstRomCtrlScrKey + default: 0x23c074e020fd502869582e71443c8be0 + randwidth: 128 + } ] inter_signal_list: [
diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv index 25ba066..3c9630d 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv
@@ -37,7 +37,7 @@ cfg.flash_bank1_bkdr_vif.set_mem(); // Backdoor load memories with sw images. - cfg.rom_bkdr_vif.load_mem_from_file({cfg.sw_images[SwTypeRom], ".32.vmem"}); + cfg.rom_bkdr_vif.load_mem_from_file({cfg.sw_images[SwTypeRom], ".scr.40.vmem"}); // TODO: the location of the main execution image should be randomized for either bank in future if (cfg.use_spi_load_bootstrap) begin
diff --git a/hw/top_earlgrey/dv/tb/chip_hier_macros.svh b/hw/top_earlgrey/dv/tb/chip_hier_macros.svh index d71592f..cefaa1f 100644 --- a/hw/top_earlgrey/dv/tb/chip_hier_macros.svh +++ b/hw/top_earlgrey/dv/tb/chip_hier_macros.svh
@@ -11,7 +11,7 @@ `define CPU_HIER `CHIP_HIER.u_rv_core_ibex `define RAM_MAIN_HIER `CHIP_HIER.u_ram1p_ram_main.u_prim_ram_1p_adv.u_mem `define RAM_RET_HIER `CHIP_HIER.u_ram1p_ram_ret_aon.u_prim_ram_1p_adv.u_mem -`define ROM_HIER `CHIP_HIER.u_rom_ctrl.u_rom.u_prim_rom +`define ROM_HIER `CHIP_HIER.u_rom_ctrl.u_rom.u_rom.u_prim_rom `define FLASH_HIER `CHIP_HIER.u_flash_eflash.u_flash `define RSTMGR_HIER `CHIP_HIER.u_rstmgr_aon `define CLKMGR_HIER `CHIP_HIER.u_clkmgr_aon
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index 7e7698f..7aac243 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -2274,7 +2274,9 @@ rom_ctrl #( .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[30:30]), - .BootRomInitFile(RomCtrlBootRomInitFile) + .BootRomInitFile(RomCtrlBootRomInitFile), + .RndCnstScrNonce(RndCnstRomCtrlScrNonce), + .RndCnstScrKey(RndCnstRomCtrlScrKey) ) u_rom_ctrl ( // [30]: fatal .alert_tx_o ( alert_tx[30:30] ),
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_rnd_cnst_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_rnd_cnst_pkg.sv index 12dbfc5..01fb60b 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_rnd_cnst_pkg.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_rnd_cnst_pkg.sv
@@ -228,4 +228,17 @@ 256'hA46ED80E5942BC02513FBDFD5A98A66805BC17DDED6CCD3271A3E37A08C92847 }; + //////////////////////////////////////////// + // rom_ctrl + //////////////////////////////////////////// + // Fixed nonce used for address / data scrambling + parameter bit [63:0] RndCnstRomCtrlScrNonce = { + 64'hFC00DE9D9734C3FE + }; + + // Randomised constant used as a scrambling key for ROM data + parameter bit [127:0] RndCnstRomCtrlScrKey = { + 128'h23C074E020FD502869582E71443C8BE0 + }; + endpackage : top_earlgrey_rnd_cnst_pkg
diff --git a/hw/top_earlgrey/util/opentitan_earlgrey_usbdev_pin_config_sim.sh b/hw/top_earlgrey/util/opentitan_earlgrey_usbdev_pin_config_sim.sh index b5a3232..da2c9c4 100755 --- a/hw/top_earlgrey/util/opentitan_earlgrey_usbdev_pin_config_sim.sh +++ b/hw/top_earlgrey/util/opentitan_earlgrey_usbdev_pin_config_sim.sh
@@ -7,7 +7,7 @@ VERILATOR=build/lowrisc_systems_chip_earlgrey_verilator_0.1/sim-verilator/Vchip_earlgrey_verilator # Code to load -ROMCODE=build-bin/sw/device/boot_rom/boot_rom_sim_verilator.elf +ROMCODE=build-bin/sw/device/boot_rom/boot_rom_sim_verilator.scr.40.vmem FLASH=build-bin/sw/device/examples/hello_usbdev/hello_usbdev_sim_verilator.elf OTP=build-bin/sw/device/otp_img/otp_img_sim_verilator.vmem