[dv] Add cip_lc_tx_cov_if to sample lc_esc coverage
lc_tx_t On/Off value are different than mubi4, so need to create another
interface
Signed-off-by: Weicai Yang <weicai@google.com>
diff --git a/hw/dv/sv/cip_lib/cip_lc_tx_cov_if.sv b/hw/dv/sv/cip_lib/cip_lc_tx_cov_if.sv
new file mode 100644
index 0000000..fb8d67e
--- /dev/null
+++ b/hw/dv/sv/cip_lib/cip_lc_tx_cov_if.sv
@@ -0,0 +1,20 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+interface cip_lc_tx_cov_if(input [3:0] val, input rst_ni);
+ import uvm_pkg::*;
+ import dv_base_reg_pkg::*;
+
+ typedef mubi_cov #(.Width(4),
+ .ValueTrue(lc_ctrl_pkg::On),
+ .ValueFalse(lc_ctrl_pkg::Off)) lc_tx_cov;
+ lc_tx_cov cov;
+ initial begin
+ cov = lc_tx_cov::type_id::create($sformatf("%m"));
+ forever begin
+ @(val or rst_ni);
+ if (rst_ni === 1) cov.sample(val);
+ end
+ end
+endinterface
diff --git a/hw/dv/sv/cip_lib/cip_lib.core b/hw/dv/sv/cip_lib/cip_lib.core
index 0ba06d8..3eee861 100644
--- a/hw/dv/sv/cip_lib/cip_lib.core
+++ b/hw/dv/sv/cip_lib/cip_lib.core
@@ -35,6 +35,7 @@
- seq_lib/cip_tl_host_single_seq.sv: {is_include_file: true}
- cip_base_test.sv: {is_include_file: true}
- cip_mubi_cov_if.sv
+ - cip_lc_tx_cov_if.sv
file_type: systemVerilogSource
targets:
