| commit | 3907dd0b10184d8bb94b0c9f99f5953dd001f352 | [log] [tgz] |
|---|---|---|
| author | Eunchan Kim <eunchan@opentitan.org> | Sat May 22 00:15:58 2021 -0700 |
| committer | Eunchan Kim <eunchan@opentitan.org> | Mon May 24 14:31:58 2021 -0700 |
| tree | bfa6f9590cb86c2f59956e679f33c681a5ced53e | |
| parent | fca43823ad5c0c2bb9a96158d85086ab630c819c [diff] |
[hmac] Idle logic This commit implements the idle signal. Idle signal is used in the clkmgr to ensure the safe clock off by checking the logic's idle status. HMAC implements the idle logic by checking four submodules' idle status: - packer: packer does not have empty status signal sending out. So, currently, the logic relies on the fifo valid out signal. However, the case that packer has partial data and not sending out the write signal is covered by HMAC_CORE or SHA_CORE idle signals. - msg_fifo: fifo_wvalid output signal is used as an idle signal. - HMAC_CORE: the core raises an idle signal when the core sits in the Idle state or HMAC mode is not set. - SHA_CORE: If the FIFO FSM sits in Idle state, SHA core is in idle. SHA state machine is dependent on the Fifo FSM. This is related to #6650 Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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