| commit | 82c66a1a75469252b87085d5ef907a27fb4f5bab | [log] [tgz] |
|---|---|---|
| author | Udi Jonnalagadda <udij@google.com> | Wed Apr 28 16:59:14 2021 -0700 |
| committer | udinator <udij@google.com> | Thu Apr 29 13:09:59 2021 -0700 |
| tree | 3c28783b0c2e1db27a07a405489c3b4a5eb820ee | |
| parent | 22117a9bdda2e2dfb5509d89a01299687942013c [diff] |
[dv/kmac] cycle-accurate model bugfixes - pt 2 this PR fixes some issues in the cycle accurate model: - data overflow during msgfifo flushing - use a nonblocking forked process to update fifo_empty interrupt as if it is blocking we can miss updates to the fifo pointers and cause weird errors later in simulation - fix looping wait if fifo fills up when not using kmac_app interface, which would cause premature failures Signed-off-by: Udi Jonnalagadda <udij@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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